JP7308593B2 - Nitride semiconductor device - Google Patents

Description

The present invention relates to a nitride semiconductor device made of a Group III nitride semiconductor (hereinafter sometimes simply referred to as "nitride semiconductor").

A group III nitride semiconductor is a semiconductor in which nitrogen is used as a group V element in a group III-V semiconductor. Aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are representative examples. In general, it can be expressed as _{AlxInyGa1 -x-yN} (0≤x≤1, 0≤y≤1, 0≤x+y≤1) _.
A HEMT (High Electron Mobility Transistor) using such a nitride semiconductor has been proposed. Such a HEMT includes, for example, an electron transit layer made of GaN and an electron supply layer made of AlGaN epitaxially grown on the electron transit layer. A pair of source and drain electrodes are formed in contact with the electron supply layer, and a gate electrode is arranged therebetween. Due to polarization caused by lattice mismatch between GaN and AlGaN, a two-dimensional electron gas is formed in the electron transit layer at a position several angstroms inward from the interface between the electron transit layer and the electron supply layer. . Using this two-dimensional electron gas as a channel, the source and the drain are connected. When a control voltage is applied to the gate electrode to cut off the two-dimensional electron gas, the connection between the source and the drain is cut off. When no control voltage is applied to the gate electrode, the source-drain is conductive, so the device is a normally-on type device.

Devices using nitride semiconductors have features such as high withstand voltage, high temperature operation, large current density, high-speed switching and low on-resistance, and their application to power devices has been investigated.
However, in order to use it as a power device, it must be a normally-off type device that cuts off current at zero bias.

A structure for realizing a normally-off nitride semiconductor HEMT is proposed in Patent Document 1, for example.

JP-A-2006-339561

In Patent Document 1, a p-type GaN gate layer (nitride semiconductor gate layer) is stacked on an AlGaN electron supply layer, a gate electrode is arranged thereon, and a depletion layer spreading from the p-type GaN gate layer eliminates the channel. Thus, a configuration is disclosed that achieves normally-off. In Patent Document 1, a gate electrode made of Pd (palladium) that forms an ohmic contact with a p-type GaN gate layer is used as the gate electrode.

As the gate electrode, it is conceivable to use a gate electrode made of metal such as TiN (titanium nitride) that forms a Schottky junction with the p-type GaN gate layer. A nitride semiconductor device having such a configuration may be referred to as a comparative device. In the comparison target device, since the nitride semiconductor gate layer and the gate electrode form a Schottky junction, the gate leak current increases and the nitride semiconductor gate layer is likely to deteriorate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device capable of reducing a gate leakage current as compared with a comparative device.

A nitride semiconductor device according to one embodiment of the present invention includes a first nitride semiconductor layer forming an electron transit layer, and a layer formed on the first nitride semiconductor layer and having a higher band than the first nitride semiconductor layer. a second nitride semiconductor layer having a large gap and forming an electron supply layer; and a gate portion disposed on the second nitride semiconductor layer, wherein the gate portion is on the second nitride semiconductor layer. It includes a nitride semiconductor gate layer disposed and containing an acceptor-type impurity, a gate insulating film formed on the nitride semiconductor gate layer, and a gate electrode formed on the gate insulating film.

In this configuration, since the gate insulating film is interposed between the nitride semiconductor gate layer and the gate electrode, the gate leakage current can be reduced as compared with the comparative device.
In _one embodiment of the present invention, the gate insulating film is made of one selected from SiN, _SiO2 , SiON, _Al2O3 , AlN, AlON, HfO, HfN, HfON, HfSiON and AlON. ing.

In one embodiment of the present invention, the gate insulating film is made of in-situ SiN deposited in-situ with the nitride semiconductor gate layer.
In one embodiment of the invention, the gate leakage current is 1 nA/mm or less.
In one embodiment of the present invention, the film thickness of the nitride semiconductor gate layer is 100 nm or less, and the film thickness of the gate insulating film is 3 nm or more.

In one embodiment of the present invention, the semiconductor device further includes a third nitride semiconductor layer that is arranged on the side of the first nitride semiconductor layer opposite to the second nitride semiconductor layer and that constitutes a buffer layer.
In one embodiment of the present invention, the carbon concentration at the interface between the nitride semiconductor gate layer and the gate insulating film is 1×10 ¹³ cm ⁻² or less.
In one embodiment of the present invention, the first nitride semiconductor layer is a GaN layer, the second nitride semiconductor layer is an AlGaN layer, and the nitride semiconductor gate layer is a p-type GaN layer.

In one embodiment of the present invention, the first nitride semiconductor layer is a GaN layer, the second nitride semiconductor layer is an AlGaN layer, the nitride semiconductor gate layer is a p-type GaN layer, and the third nitride semiconductor layer is a p-type GaN layer. The nitride semiconductor layer consists of an AlGaN layer.
In one embodiment of this invention, said acceptor-type impurity is magnesium or iron.

A nitride semiconductor device according to one embodiment of the present invention includes a first nitride semiconductor layer forming an electron transit layer, and a layer formed on the first nitride semiconductor layer and having a higher band than the first nitride semiconductor layer. a second nitride semiconductor layer having a large gap and forming an electron supply layer; and a gate portion disposed on the second nitride semiconductor layer, wherein the gate portion is on the second nitride semiconductor layer. a nitride semiconductor gate layer disposed and containing an acceptor-type impurity; a nitrogen-containing layer containing nitrogen formed on the nitride semiconductor gate layer; and a gate electrode disposed on the nitrogen-containing layer.

In one embodiment of the invention, the nitrogen-containing layer has a thickness of 10 nm or less.
In one embodiment of the present invention, the nitrogen-containing layer is composed of a single film of AlN film or SIN film, or a laminated film of AlN film and SIN film.
In one embodiment of the invention, the nitrogen-containing layer comprises an AlN film formed on the nitride semiconductor gate layer and an SIN film formed on the AlN film.

One embodiment of the present invention further includes a gate insulating film formed between the nitrogen-containing layer and the gate electrode.
In one embodiment of the present invention, the gate insulating film is made of an insulating film containing oxygen.
In one embodiment of _the present invention, the gate insulating film is made of _Al2O3 film or _SiO2 film.

In one embodiment of the invention, the gate leakage current is 1 nA/mm or less.

FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to a first embodiment of the invention. FIG. 2A is a cross-sectional view showing an example of the manufacturing process of the nitride semiconductor device. FIG. 2B is a cross-sectional view showing the next step of FIG. 2A. FIG. 2C is a cross-sectional view showing the next step of FIG. 2B. FIG. 2D is a cross-sectional view showing the next step of FIG. 2C. FIG. 2E is a cross-sectional view showing the next step of FIG. 2D. FIG. 2F is a cross-sectional view showing the next step of FIG. 2E. FIG. 2G is a cross-sectional view showing the next step of FIG. 2F. FIG. 3 is a cross-sectional view showing the configuration of a nitride semiconductor device according to a first comparative example. FIG. 4 is an energy band diagram showing the energy distribution of the first comparative example. FIG. 5 is an electric field strength distribution diagram showing the electric field strength distribution of the first comparative example. FIG. 6 is an energy band diagram showing the energy distribution of this embodiment. FIG. 7 is an electric field intensity distribution diagram showing the electric field intensity distribution of this embodiment. FIG. 8 is an energy band diagram showing energy distribution when the gate insulating film is made of SiO ₂ . FIG. 9 is an electric field strength distribution diagram showing the electric field strength distribution when the gate insulating film is made of SiO ₂ . FIG. 10 is a cross-sectional view for explaining the configuration of the nitride semiconductor device according to the second embodiment of the invention. 11 is an enlarged sectional view of the gate portion of FIG. 10. FIG. FIG. 12 is an enlarged cross-sectional view showing a first modification of the gate portion of the second embodiment. FIG. 13 is an enlarged cross-sectional view showing a second modification of the gate portion of the second embodiment. FIG. 14 is a graph showing high temperature gate bias test results when the gate voltage Vg is set to 5V. FIG. 14 is a graph showing high temperature gate bias test results when the gate voltage Vg is set to -3V.

BEST MODE FOR CARRYING OUT THE INVENTION Below, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view for explaining the configuration of a nitride semiconductor device according to a first embodiment of the invention.
Nitride semiconductor device 1 includes substrate 2 , buffer layer 3 formed on the surface of substrate 2 , first nitride semiconductor layer 4 epitaxially grown on buffer layer 3 , and and a second nitride semiconductor layer 5 epitaxially grown. Further, nitride semiconductor device 1 includes a gate portion 20 formed on second nitride semiconductor layer 5 .

Further, nitride semiconductor device 1 includes passivation film 9 covering second nitride semiconductor layer 5 and gate portion 20 , and barrier metal film 10 laminated on passivation film 9 . Further, in the nitride semiconductor device 1, the second nitride semiconductor layer 5 is formed through the source electrode contact hole 11 and the drain electrode contact hole 12 formed in the laminated film of the passivation film 9 and the barrier metal film 10. It includes a source electrode 13 and a drain electrode 14 in ohmic contact with each other. The source electrode 13 and the drain electrode 14 are spaced apart. Source electrode 13 is formed to cover gate portion 20 . Further, nitride semiconductor device 1 includes interlayer insulating film 15 covering source electrode 13 and drain electrode 14 .

Substrate 2 may be, for example, a low resistance silicon substrate. A low-resistance silicon substrate may have an impurity concentration of, for example, 1×10 ¹⁷ cm ⁻³ to 1×10 ²⁰ cm ⁻³ (more specifically, about 1×10 ¹⁸ cm ⁻³ ). The substrate 2 may be a low-resistance silicon substrate, a low-resistance GaN substrate, a low-resistance SiC substrate, or the like. The thickness of the substrate 2 is approximately 650 μm.

In this embodiment, the buffer layer 3 is composed of a multi-layered buffer layer in which a plurality of nitride semiconductor films are laminated. In this embodiment, the buffer layer 3 includes a first buffer layer 3A made of an AlN film in contact with the surface of the substrate 2, and an AlGaN layer laminated on the surface of the first buffer layer 3A (the surface opposite to the substrate 2). and a second buffer layer 3B made of a film. The film thickness of the first buffer layer 3A is approximately 100 nm to 300 nm. The film thickness of the second buffer layer 3B is approximately 100 nm to 5 μm.

The first nitride semiconductor layer 4 constitutes an electron transit layer. In this embodiment, the first nitride semiconductor layer 4 is made of a GaN layer doped with acceptor-type impurities and has a thickness of about 100 nm to 5 μm. The acceptor-type impurity concentration is preferably 4×10 ¹⁶ cm ⁻³ or higher. In this embodiment, the acceptor-type impurity is C (carbon).
The second nitride semiconductor layer 5 constitutes an electron supply layer. The second nitride semiconductor layer 5 is made of a nitride semiconductor having a bandgap larger than that of the first nitride semiconductor layer 4 . Specifically, the second nitride semiconductor layer 5 is made of a nitride semiconductor having a higher Al composition than the first nitride semiconductor layer 4 . In nitride semiconductors, the higher the Al composition, the larger the bad gap. In this embodiment, the second nitride semiconductor layer 5 is an Al _x1 Ga _1-x1 N layer (0<x1<1) and has a thickness of about 10 nm to 30 nm.

Thus, the first nitride semiconductor layer 4 (electron transit layer) and the second nitride semiconductor layer 5 (electron supply layer) are made of nitride semiconductors having different band gaps (Al composition). has lattice mismatch. Then, the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 are polarized by the spontaneous polarization of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 and the piezoelectric polarization caused by the lattice mismatch therebetween. The energy level of the conduction band of the first nitride semiconductor layer 4 at the interface with is lower than the Fermi level. As a result, the two-dimensional electron gas (2DEG) 16 spreads at a position near the interface between the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 (for example, a distance of several angstroms from the interface).

The gate portion 20 is formed on the nitride semiconductor gate layer 6 epitaxially grown on the second nitride semiconductor layer 5 , the gate insulating film 7 formed on the nitride semiconductor gate layer 6 , and the gate insulating film 7 . and a gate electrode 8 . The nitride semiconductor gate layer 6 is made of a nitride semiconductor doped with an acceptor-type impurity. In this embodiment, the nitride semiconductor gate layer 6 is made of a GaN layer (p-type GaN layer) doped with an acceptor-type impurity, and has a thickness of about 10 nm to 100 nm. The film thickness of nitride semiconductor gate layer 6 is preferably 100 nm or less. The reason for this will be described later. In this embodiment, the film thickness of the nitride semiconductor gate layer 6 is 60 nm.

The concentration of the acceptor-type impurity implanted into nitride semiconductor gate layer 6 is preferably 3×10 ¹⁷ cm ⁻³ or higher. In this embodiment, the acceptor-type impurity is Mg (magnesium). The acceptor-type impurity may be an acceptor-type impurity other than Mg, such as Fe. In the nitride semiconductor gate layer 6, two-dimensional electrons generated at the interface between the first nitride semiconductor layer 4 (electron transit layer) and the second nitride semiconductor layer 5 (electron supply layer) in the region immediately below the gate portion 20 It is provided to offset gas 16 . The surface (upper surface) of the nitride semiconductor gate layer 6 is the c-plane of the GaN crystal, and the side surface of the nitride semiconductor gate layer 6 is the m-plane of the GaN crystal.

Gate insulating film 7 is formed in contact with the surface (c-plane) of nitride semiconductor gate layer 6 . The gate insulating film 7 is made of in-situ SiN formed in-situ with the nitride semiconductor gate layer 6 in this embodiment. The thickness of the gate insulating film 7 is about 3 nm to 30 nm. The film thickness of the gate insulating film 7 is preferably 3 nm or more. In this embodiment, the film thickness of the gate insulating film 7 is 30 nm. The gate insulating film 7 is made of SiN (excluding in-situ SiN), SiO ₂ , SiON, Al ₂ O ₃ , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, etc., in addition to in-situ SiN. may

In this embodiment, the carbon concentration at the interface between the nitride semiconductor gate layer 6 and the gate insulating film 7 is 1×10 ¹³ cm ⁻² or less.
Gate electrode 8 is formed in contact with the surface of gate insulating film 7 . In this embodiment, the gate electrode 8 is composed of a TiN layer and has a thickness of approximately 50 nm to 200 nm. The gate electrode 8 is biased toward the source electrode contact hole 11 .

Passivation film 9 covers the surface of second nitride semiconductor layer 5 (excluding regions facing contact holes 11 and 12 ) and the side surface and surface of gate portion 20 . In this embodiment, the passivation film 9 is made of SiN film and has a thickness of about 50 nm to 200 nm. In this embodiment, the passivation film 9 has a thickness of 50 nm.
A barrier metal film 10 is laminated on the passivation film 9 . In this embodiment, the barrier metal film 10 is made of a TiN film and has a thickness of about 10 nm to 50 nm. In this embodiment, the barrier metal film 10 has a thickness of 25 nm.

In this embodiment, the source electrode 13 and the drain electrode 14 are composed of lower layers (ohmic metal layers) 13A and 14A in contact with the second nitride semiconductor layer 5 and intermediate layers (main electrode metal layers) stacked on the lower layers 13A and 14A. 13B, 14B and upper layers (barrier metal layers) 13C, 14C laminated on the intermediate layers 13B, 14B. The lower layers 13A and 14A are, for example, Ti layers with a thickness of about 10 nm to 20 nm. The intermediate layers 13B and 14B are Al layers with a thickness of about 100 nm to 300 nm. The upper layers 13C and 14C are, for example, TiN with a thickness of about 10 nm to 50 nm.

The interlayer insulating film 15 is made of _SiO2 , for example. The thickness of the interlayer insulating film 15 is about 1 μm.
In this nitride semiconductor device 1, a second nitride semiconductor layer 5 (electron supply layer) having a different bandgap (Al composition) is formed on a first nitride semiconductor layer 4 (electron transit layer) to form a heterojunction. It is As a result, the two-dimensional electron gas 16 is formed in the first nitride semiconductor layer 4 near the interface between the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5, and the two-dimensional electron gas 16 is used as a channel. A utilized HEMT is formed. Gate electrode 8 faces second nitride semiconductor layer 5 with gate insulating film 7 and nitride semiconductor gate layer 6 composed of a p-type GaN layer interposed therebetween.

Below the gate electrode 8, the energy levels of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 are raised by ionized acceptors contained in the nitride semiconductor gate layer 6 made of the p-type GaN layer. The energy level of the conduction band at the heterojunction interface is higher than the Fermi level. Therefore, immediately below the gate electrode 8 (gate portion 20), the two-dimensional electron gas 16 originates from the spontaneous polarization of the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 and the piezoelectric polarization due to their lattice mismatch. not formed. Therefore, when no bias is applied to the gate electrode 8 (at zero bias), the channel formed by the two-dimensional electron gas 16 is blocked immediately below the gate electrode 8 . Thus, a normally-off HEMT is realized. When an appropriate on-voltage (for example, 3 V) is applied to the gate electrode 8, a channel is induced in the first nitride semiconductor layer 4 immediately below the gate electrode 8, connecting the two-dimensional electron gas 16 on both sides of the gate electrode 8. be. This allows conduction between the source and the drain.

During use, for example, a predetermined voltage (for example, 200 V to 300 V) is applied between the source electrode 13 and the drain electrode 14 such that the drain electrode 14 side is positive. In this state, an off voltage (0 V) or an on voltage (3 V) is applied to the gate electrode 8 with the source electrode 13 as a reference potential (0 V).
2A to 2G are cross-sectional views for explaining an example of the manufacturing process of nitride semiconductor device 1 described above, showing cross-sectional structures at a plurality of stages in the manufacturing process.

First, as shown in FIG. 2A, a buffer layer 3 and a first nitride semiconductor layer (electron transit layer) 4 are epitaxially grown in this order on a substrate 2 by MOCVD (Metal Organic Chemical Vapor Deposition). Furthermore, a second nitride semiconductor layer (electron supply layer) 5 is epitaxially grown on the first nitride semiconductor layer 4 by MOCVD.

Next, as shown in FIG. 2B, a gate layer material film 31, which is a material film of the nitride semiconductor gate layer 6, is formed on the second nitride semiconductor layer 5 by MOCVD. Next, an insulating material film 32 which is a material film of the gate insulating film 7 is formed on the gate layer material film 31 . When the gate insulating film 7 is made of SiN as in the above embodiment, the insulating material film 32 can be formed by the same MOCVD apparatus following the formation of the gate layer material film 31 . In this case, the insulating material film 32 is in-situ SiN formed in-situ with the gate layer material film 31 .

When the gate insulating film 7 is SiN, the insulating material film 32 can be formed on the gate layer material film 31 by plasma CVD. Further, when the gate insulating film 7 is composed of an insulating material other than SiN such as SiO ₂ , the gate layer material film is formed by plasma CVD, LPCVD (Low Pressure CVD), ALD (Atomic Layer Deposition), or the like. An insulating material film 32 can be deposited on 31 .

Thereafter, a gate electrode film 33, which is a material film of the gate electrode 8, is formed on the insulating material film 32 by sputtering or vapor deposition. The gate electrode film 33 is made of, for example, a TiN metal film.
Next, as shown in FIG. 2C, a resist film 34 is formed to cover the gate electrode forming region on the surface of the gate electrode film 33 . Using the resist film 34 as a mask, the gate electrode film 33, the insulating material film 32 and the gate layer material film 31 are selectively etched.

Thereby, the gate electrode film 33 is patterned and the gate electrode 8 is obtained. Also, the insulating material film 32 and the gate layer material film 31 are patterned in the same pattern as the gate electrode 8 . In this way, the gate portion 20 composed of the nitride semiconductor gate layer 6 , the gate insulating film 7 and the gate electrode 8 is formed on the second nitride semiconductor layer 5 .
Next, the resist film 34 is removed. Thereafter, as shown in FIG. 2D, a passivation film 9 is formed by plasma CVD or LPCVD to cover the entire exposed surface. A barrier metal film 10 is formed on the surface of the passivation film 9 by sputtering. Passivation film 9 is made of, for example, a SiN layer. Barrier metal film 10 is made of, for example, a TiN layer.

Next, as shown in FIG. 2E, a source electrode contact hole 11 and a drain electrode contact hole 12 are formed in the laminated film of the passivation film 9 and the barrier metal film 10 .
Next, as shown in FIG. 2F, a source/drain electrode film 35 is formed to cover the entire exposed surface. The source/drain electrode film 35 is composed of a laminated metal film in which a Ti layer 35A as a lower layer, an Al layer 35B as an intermediate layer, and a TiN layer 35C as an upper layer are laminated, and is formed by sequentially vapor-depositing each layer.

Next, as shown in FIG. 2G, the source/drain electrode film 35 is patterned by etching and then annealed to form the source electrode 13 and the drain electrode 14 in ohmic contact with the second nitride semiconductor layer 5. is formed. At this time, the source electrode 13 is composed of a lower layer 13A made of a Ti layer 35A, an intermediate layer 13B made of an Al layer 35B, and an upper layer 13C made of a TiN layer 35C. The drain electrode 14 is composed of a lower layer 14A made of a Ti layer 35A, an intermediate layer 14B made of an Al layer 35B, and an upper layer 14C made of a TiN layer 35C.

Thereafter, interlayer insulating film 15 is formed to cover source electrode 13 and drain electrode 14, thereby obtaining nitride semiconductor device 1 having the structure shown in FIG.
Hereinafter, a nitride semiconductor device having a configuration in which the gate insulating film 7 is not provided in contrast to the nitride semiconductor device 1 of FIG. 1 will be referred to as a first comparative example. FIG. 3 is a cross-sectional view showing the configuration of a nitride semiconductor device 101 according to a first comparative example. In the nitride semiconductor device 101 according to the first comparative example, the gate portion 20 includes the nitride semiconductor gate layer 6 formed on the second nitride semiconductor layer 5 and the gate formed on the nitride semiconductor gate layer 6. an electrode 8; In the first comparative example, a gate electrode 8 made of TiN is Schottky-junctioned to a nitride semiconductor gate layer 6 made of p-type GaN. The film thickness of the nitride semiconductor gate layer 6 of the first comparative example is 80 nm. The film thickness of the nitride semiconductor gate layer 6 of the nitride semiconductor device 1 described above is 60 nm, and the film thickness of the gate insulating film 7 is 30 nm.

In the nitride semiconductor device 101 according to the first comparative example, since the gate electrode 8 is in Schottky junction with the nitride semiconductor gate layer 6, the gate leakage current is large. Therefore, nitride semiconductor gate layer 6 is likely to deteriorate.
In the nitride semiconductor device 1 according to the above-described embodiment (hereinafter referred to as the first example), the gate insulating film 7 is formed on the nitride semiconductor gate layer 6, and the gate electrode 8 is formed on the gate insulating film 7. It is That is, in the first embodiment, since the gate insulating film 7 is interposed between the nitride semiconductor gate layer 6 and the gate electrode 8, the gate leakage current can be reduced as compared with the first comparative example. . This makes it difficult for nitride semiconductor gate layer 6 to deteriorate. In the first example, the gate leak current is 1 nA/mm or less.

Further, as will be described later, in the first example, the threshold voltage Vth can be made higher than in the first comparative example. In addition, in the first example, the nitride semiconductor gate layer 6 can be made thinner than in the first comparative example. Time dependent dielectric breakdown (TDDB) of 6 is less likely to occur. Furthermore, in the first example, the threshold voltage Vth can be stabilized as compared with the first comparative example.

In the first example, the reason why the threshold voltage Vth can be made higher than that of the first comparative example and the reason why the nitride semiconductor gate layer 6 can be thinner than that of the first comparative example will be explained.
FIG. 4 is an energy band diagram showing the energy distribution of the first comparative example. FIG. 5 is an electric field strength distribution diagram showing the electric field strength distribution of the first comparative example. 4 and 5, GaN indicates the first nitride semiconductor layer 4, AlGaN indicates the second nitride semiconductor layer 5, P-GaN indicates the nitride semiconductor gate layer 6, and Metal indicates the gate electrode 8. is shown. In FIG. 4, E _C is the conduction band energy level, E _V is the valence band energy level, and E _F is the Fermi level.

In the first comparative example, the gate electrode 8 is Schottky-junctioned with the nitride semiconductor gate layer 6 . A potential barrier (Schottky barrier) _ΦB at the interface between the gate electrode 8 and the nitride semiconductor gate layer 6 affects the threshold voltage Vth.
In the example of FIG. 4, the threshold voltage Vth is 2 [V]. Since the threshold voltage Vth of a nitride semiconductor device is smaller than that of a Si semiconductor device, it is important to increase the threshold voltage Vth. In order to increase the threshold voltage Vth in the first comparative example, it is necessary to increase the film thickness of the nitride semiconductor gate layer 6 . Since Mg and Fe, which are acceptors of p-GaN, have a memory effect, as can be seen from FIG. It becomes higher as it approaches the boundary with the electrode 8 . In addition, the nitride semiconductor has a smaller permissible electric field strength than the insulating film. Therefore, the thickness of the nitride semiconductor gate layer 6 cannot be increased, and it is difficult to increase the threshold voltage Vth. The film thickness of nitride semiconductor gate layer 6 is usually set to 100 nm or less.

FIG. 6 is an energy band diagram showing the energy distribution of the first embodiment. FIG. 7 is an electric field intensity distribution diagram showing the electric field intensity distribution of this embodiment. 6 and 7, GaN indicates the first nitride semiconductor layer 4, AlGaN indicates the second nitride semiconductor layer 5, P-GaN indicates the nitride semiconductor gate layer 6, and SiN indicates the gate insulating film 7. , and Metal indicates the gate electrode 8 . In FIG. 6, E _C is the conduction band energy level, E _V is the valence band energy level, and E _F is the Fermi level.

In the first embodiment, gate insulating film 7 is formed on nitride semiconductor gate layer 6 . The electric field intensity distribution inside the gate insulating film 7 is uniform, and even if the gate insulating film 7 is thickened, the electric field intensity does not increase. Therefore, in the first example, the film thickness of the nitride semiconductor gate layer 6 is made thinner than the film thickness of the nitride semiconductor gate layer 6 of the first comparative example (thus, the gate insulating film 7 is formed to have a thickness of 1000 nm from the gate electrode 8). The threshold voltage Vth can be made high (3 [V] in FIG. 6) while maintaining a small electric field strength at the boundary).

In the first embodiment, since the threshold voltage Vth can be increased by forming the gate insulating film 7 on the nitride semiconductor gate layer 6, the film thickness of the nitride semiconductor gate layer 6 is increased to increase the threshold voltage Vth. No need to thicken. Therefore, in the first example, the film thickness of the nitride semiconductor gate layer 6 is made thinner than in the first comparative example. As a result, as shown in FIG. 7, the electric field intensity at the boundary between the nitride semiconductor gate layer 6 of the first example and the gate insulating film 7 is the same as that of the gate electrode of the nitride semiconductor gate layer 6 of the first comparative example. Since the electric field intensity at the boundary with 8 is reduced, in the first example, the time-dependent dielectric breakdown (TDDB) of the nitride semiconductor gate layer 6 is less likely to occur than in the first comparative example.

In the first embodiment, the field strength at the boundary between the gate electrode 8 and the gate insulating film 7 is higher than the field strength at the boundary between the gate insulating film 7 and the nitride semiconductor gate layer 6 . Since the dielectric breakdown voltage of the gate insulating film 7 is higher than that of the nitride semiconductor gate layer 6, there is no problem.
Next, the reason why the threshold voltage Vth can be stabilized in the first example as compared with the first comparative example will be described.

Since the nitride semiconductor gate layer 6 made of p-type GaN is a polarizable material, polarization charges appear on its surface (c-plane). In the manufacturing process of the nitride semiconductor device, when the surface of the nitride semiconductor gate layer 6 is exposed to the atmosphere, polar organic molecules (carboxylic acid, siloxy acid, etc.) in the atmosphere cancel the polarization charges on the surface. Adheres to surfaces.
In the first comparative example, after forming a material film (gate layer material film) for the nitride semiconductor gate layer 6 by a CVD device, a material film (gate electrode film) for the gate electrode is formed on the gate layer material film by a sputtering device. be done. As a result, the surface of nitride semiconductor gate layer 6 is exposed to the atmosphere, and organic molecules in the atmosphere adhere to the surface. As a result, the size of the Schottky barrier _ΦB fluctuates and the threshold voltage Vth becomes unstable.

On the other hand, in the first embodiment, after the material film (gate layer material film 31) of the nitride semiconductor gate layer 6 is formed by the MOCVD apparatus, an in-layer film is subsequently formed on the gate layer material film 31 by the same MOCVD apparatus. A material film (insulating material film 32) of the gate insulating film 7 made of in situ SiN is formed. Therefore, in the manufacturing process of nitride semiconductor device 1, the surface (c-plane) of nitride semiconductor gate layer 6 is not exposed to the atmosphere. Therefore, in the first example, organic molecules are less likely to adhere to the surface (c-plane) of the nitride semiconductor gate layer 6 than in the first comparative example. Thus, in the first example, the potential barrier _ΦB at the interface between the gate electrode 8 and the gate insulating film 7 is stabilized, and the threshold voltage Vth is stabilized, as compared with the first comparative example.

When the insulating material film 32 is made of a material other than in-situ SiN, such as SiO ₂ , after forming the material film (gate layer material film 31) of the nitride semiconductor gate layer 6 by MOCVD, the surface will be exposed to the atmosphere. In this case, by heating the gate layer material film 31 to 400° C. or higher in an insulating film forming device such as a plasma CVD device, an LPCVD device, or an ALD device, the organic matter adhering to the surface of the gate layer material film 31 is removed. After removing the molecules, the insulating material film 32 may be formed.

8 and 9 show the energy distribution and electric field intensity distribution when the gate insulating film 7 is made of SiO ₂ . In the examples of FIGS. 8 and 9, the thickness of the gate insulating film (SiO ₂ ) 7 is 30 nm, and the thickness of the nitride semiconductor gate layer (p-GaN) 6 is 50 nm.
FIG. 10 is a cross-sectional view for explaining the configuration of the nitride semiconductor device according to the second embodiment of the invention. 11 is an enlarged sectional view of the gate portion of FIG. 10. FIG. In FIG. 10, the same reference numerals as in FIG. 1 denote the parts corresponding to the parts in FIG. 1 described above.

A nitride semiconductor device 1A according to the second embodiment differs from that of the first embodiment in the structure of the gate portion. Other points are the same as those of the nitride semiconductor device 1 according to the first embodiment.
The structure of the gate portion 20A of the nitride semiconductor device 1A according to the second embodiment will be described below.
Gate portion 20A includes nitride semiconductor gate layer 6 epitaxially grown on second nitride semiconductor layer 5, nitrogen-containing layer 50 containing nitrogen formed on nitride semiconductor gate layer 6, and nitrogen-containing layer 51. and a gate electrode 8 formed on the gate insulating film 7 .

The nitride semiconductor gate layer 6 is made of a nitride semiconductor doped with an acceptor-type impurity. In this embodiment, the nitride semiconductor gate layer 6 is made of a GaN layer (p-type GaN layer) doped with an acceptor-type impurity, and has a thickness of about 10 nm to 100 nm. The film thickness of nitride semiconductor gate layer 6 is preferably 100 nm or less. In this embodiment, the film thickness of the nitride semiconductor gate layer 6 is 60 nm.

The concentration of the acceptor-type impurity implanted into nitride semiconductor gate layer 6 is preferably 3×10 ¹⁷ cm ⁻³ or more. In this embodiment, the acceptor-type impurity is Mg (magnesium). The acceptor-type impurity may be an acceptor-type impurity other than Mg, such as Fe.
In this embodiment, the nitrogen-containing layer 50 is a laminated film of an AlN film 51 formed on the nitride semiconductor gate layer 6 and a SiN film laminated on the AlN film 51 . The film thickness of the nitrogen-containing layer 50 is preferably 10 nm or less. In this embodiment, the AlN film 51 has a thickness of about 2 nm, and the SiN film 52 has a thickness of about 5 nm.

Gate insulating film 7 is formed in contact with the surface of nitrogen-containing layer 50 . The gate insulating film 7 is made of SiO ₂ in this embodiment. The thickness of the gate insulating film 7 is about 3 nm to 30 nm. The film thickness of the gate insulating film 7 is preferably 3 nm or more. In this embodiment, the film thickness of the gate insulating film 7 is 30 nm. The gate insulating film 7 may be made of Al ₂ O ₃ , SiN, SiON, AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, etc., in addition to SiO ₂ .

Gate electrode 8 is formed in contact with the surface of gate insulating film 7 . In this embodiment, the gate electrode 8 is composed of a TiN layer and has a thickness of approximately 50 nm to 200 nm. The gate electrode 8 is biased toward the source electrode contact hole 11 .
In the second embodiment, the nitrogen-containing layer 50 is formed on the nitride semiconductor gate layer 6, the gate insulating film 7 is formed on the nitrogen-containing layer 50, and the gate electrode 8 is formed on the gate insulating film 7. It is That is, in the second embodiment, since the gate insulating film 7 is interposed between the nitride semiconductor gate layer 6 and the gate electrode 8, the gate leakage current can be reduced as compared with the first comparative example. . This makes it difficult for nitride semiconductor gate layer 6 to deteriorate. In the second embodiment, the gate leak current is 1 nA/mm or less.

Moreover, in the second embodiment, for the same reason as in the first embodiment, the same effect as in the first embodiment can be obtained. That is, in the second embodiment, the threshold voltage Vth can be made higher than in the first comparative example. Further, in the second embodiment, the nitride semiconductor gate layer 6 can be made thinner than in the first comparative example. Time-dependent dielectric breakdown (TDDB) of 6 becomes less likely to occur.

Furthermore, in the second embodiment, since the nitrogen-containing layer 50 is formed on the nitride semiconductor gate layer 6, even if the gate insulating film 7 is composed of an insulating film containing oxygen such as _SiO2 , , the effect that the threshold voltage Vth can be stabilized can be obtained. This point will be described below.
When the gate insulating film 7 made of an insulating film containing oxygen is formed in contact with the surface of the nitride semiconductor gate layer 6 , the nitride semiconductor gate layer 6 is oxidized and a Ga oxide film is formed on the nitride semiconductor gate layer 6 . may be formed. When the Ga oxide film is formed on the nitride semiconductor gate layer 6, the threshold voltage Vth tends to fluctuate.

In the second embodiment, since the nitrogen-containing layer 50 is formed on the nitride semiconductor gate layer 6, oxidation of the nitride semiconductor gate layer 6 can be suppressed and the threshold voltage Vth can be stabilized. More specifically, the AlN film 51 formed on the nitride semiconductor gate layer 6 acts as an interface control layer that reconstructs the surface of the underlying nitride semiconductor (nitride semiconductor gate layer 6). The SiN layer 52 formed on the AlN film 51 acts as an anti-oxidation layer that suppresses oxidation of the AlN film 51 during the process when the gate insulating film 7 is made of a material containing oxygen atoms. A good interface can be formed between the nitride semiconductor gate layer 6 and the gate insulating film 7 by the functions of the AlN film 51 and the SiN layer 52 .

FIG. 12 is an enlarged cross-sectional view showing a first modification of the gate portion of the second embodiment.
The gate portion 20B of FIG. 12 includes a nitride semiconductor gate layer 6, a nitrogen-containing layer 50A formed on the nitride semiconductor gate layer 6, a gate insulating film 7 formed on the nitrogen-containing layer 50A, and a gate insulating film. and a gate electrode 8 formed on the film 7 . The gate portion 20B of FIG. 12 differs from the gate portion 20A of FIG. 11 in the structure of the nitrogen-containing layer 50A. The nitrogen-containing layer 50A is composed of a single SiN film formed on the nitride semiconductor gate layer 6 . In this example, the film thickness of the nitrogen-containing layer 50A is approximately 2 nm.

FIG. 13 is an enlarged cross-sectional view showing a second modification of the gate portion of the second embodiment.
The gate portion 20C of FIG. 13 includes the nitride semiconductor gate layer 6, the nitrogen-containing layer 50B formed on the nitride semiconductor gate layer 6, the gate insulating film 7 formed on the nitrogen-containing layer 51, and the gate insulating layer 50B. and a gate electrode 8 formed on the film 7 . The gate portion 20C of FIG. 13 differs from the gate portion 20A of FIG. 11 in the structure of the nitrogen-containing layer 50B. Nitrogen-containing layer 50B is composed of SiN film 53 formed on nitride semiconductor gate layer 6 and AlN film 54 formed on SiN film 53 . In this example, the thickness of the SiN film 53 is approximately 5 nm, and the thickness of the AlN film 54 is approximately 2 nm.

Hereinafter, a nitride semiconductor device having a configuration in which the nitrogen-containing layer 50 is not provided with respect to the nitride semiconductor device 1A according to the second embodiment shown in FIG. 10 will be referred to as a second comparative example. Also, the nitride semiconductor device 1A according to the second embodiment shown in FIG. 10 will be referred to as a second example.
For the second embodiment and the second comparative example, two types of high temperature gate bias tests (HTGB: High Temperature Gate Bias test) was performed to measure the amount of change ΔVth in the threshold voltage Vth. A high-temperature gate bias test is a test in which a bias is applied only to the gate while the source and drain are short-circuited at a high temperature.

The threshold voltage Vth was measured at a plurality of predetermined timings before and after the start of the high-temperature gate bias test, and the amount of change ΔVth in the threshold voltage Vth from the threshold voltage Vth measured before the start of the test was measured. However, when the drain gate voltage Vd is 0.1 V and the drain current Id is 100 μA, the ON state of the HEMT is defined, and the gate-source voltage Vgs is defined as the threshold voltage Vth.

FIG. 14 is a graph showing high temperature gate bias test results when the gate voltage Vg is set to 5V. FIG. 15 is a graph showing high temperature gate bias test results when the gate voltage Vg is set to -3V. 14 and 15, "SiO2 only" indicates the second comparative example, and "AlN/SiN/SiO2" indicates the second example.
From FIGS. 14 and 15, it can be seen that in the second embodiment, the amount of change ΔVth in the threshold voltage Vth is small both when the gate voltage Vg is 5V and when it is -3V.

Although the first and second embodiments of the present invention have been described above, the present invention can also be implemented in other forms. For example, in the above-described embodiment, the first nitride semiconductor layer (electron transit layer) 4 is made of a GaN layer, and the second nitride semiconductor layer (electron supply layer) 5 is made of an AlGaN layer. It is sufficient that the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 have different bandgaps (for example, Al composition), and other combinations are also possible. For example, the combination of the first nitride semiconductor layer 4/second nitride semiconductor layer 5 can be GaN/AlN, AlGaN/AlN, or the like.

In the first and second embodiments described above, silicon was exemplified as a material for the substrate 2, but any substrate material such as a sapphire substrate or a GaN substrate can also be applied.
Further, in the first and second embodiments described above, when the gate electrode 7 is joined to the nitride semiconductor gate layer 6, the gate electrode 7 is made of a material that forms a Schottky junction. bottom. However, if the gate electrode 7 is joined to the nitride semiconductor gate layer 6, the present invention can also be applied to the case where the gate electrode 7 is made of a material such that they form an ohmic contact.

In addition, various design changes can be made within the scope of the matters described in the claims.

Reference Signs List 1, 1A nitride semiconductor device 2 substrate 3 buffer layer 3A first buffer layer 3B second buffer layer 4 first nitride semiconductor layer 5 second nitride semiconductor layer 20, 20A, 20B, 20C gate section 6 nitride semiconductor gate Layer 7 gate insulating film 8 gate electrode 9 passivation film 10 barrier metal film 11 source electrode contact hole 12 drain electrode contact hole 13 source electrode 14 drain electrode 13A, 14A lower layer 13B, 14B intermediate layer 13C, 14C upper layer 15 interlayer insulating film 16 two-dimensional electron gas 31 gate layer material film 32 insulating material film 33 gate electrode film 34 resist film 35 source/drain electrode film 50, 50A, 50B nitrogen-containing layer

Claims (19)

a first nitride semiconductor layer constituting an electron transit layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer, having a bandgap larger than that of the first nitride semiconductor layer, and constituting an electron supply layer;
a gate portion disposed on the second nitride semiconductor layer;
a passivation film formed to cover the gate;
a source electrode and a drain electrode arranged to sandwich the gate portion in a direction along the surface of the second nitride semiconductor layer;
The gate section
a nitride semiconductor gate layer disposed on the second nitride semiconductor layer and containing an acceptor-type impurity;
a gate insulating film formed on the nitride semiconductor gate layer;
a gate electrode formed on the gate insulating film;
the source electrode is formed to cover the gate portion and the passivation film, and is arranged to face the drain electrode beyond the gate portion;
A nitride semiconductor device having a gate leak current of 1 nA/mm or less. 2. The gate insulating film according to claim 1, wherein said gate insulating _film is composed of one selected from SiN, _SiO2 , SiON, _Al2O3 , AlN, AlON, HfO, HfN, HfON, HfSiON and AlON. nitride semiconductor device. 2. The nitride semiconductor device according to claim 1, wherein said gate insulating film is made of SiN. the thickness of the nitride semiconductor gate layer is 100 nm or less,
4. The nitride semiconductor device according to claim 1, wherein said gate insulating film has a film thickness of 3 nm or more. 5. The semiconductor device according to any one of claims 1 to 4, further comprising a third nitride semiconductor layer arranged on a side of said first nitride semiconductor layer opposite to said second nitride semiconductor layer and constituting a buffer layer. nitride semiconductor device. 2. The nitride semiconductor device according to claim 1, wherein the carbon concentration at the interface between said nitride semiconductor gate layer and said gate insulating film is 1×10 ¹³ cm ⁻² or less. 7. The nitride semiconductor gate layer according to claim 1, wherein said first nitride semiconductor layer comprises a GaN layer, said second nitride semiconductor layer comprises an AlGaN layer, and said nitride semiconductor gate layer comprises a p-type GaN layer. The nitride semiconductor device according to 1. The first nitride semiconductor layer is a GaN layer, the second nitride semiconductor layer is an AlGaN layer, the nitride semiconductor gate layer is a p-type GaN layer, and the third nitride semiconductor layer is an AlGaN layer. 6. The nitride semiconductor device according to claim 5, comprising: 9. The nitride semiconductor device according to claim 7, wherein said acceptor-type impurity is magnesium or iron. a first nitride semiconductor layer constituting an electron transit layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer, having a bandgap larger than that of the first nitride semiconductor layer, and constituting an electron supply layer;
a gate portion disposed on the second nitride semiconductor layer;
a passivation film formed to cover the gate;
a source electrode and a drain electrode arranged to sandwich the gate portion in a direction along the surface of the second nitride semiconductor layer;
The gate section
a nitride semiconductor gate layer disposed on the second nitride semiconductor layer and containing an acceptor-type impurity;
a nitrogen-containing layer containing nitrogen formed on the nitride semiconductor gate layer;
a gate insulating film disposed on the nitrogen-containing layer;
a gate electrode formed on the gate insulating film;
the source electrode is formed to cover the gate portion and the passivation film, and is arranged to face the drain electrode beyond the gate portion;
A nitride semiconductor device having a gate leak current of 1 nA/mm or less. 11. The nitride semiconductor device according to claim 10, wherein said nitrogen-containing layer has a thickness of 10 nm or less. 12. The nitride semiconductor device according to claim 10, wherein said nitrogen-containing layer is composed of a single film of AlN film or SiN film, or a laminated film of AlN film and SiN film. 13. The nitride semiconductor device according to claim 12, wherein said nitrogen-containing layer comprises an AlN film formed on said nitride semiconductor gate layer and an SiN film formed on said AlN film. 14. The nitride semiconductor device according to claim 10, wherein said gate insulating film is made of an insulating film containing oxygen. 15. The nitride semiconductor device according to claim ₁₄ , wherein said gate insulating film comprises an _Al2O3 film or a _SiO2 film. 16. The nitride semiconductor device according to claim 1, further comprising a barrier metal film formed on said passivation film. 17. The nitride semiconductor device according to claim 1, further comprising an interlayer insulating film covering said source electrode, upper surfaces of said source electrode, and opposing surfaces of said source electrode and said source electrode. 18. The nitride semiconductor device according to claim 1, wherein said drain-side end surface of said source electrode is flush with said drain-side end surface of said passivation film covering said gate electrode. . 6. The nitride semiconductor device according to claim 5, wherein said third nitride semiconductor layer comprises an AlN film formed on said silicon substrate and an AlGaN film laminated on said AlN film.

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