KR20220000362A - Semiconductor package including antenna - Google Patents

Abstract

According to the present invention, provided is a semiconductor package, which comprises: a package substrate including a wiring pattern; a semiconductor chip on the package substrate; a molding layer disposed on the package substrate to cover the semiconductor chip; a connection conductor extending through the molding layer from a lower surface to an upper surface of the molding layer, and electrically connected to the wiring pattern of the package substrate; an antenna structure on the molding layer; a conductive connection terminal disposed between the connection conductor and a connection pad of the antenna structure to electrically connect the connection conductor and the connection pad of the antenna structure; and a conductive interface layer disposed between the connection conductor and the conductive connection terminal, and extending along a surface of the connection conductor facing the conductive connection terminal. Therefore, the signal transmission efficiency can be improved.

Description

Semiconductor package including antenna {SEMICONDUCTOR PACKAGE INCLUDING ANTENNA}

The technical idea of the present invention relates to a semiconductor package, and more particularly, to a semiconductor package including an antenna structure for transmitting and receiving a radio signal.

In electronic devices, integrated circuits are widely applied due to their advantages of small size, light weight, high reliability, and easy mass production. The integrated circuit package device may integrate all components required by a circuit having a specific function into one chip, and package the chip on a package substrate. The component may include devices such as semiconductors, resistors and capacitors, and connecting wires between the devices. When the chip needs to receive or transmit wireless signals, an antenna may be placed in the integrated circuit packaged device.

An object to be solved by the technical spirit of the present invention is to provide a semiconductor package including an antenna structure.

In order to solve the above problems, the technical idea of the present invention is a package substrate including a wiring pattern; a semiconductor chip on the package substrate; a molding layer disposed on the package substrate to cover the semiconductor chip; a connection conductor penetrating through the molding layer, extending from a lower surface to an upper surface of the molding layer, electrically connected to the wiring pattern of the package substrate, and including a first metal; an antenna structure on the molding layer; a conductive connection terminal disposed between the connection conductor and the connection pad of the antenna structure to electrically connect the connection conductor and the connection pad of the antenna structure, the conductive connection terminal including a second metal different from the first metal; and a conductive interface layer disposed between the connection conductor and the conductive connection terminal, the conductive interface layer extending along a surface of the connection conductor facing the conductive connection terminal, and including the first metal and the second metal; and wherein the antenna structure is spaced apart by the molding layer, and a gap is formed between the antenna structure and the molding layer. In exemplary embodiments, the first metal is solder, and the second metal is a solder. The metal is copper.

In example embodiments, a lower portion of the conductive connection terminal is buried in a connection conductor, and extends from the top surface of the molding layer toward the bottom surface of the molding layer.

In example embodiments, a vertical height and a maximum horizontal width of the connecting conductor are greater than a vertical height of the semiconductor chip, and the vertical height of the connecting conductor is between 300 micrometers and 1400 micrometers.

In exemplary embodiments, the distance between the top surface of the molding layer and the antenna structure is between 4 micrometers and 25 micrometers.

In exemplary embodiments, the connecting conductor has an outwardly convex sidewall, the lower horizontal width of the connecting conductor becomes smaller as it approaches the package substrate, and the horizontal width of the upper portion of the connecting conductor is It becomes smaller as it is adjacent to the upper surface of the molding layer.

In example embodiments, the connecting conductor may include a core portion including a first conductive material; and a shell part including a second conductive material different from the first conductive material and surrounding the core part.

In exemplary embodiments, the connecting conductor has a columnar shape with a straight sidewall of the connecting conductor, and includes solder.

In exemplary embodiments, a lower surface of the antenna structure facing the upper surface of the molding layer includes first and second edges opposite to each other, and the first edge and the molding of the lower surface of the antenna structure The ratio between the distance between the top surface of the layer and the distance between the second edge of the bottom surface of the antenna structure and the top surface of the molding layer is between 80% and 110%.

In order to solve the above problems, the technical idea of the present invention is to provide a semiconductor package including a first region and a second region separated from each other, the package substrate including a wiring pattern and an antenna pattern in the first region; a semiconductor chip on the package substrate; a molding layer disposed on the package substrate to cover the semiconductor chip; and an external conductive shielding layer partially covering the molding layer, wherein the external conductive shielding layer is provided in the second region and spaced apart from the first region.

In example embodiments, the molding layer entirely covers a top surface of the package substrate, and the external conductive shielding layer covers a portion of the top surface of the molding layer in the second region, and the molding layer in the first region. The other part of the top surface of the molding layer is not covered so that the other part of the top surface of the molding layer is exposed to the outside.

In example embodiments, the molding layer may cover a portion of an upper surface of the package substrate in the second region, and expose another portion of the upper surface of the package substrate in the first region to the outside. The other portion of the top surface of the substrate is not covered.

In exemplary embodiments, a cover insulating layer that is in contact with the upper surface of the molding layer and at least partially covers the upper surface of the molding layer, wherein the cover insulating layer includes polyimide.

In order to solve the above problems, the technical idea of the present invention is a package substrate including a wiring pattern; a semiconductor chip on the package substrate; a molding layer disposed on the package substrate to cover the semiconductor chip; an internal conductive shielding layer extending in a vertical direction in the molding layer and enclosing a side surface of the semiconductor chip; and an antenna pattern extending in the vertical direction within the molding layer, disposed between the inner conductive shielding layer and an outer surface of the molding layer, and electrically connected to the semiconductor chip through the wiring pattern; provides

In example embodiments, the internal conductive shielding layer may include a cover part covering an upper surface of the semiconductor chip; and a sidewall portion extending to surround the side surface of the semiconductor chip and extending from an edge of the cover portion toward the package substrate.

According to exemplary embodiments of the present invention, since the antenna structure is disposed close to the semiconductor chip, a signal transmission path between the antenna structure and the semiconductor chip may be shortened, and thus signal transmission efficiency may be improved.

1 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
FIG. 2 is a plan view showing an upper surface of the molding layer of FIG. 1 .
3 is an enlarged view showing an enlarged area indicated by "III" in FIG.
4 is a cross-sectional view illustrating a part of a semiconductor package according to exemplary embodiments of the present invention.
5 is a cross-sectional view illustrating a part of a semiconductor package according to exemplary embodiments of the present invention.
6 is a cross-sectional view illustrating a part of a semiconductor package according to exemplary embodiments of the present invention.
7A to 7C are cross-sectional views illustrating a portion of a semiconductor package according to exemplary embodiments of the present invention.
8 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
9 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
10 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
11 is a plan view of the semiconductor package of FIG. 10 as viewed from above.
12 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
13 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
14A is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
14B is a cross-sectional view taken along line B1-B1' of FIG. 14A.
15A is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
15B is a cross-sectional view taken along line B2-B2' of FIG. 15A.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, exemplary embodiments of the present disclosure may be modified in various other forms, and the scope of the present disclosure should not be construed as being limited by the embodiments described below. It is preferred that the exemplary embodiments of the present disclosure are provided to more completely explain the concepts of the present disclosure to those of ordinary skill in the art. The same symbols refer to the same elements from beginning to end. Furthermore, various elements and regions in the drawings are schematically drawn. Accordingly, the concept of the present disclosure is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and conversely, the second component may be referred to as a first component.

The terminology used in the present disclosure is used only to describe specific embodiments, and is not intended to limit the concept of the present disclosure. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, expressions such as "comprises" or "have" are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification is present, but one or more other features or It should be understood that the existence or addition of numbers, operations, components, parts or combinations thereof is not precluded in advance.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the concepts of this disclosure belong, including technical and scientific terms. In addition, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined herein, in an overly formal sense. It will be understood that they shall not be construed.

1 is a cross-sectional view illustrating a semiconductor package 10 according to exemplary embodiments of the present invention. FIG. 2 is a plan view showing the upper surface 149 of the molding layer 140 of FIG. 1 . 3 is an enlarged view showing an enlarged area indicated by "III" in FIG.

Referring to FIG. 1 , a semiconductor package 10 may include a package substrate 101 , a semiconductor chip 130 , a molding layer 140 , a connection conductor 155 , and an antenna structure 210 .

The package substrate 101 includes a redistribution board formed through a redistribution process, a printed circuit board (PCB), a metal core PCB (MCPCB), a metal PCB (MPCB), and a flexible PCB (FPCB). can do. The package substrate 101 has a substantially flat shape, and may include an upper surface 109 on which the semiconductor chip 130 is mounted and a lower surface opposite to the upper surface 109 . Hereinafter, the horizontal direction is defined as a direction parallel to the upper surface 109 of the package substrate 101 (eg, the X direction and/or the Y direction), and the vertical direction is the upper surface 109 of the package substrate 101 . It is defined as a direction perpendicular to (eg, Z direction). In addition, the horizontal width of an arbitrary member is defined as a length along the horizontal direction (eg, X-direction and/or Y-direction), and the vertical height of an arbitrary member is defined as a length in the vertical direction (eg, Z-direction). defined by the length

In example embodiments, the package substrate 101 may be a redistribution substrate including the wiring insulating layer 110 and the wiring pattern 120 . The wiring insulating layer 110 may include a plurality of insulating layers 111 , 113 , and 115 stacked in a vertical direction. For example, the wiring insulating layer 110 may be formed of an insulating polymer, epoxy, or a combination thereof. The wiring pattern 120 may be covered by the wiring insulating layer 110 . The wiring pattern 120 may be electrically connected to electronic components included in the semiconductor package 10 , such as the semiconductor chip 130 , and electrically connect between electronic components included in the semiconductor package 10 . The wiring pattern 120 may include line patterns disposed in the wiring insulating layer 110 to form different layers and via patterns connecting between the line patterns. The wiring pattern 120 may include an external pad exposed through the lower surface of the package substrate 101 . In example embodiments, the lower pads included in the wiring pattern 120 may be arranged at a pitch between 450 micrometers and 1400 micrometers. The wiring pattern 120 may include a conductive material such as copper (Cu) or aluminum (Al).

The semiconductor chip 130 may include a first surface and a second surface opposite to each other. The first surface of the semiconductor chip 130 may be a pad surface on which the chip pad 131 is provided. The chip pad 131 of the semiconductor chip 130 may be electrically connected to a semiconductor device formed in the semiconductor chip 130 . Although not specifically illustrated, the semiconductor chip 130 may include a passivation layer covering the first surface of the semiconductor chip 130 and including an opening exposing the chip pad 131 .

The semiconductor chip 130 may be mounted on the package substrate 101 in a flip-chip method. The semiconductor chip 130 may be disposed on the top surface 109 of the package substrate 101 such that the first surface on which the chip pad 131 is provided faces the package substrate 101 . For example, a chip connection terminal 137 such as a micro bump may be disposed between the semiconductor chip 130 and the package substrate 101 . The semiconductor chip 130 may be electrically connected to the wiring pattern 120 through the chip connection terminal 137 . More specifically, the wiring pattern 120 includes an upper pad to which the chip connection terminal 137 is attached, and the chip connection terminal 137 includes the upper pad of the wiring pattern 120 and the chip of the semiconductor chip 130 . The pads 131 may be physically and electrically connected. In example embodiments, upper pads included in the wiring pattern 120 may be arranged at a pitch of between 60 micrometers and 230 micrometers.

A plurality of individual devices of various types may be formed in the semiconductor chip 130 . For example, the plurality of individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-oxide-semiconductor transistor (CMOS), and a system large scale LSI (LSI). integration), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, and the like.

In example embodiments, the semiconductor chip 130 is a communication semiconductor chip electrically or signal-transmittable connected to the antenna structure 210 , and a signal processing circuit for processing a radio signal transmitted and received through the antenna structure 210 . and the like. For example, the semiconductor chip 130 may include a radio-frequency integrated circuit (RFIC).

In example embodiments, the semiconductor chip 130 may be, for example, a memory chip. The memory chip is, for example, a volatile memory semiconductor chip 130 such as dynamic random access memory (DRAM) or static random access memory (SRAM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), etc. ), a ferroelectric random access memory (FeRAM), or a non-volatile memory chip such as a resistive random access memory (RRAM).

Alternatively, in example embodiments, the semiconductor chip 130 may be a logic chip. For example, the semiconductor chip 130 may be a central processor unit (CPU), a micro processor unit (MPU), a graphic processor unit (GPU), or an application processor (AP).

The semiconductor package 10 may include one semiconductor chip 130 or two or more semiconductor chips 130 . The two or more semiconductor chips 130 included in the semiconductor package 10 may be semiconductor chips of the same type or different types of semiconductor chips. In example embodiments, the semiconductor package 10 may be a system in package in which different types of semiconductor chips 130 and various electronic components are electrically connected to each other to operate as one system.

The molding layer 140 is disposed on the upper surface 109 of the package substrate 101 and may cover at least a portion of the semiconductor chip 130 . For example, the molding layer 140 may cover the side surface of the semiconductor chip 130 and cover the top surface of the semiconductor chip 130 . In some example embodiments, the molding layer 140 may cover the side surface of the semiconductor chip 130 , but may not cover the top surface of the semiconductor chip 130 . Also, the molding layer 140 may be filled between the semiconductor chip 130 and the package substrate 101 and surround the chip connection terminal 137 under the semiconductor chip 130 . The molding layer 140 may be formed of, for example, an epoxy molding compound, but is not limited thereto.

The connecting conductor 155 may penetrate the molding layer 140 . The connecting conductor 155 may extend from the lower surface of the molding layer 140 in contact with the upper surface 109 of the package substrate 101 to the upper surface 149 of the molding layer 140 . The lower end of the connecting conductor 155 may be connected to the wiring pattern 120 of the package substrate 101 , and the upper end of the connecting conductor 155 may be connected to the conductive connecting terminal 193 .

In example embodiments, a vertical height of the connection conductor 155 may be greater than a vertical height of the semiconductor chip 130 . For example, the vertical height of the connecting conductor 155 may be between 150% and 400%, or between 200% and 350% of the vertical height of the semiconductor chip 130 . A vertical height of the connecting conductor 155 may be approximately equal to a vertical height of the molding layer 140 . In exemplary embodiments, the vertical height of the connecting conductor 155 is between 300 micrometers and 1400 micrometers, between 400 micrometers and 1200 micrometers, between 500 micrometers and 900 micrometers, or between 600 micrometers and 700 micrometers. It can be between meters.

The horizontal width of the connecting conductor 155 may be maximum in the middle portion between the bottom and the top of the connecting conductor 155 . For example, the connecting conductor 155 may gradually increase from the lower end to the middle portion, and may gradually decrease from the middle portion to the upper end. In other words, the horizontal width of the lower portion of the connecting conductor 155 becomes smaller as it approaches the upper surface 109 of the package substrate 101 , and the upper portion of the connecting conductor 155 is the upper surface 149 of the molding layer 140 . The horizontal width may become smaller as it is adjacent to .

In example embodiments, a horizontal width of the middle portion of the connection conductor 155 may be greater than a vertical height of the semiconductor chip 130 . For example, the horizontal width of the middle portion of the connecting conductor 155 may be between 1.5 and 3 times the height of the semiconductor chip 130 .

In example embodiments, a separation distance in a horizontal direction (eg, X-direction and/or Y-direction) between the connection conductor 155 and the semiconductor chip 130 is between 50 micrometers and 250 micrometers, 70 It may be between micrometers and 200 micrometers, or between 80 micrometers and 150 micrometers.

The connecting conductor 155 includes solder, tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), lead (Pb), and / or alloys thereof. In example embodiments, the connecting conductor 155 may be manufactured using a solder ball and may include solder.

In example embodiments, in order to form the connection conductor 155 , a solder ball is placed on the package substrate 101 and a reflow process is performed, and a molding material covering the semiconductor chip 130 and the solder ball is performed. The steps of forming a , exposing the solder balls by performing a polishing process (eg, back grinding or chemical mechanical polishing) on the molding material may be sequentially performed. During the polishing process, a portion of the solder ball may be removed together with the molding material, and the upper surface of the connecting conductor 155 and the upper surface 149 of the molding layer 140 may be flatly polished to be on the same plane. have.

The antenna structure 210 may be mounted on the molding layer 140 . The antenna structure 210 may be an antenna module or a chip antenna in which an antenna structure for wireless communication with an external device is embedded. For example, the antenna structure of the antenna structure 210 may be configured to radiate or receive a radio signal in a millimeter wavelength band.

The antenna structure 210 may include a connection pad 211 provided on a lower surface facing the molding layer 140 . A conductive connection terminal 193 may be disposed between the connection pad 211 of the antenna structure 210 and the upper surface of the connection conductor 155 . The antenna structure 210 may be mounted on the molding layer 140 and the connection conductor 155 through the conductive connection terminal 193 . The connection pad 211 of the antenna structure 210 and the connection conductor 155 may be electrically and physically connected through the conductive connection terminal 193 . The antenna structure of the antenna structure 210 is formed through an electrical path passing through the connection pad 211 , the conductive connection terminal 193 , the connection conductor 155 , and the wiring pattern 120 of the antenna structure 210 , the semiconductor It may be connected to the chip 130 for signal transmission.

In example embodiments, a conductive interface layer 194 may be provided between the connection conductor 155 and the conductive connection terminal 193 . The conductive interface layer 194 may extend along a top surface of the connection conductor 155 facing the conductive connection terminal 193 . In example embodiments, the conductive interface layer 194 may cover a top surface of the connecting conductor 155 in a plan view.

The conductive interface layer 194 may include a first metal material constituting the connection conductor 155 and a second metal material constituting the conductive connection terminal 193 . The conductive interface layer 194 may include an intermetallic compound layer formed when the connection conductor 155 including different metals and the conductive connection terminal 193 are combined. For example, when the connecting conductor 155 includes solder and the conductive connection terminal 193 includes copper (Cu), the conductive interface layer 194 may include solder and copper.

In exemplary embodiments, the antenna structure 210 is spaced apart from the top surface 149 of the molding layer 140 , and a gap 195 is formed between the antenna structure 210 and the top surface 149 of the molding layer 140 . can be formed. The vertical height of the gap 195 may be similar to the vertical height of the conductive connection terminal 193 . For example, the gap 195 may be used as a space in which heat generated in an electronic component such as the semiconductor chip 130 is emitted. In example embodiments, the conductive connection terminal 193 has a pillar or bump shape and may include copper (Cu). When the conductive connection terminal 193 is formed using copper (Cu), the uniformity of the height of the gap 195 may be improved compared to the case where a material such as solder is used. In embodiments, the distance between the antenna structure 210 and the top surface 149 of the molding layer 140 may be uniform throughout.

In example embodiments, the lower surface of the antenna structure 210 has opposite first edges (eg, the left edge of the lower surface of the antenna structure 210 ) and a second edge (eg, the antenna structure 210 ). ) when including the right edge of the lower surface), the distance between the first edge of the lower surface of the antenna structure 210 and the upper surface of the molding layer 140 and the second edge of the lower surface of the antenna structure 210 and molding The ratio between the distances between the top surfaces of the layers 140 may be between 80% and 110%.

In example embodiments, the height of the gap 195 may be adjusted by adjusting the vertical height of the conductive connection terminal 193 . In some exemplary embodiments, by adjusting the vertical height of the conductive connection terminal 193 , the distance between the antenna pattern included in the antenna structure 210 and the semiconductor chip 130 corresponding to the RFIC is adjusted to the characteristics of the antenna pattern. can be adjusted accordingly.

In example embodiments, the vertical height of the conductive connection terminal 193 may be between 4 micrometers and 25 micrometers, between 6 micrometers and 18 micrometers, or between 8 micrometers and 11 micrometers. The vertical height of the gap 195 , that is, the distance in the vertical direction (eg, Z direction) between the upper surface 149 of the molding layer 140 and the antenna structure 210 is the vertical height of the conductive connection terminal 193 . may be similar to For example, a distance in a vertical direction (eg, Z direction) between the upper surface 149 of the molding layer 140 and the antenna structure 210 is between 4 micrometers and 25 micrometers, and between 6 micrometers and 18 micrometers. meters, or between 8 micrometers and 11 micrometers. If the separation distance between the upper surface 149 of the molding layer 140 and the antenna structure 210 is too small, there is a fear that heat dissipation efficiency through the gap 195 may be reduced. If the separation distance between the upper surface 149 of the molding layer 140 and the antenna structure 210 is too large, the signal transmission path between the semiconductor chip 130 and the antenna structure 210 becomes long, so that the signal transmission efficiency is reduced. There is a risk of deterioration.

In example embodiments, the horizontal width of the conductive connection terminal 193 may be greater than the horizontal width of the upper surface of the connection conductor 155 . The central portion of the conductive connection terminal 193 covers the top surface of the connection conductor 155 , and the edge of the conductive connection terminal 193 is on the top surface 149 of the molding layer 140 around the connection conductor 155 . can be contacted. As the conductive connection terminal 193 is formed to have a greater horizontal width than the upper surface of the connection conductor 155 , the support of the antenna structure 210 through the conductive connection terminal 193 may be more robust.

According to exemplary embodiments of the present invention, since the connecting conductor 155 can be manufactured at low cost using a solder ball, the manufacturing cost of the semiconductor package 10f can be greatly reduced.

In addition, according to exemplary embodiments of the present invention, since the connecting conductor 155 has a larger volume than a general vertical connection structure, misalignment issues due to process errors are reduced. In addition, the contact area between the connection conductor 155 and the conductive connection terminal 193 is increased to reduce contact resistance, and ultimately, signal transmission efficiency through the signal transmission path including the connection conductor 155 is improved. can be Furthermore, since the antenna structure 210 is disposed close to the semiconductor chip 130 , a signal transmission path between the antenna structure 210 and the semiconductor chip 130 may be shortened, and thus signal transmission efficiency may be improved. .

4 to 6 are cross-sectional views each showing a portion of a semiconductor package according to exemplary embodiments of the present invention. 4 to 6 , a partial region of the semiconductor package corresponding to the region indicated by “III” in FIG. 1 is shown, respectively. Hereinafter, differences from the semiconductor package 10 described above with reference to FIGS. 1 to 3 will be mainly described.

Referring to FIG. 4 together with FIG. 1 , the connecting conductor 155a may have a core-shell structure including a core part 1551 and a shell part 1553 . The shell part 1553 may surround at least a portion of the core part 1551 . For example, the core part 1551 may have a substantially ball shape, and the shell part 1553 may cover the entire outer surface of the core part 1551 .

The core part 1551 and the shell part 1553 may include different conductive materials. For example, the core part 1551 may be made of a material having higher electrical conductivity than a material constituting the shell part 1553 . For example, the shell part 1553 may be made of a material having excellent adhesion to other materials. In example embodiments, the core part 1551 may include copper (Cu), and the shell part 1553 may include solder.

Referring to FIG. 5 together with FIG. 1 , the connecting conductor 155b may include a core part 1551a and a shell part 1553a surrounding the side surfaces of the core part 1551a. The upper portion of the core portion 1551a may not be covered by the shell portion 1553a. The core part 1551a may have an upper surface planarized through a polishing process, and the upper surface of the core part 1551a may be in direct contact with the conductive connection terminal 193 . Also, a lower portion of the core portion 1551a may not be covered by the shell portion 1553a , and a lower portion of the core portion 1551a may be directly connected to the wiring pattern 120 .

In exemplary embodiments, the conductive interface layer 194 is disposed between the top surface of the shell part 1553a and the conductive connection terminal 193 , but is not disposed between the top surface of the core part 1551a and the conductive connection terminal 193 . it may not be

Referring to FIG. 6 , a portion of the conductive connection terminal 193 may extend into the connection conductor 155 and be buried in the connection conductor 155 . More specifically, the conductive connection terminal 193 is buried in the connection conductor 155 and may include a lower portion 1931 extending downward from the top surface 149 of the molding layer 140 . That is, the lower portion 1931 of the conductive connection terminal 193 extends downward from the upper surface 149 of the molding layer 140 , and may be between the upper surface 149 and the lower surface of the molding layer 140 . Since the sidewall and bottom surface of the lower portion 1931 of the conductive connection terminal 193 are covered by the connection conductor 155 , the contact area between the conductive connection terminal 193 and the connection conductor 155 is increased, and the conductive connection Connection reliability between the terminal 193 and the connection conductor 155 may be improved.

In example embodiments, the conductive interface layer 194 may extend along an interface between the lower portion 1931 of the conductive connection terminal 193 and the connection conductor 155 .

In example embodiments, the vertical height of the lower portion 1931 of the conductive connection terminal 193 may be between 5% and 40% of the vertical height of the connection conductor 155 . In some exemplary embodiments, the vertical height of the lower portion 1931 of the conductive connection terminal 193 is determined such that, during the bonding process between the connection conductor 155 and the conductive connection terminal 193 , the conductive connection terminal 193 is conductively connected. The degree of diffusion into the sieve 155 may be controlled. In some exemplary embodiments, in order to adjust the vertical height of the lower portion 1931 of the conductive connection terminal 193 , before performing a bonding process between the connection conductor 155 and the conductive connection terminal 193 , the connection conductor A bonding process between the connecting conductor 155 and the conductive connecting terminal 193 is performed in a state where a groove is formed in the 155 and a part of the conductive connecting terminal 193 is inserted into the groove of the connecting conductor 155 . can

7A to 7C are cross-sectional views illustrating semiconductor packages according to exemplary embodiments of the present invention. Hereinafter, descriptions overlapping those described above will be omitted.

Referring to FIG. 7A , a gapper 199 may be further disposed between the upper surface 149 of the molding layer 140 and the antenna structure 210 . Similar to the conductive connection terminal 193 , the gapper 199 may be in the form of a pillar or bump extending between the lower surface of the antenna structure 210 and the upper surface 149 of the molding layer 140 . The gapper 199 may support the antenna structure 210 together with the conductive connection terminal 193 , and may function to maintain a distance between the antenna structure 210 and the upper surface 149 of the molding layer 140 . . The gapper 199 may be a dummy pattern not connected to the connecting conductor 155 .

In example embodiments, the gapper 199 may include a conductive material. For example, it may include the same material as the conductive connection terminal 193 . In other exemplary embodiments, the gapper 199 may include an insulating material.

In example embodiments, the gapper 199 may be disposed between the conductive connection terminal 193 and the edge of the upper surface of the molding layer 140 .

Referring to FIG. 7B , the gapper 199a may be disposed between the conductive connection terminals 193 .

Referring to FIG. 7C , the gapper 199b may be disposed so as not to overlap the electronic component such as the semiconductor chip 130 covered with the molding layer 140 in a plan view.

8 is a cross-sectional view illustrating a semiconductor package 10a according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 10a shown in FIG. 8 will be described, focusing on differences from the semiconductor package 10 described with reference to FIGS. 1 to 3 .

Referring to FIG. 8 , the semiconductor package 10a may include a connection conductor 155c passing through the molding layer 140 and having a substantially pillar shape. The sidewall of the connecting conductor 155c may have a generally straight profile.

In example embodiments, in order to form the connecting conductor 155c, placing a conductor constituting the connecting conductor 155c on a package substrate 101 and performing a reflow process, the semiconductor Forming a molding material covering the chip 130 and the conductor, performing a polishing process (eg, back grinding or chemical mechanical polishing) on the molding material to expose the conductor may be sequentially performed. have. During the polishing process, a portion of the conductor may be removed together with the molding material, and the upper surface of the connecting conductor 155c and the upper surface 149 of the molding layer 140 are polished to be flat and on the same plane. can

In example embodiments, a horizontal width of the connection conductor 155c may be greater than a vertical height of the semiconductor chip 130 . For example, the horizontal width of the connecting conductor 155c may be between 1.5 and 3 times the height of the semiconductor chip 130 .

9 is a cross-sectional view illustrating a semiconductor package 10b according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 10b shown in FIG. 9 will be described with a focus on differences from the semiconductor package 10 described with reference to FIGS. 1 to 3 .

Referring to FIG. 9 , the antenna structure 210a may be implemented as a can antenna attached to the molding layer 140 . The can antenna may be formed of a conductor having a shape suitable for performing wireless communication. The antenna structure 210a may be attached on the upper surface of the connection conductor 155 through the conductive connection terminal 193 .

In FIG. 9 , the connecting conductor 155 is illustrated as the connecting conductor 155 described with reference to FIGS. 1 to 3 , but in other exemplary embodiments, the connecting conductor 155 is shown in FIG. 4 . The connection conductors 155a, 155b, and 155c described with reference to FIGS. to 6 may be substituted.

10 is a cross-sectional view illustrating a semiconductor package 10c according to exemplary embodiments of the present invention. 11 is a plan view of the semiconductor package 10c of FIG. 10 as viewed from above. Duplicates of the above-described contents are omitted or simplified.

10 and 11 , the semiconductor package 10 may include a package substrate 101 , a semiconductor chip 130 , a molding layer 140 , an antenna structure 150 , and an external conductive shielding layer 161 . can

The antenna structure 150 may be formed in the wiring insulating layer 110 of the package substrate 101 . In example embodiments, the antenna structure 150 may be formed of a conductive material pattern formed together during a redistribution process for forming the wiring pattern 120 . In this disclosure, the antenna structure 150 may be referred to as an antenna pattern. In this case, the antenna structure 150 may include the same material as the wiring pattern 120 . The antenna structure 150 may be electrically connected to the semiconductor chip 130 through the wiring pattern 120 of the package substrate 101 .

The external conductive shielding layer 161 may be formed on the outermost portion of the semiconductor package 10c. The external conductive shielding layer 161 may serve to shield electromagnetic interference between the external environment and electronic components such as the semiconductor chip 130 included in the semiconductor package 10c. For example, a portion of the external conductive shielding layer 161 may extend along the side and top surfaces of the molding layer 140 , and another part of the external conductive shielding layer 161 may extend along the side surface of the package substrate 101 . can

In example embodiments, the semiconductor package 10c includes a first region R1 in which the antenna structure 150 is disposed and a second region R2 separated from the first region R1 in a plan view. can do. The external conductive shielding layer 161 may be disposed in the second region R2 , but may not be disposed in the first region R1 so that transmission of a wireless signal using the antenna structure 150 is not blocked.

In example embodiments, the antenna structure 150 is disposed in a portion of the package substrate 101 in the first region R1 , and electronic components such as the semiconductor chip 130 and the external conductive shielding layer 161 are It may be disposed in the second region R2 .

In example embodiments, the external conductive shielding layer 161 covers the side and top surfaces of a portion of the molding layer 140 in the second region R2 , and the package substrate 101 in the second region R2 . may cover at least a portion of the side of the

In example embodiments, the external conductive shielding layer 161 is a top surface of the molding layer 140 such that a first portion of the top surface 149 of the molding layer 140 in the first region R1 is exposed to the outside. The second portion of (149) may be uncovered. The external conductive shielding layer 161 may cover the second portion of the upper surface 149 of the molding layer 140 in the second region R2 .

In example embodiments, the external conductive shielding layer 161 may be electrically connected to the wiring pattern 120 . For example, the external conductive shielding layer 161 may be formed to contact a portion of the wiring pattern 120 exposed through the side surface of the package substrate 101 . In example embodiments, the external conductive shielding layer 161 may be electrically grounded through the wiring pattern 120 .

For example, the external conductive shielding layer 161 may include a conductive material such as copper (Cu), silver (Ag), or platinum (Pt). For example, the external conductive shielding layer 161 may be formed through processes such as physical vapor deposition, chemical vapor deposition, electroless plating, electrolytic plating, spraying, etc., but is not limited thereto.

According to exemplary embodiments of the present invention, since the antenna structure 150 is formed in the package substrate 101 , the semiconductor package 10c can be miniaturized.

12 is a cross-sectional view illustrating a semiconductor package 10d according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 10d shown in FIG. 12 will be described with a focus on differences from the semiconductor package 10c previously described with reference to FIGS. 10 and 11 .

Referring to FIG. 12 , when the semiconductor package 10d includes a first region R1 in which the antenna structure 150 is disposed and a second region R2 spaced apart from the first region R1, the molding layer Reference numeral 140 may be disposed in the second region R2 of the semiconductor package 10d, but may not be disposed in the first region R1 of the semiconductor package 10d. The molding layer 140 is formed to partially cover the upper surface 109 of the package substrate 101 in the second region R2 of the semiconductor package 10d, and the first region R1 of the semiconductor package 10c. The other portion of the top surface 109 of the package substrate 101 in the interior may not be covered. The other portion of the top surface 109 of the package substrate 101 in the first region R1 of the semiconductor package 10d may be exposed to the outside.

According to exemplary embodiments of the present invention, since the molding layer 140 is not formed in the first region R1 of the semiconductor package 10d provided with the antenna structure 150 , signal transmission using the antenna structure 150 . Efficiency may be improved and the size of the semiconductor package 10d may be reduced.

13 is a cross-sectional view illustrating a semiconductor package 10e according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 10e shown in FIG. 13 will be described with a focus on differences from the semiconductor package 10c described with reference to FIGS. 10 and 11 .

Referring to FIG. 13 , the semiconductor package 10e may include a cover insulating layer 166 for adjusting warpage provided on the upper surface 149 of the molding layer 140 . The cover insulating layer 166 may contact the upper surface 149 of the molding layer 140 and extend along the upper surface 149 of the molding layer 140 . The external conductive shielding layer 161 is provided on the cover insulating layer 166 and may extend along the surface of the cover insulating layer 166 . The cover insulating layer 166 may reduce warpage generated due to mismatch of thermal expansion coefficients between members constituting the semiconductor package 10e.

In example embodiments, the cover insulating layer 166 may include polyimide.

In example embodiments, the thickness of the cover insulating layer 166 may be between 10 micrometers and 15 micrometers.

The cover insulating layer 166 may cover at least a portion of the upper surface 149 of the molding layer 140 . In example embodiments, the cover insulating layer 166 may entirely cover the upper surface 149 of the molding layer 140 . In example embodiments, the cover insulating layer 166 may partially cover the upper surface 149 of the molding layer 140 .

14A is a cross-sectional view illustrating a semiconductor package 10f according to exemplary embodiments of the present invention. 14B is a cross-sectional view taken along line B1-B1' of FIG. 14A. In the following, duplicates of those described above will be omitted or simplified.

14A and 14B , the antenna structure 150a is disposed on the upper surface 109 of the package substrate 101 and may extend in the vertical direction (Z direction) within the molding layer 140 . For example, the antenna structure 150a is disposed between the side surface of the semiconductor chip 130 and the side surface of the molding layer 140 constituting the side surface of the semiconductor package 10f, and mainly through the side surface of the semiconductor package 10f. It may be configured to transmit and receive wireless signals. Each of the antenna structures 150a may be electrically connected to the semiconductor chip 130 through the wiring pattern 120 .

The antenna structure 150a may be formed of a conductive material pattern extending in the molding layer 140 . In this disclosure, the antenna structure 150a may be referred to as an antenna pattern. The antenna structure 150a may have a form that completely penetrates the molding layer 140 in the vertical direction (Z direction) or partially penetrates the molding layer 140 in the vertical direction (Z direction). For example, the antenna structure 150a may extend from the top surface 109 of the package substrate 101 to a point spaced apart from the top surface 149 of the molding layer 140 by a predetermined distance in the vertical direction (Z direction). The antenna structure 150a may be connected to the wiring pattern 120 , and may be electrically connected to the semiconductor chip 130 through the wiring pattern 120 .

In example embodiments, a vertical height of the antenna structure 150a may be greater than a vertical height of the semiconductor chip 130 . In example embodiments, the vertical height of the antenna structure 150a may be between 50% and 100% of the vertical height of the molding layer 140 .

In example embodiments, the antenna structure 150a may extend along sides of the molding layer 140 . The antenna structure 150a may be disposed between the inner conductive shielding layer 165 and the outer surface of the molding layer 140 . In a plan view, the antenna structure 150a may extend along the outer surface of the molding layer 140 .

In example embodiments, the antenna structure 150a may be in the form of a rectangular ring extending discontinuously in a plan view. For example, the antenna structure 150a may include four sidewalls, and each of the four sidewalls of the antenna structure 150a may be substantially parallel to an outer surface of the adjacent molding layer 140 . For example, when the molding layer 140 has four outer surfaces, the antenna structure 150a includes a first sidewall portion extending parallel to the first outer surface of the molding layer 140 and the molding layer 140 . The second sidewall portion extending parallel to the second outer surface, the third sidewall portion extending parallel to the third outer surface of the molding layer 140 , and the third sidewall portion extending parallel to the fourth outer surface of the molding layer 140 . 4 may include a sidewall portion.

The semiconductor package 10f may include an internal conductive shielding layer 165 extending in the vertical direction (Z direction) within the molding layer 140 . The internal conductive shielding layer 165 is disposed between the electronic component such as the semiconductor chip 130 and the antenna structure 150a in a plan view, and may have a ring shape extending to surround the electronic component such as the semiconductor chip 130 . have. For example, the inner conductive shielding layer 165 may have a ring shape surrounding the side surface of the semiconductor chip 130 in a plan view, and the antenna structure 150a surrounds the inner conductive shielding layer 165 in a plan view. may have a ring shape. In example embodiments, the inner conductive shielding layer 165 may have a rectangular ring shape in a plan view.

The internal conductive shielding layer 165 is disposed on the upper surface 109 of the package substrate 101 and may extend in the vertical direction (Z direction) within the molding layer 140 . The internal conductive shielding layer 165 may completely penetrate the molding layer 140 in the vertical direction (Z direction) or may partially penetrate the molding layer 140 .

For example, the internal conductive shielding layer 165 may include a conductive material such as copper (Cu) or aluminum (Al). In example embodiments, the material of the internal conductive shielding layer 165 and the material of the antenna structure 150a may be the same.

In example embodiments, a vertical height of the internal conductive shielding layer 165 may be greater than a vertical height of the semiconductor chip 130 . In example embodiments, the vertical height of the inner conductive shielding layer 165 may be between 50% and 100% of the height of the molding layer 140 . In example embodiments, the vertical height of the inner conductive shielding layer 165 may be greater than or equal to the vertical height of the antenna structure 150a.

In example embodiments, the inner conductive shielding layer 165 may be electrically grounded. For example, the internal conductive shielding layer 165 may be electrically grounded by being connected to a portion of the electrically grounded wiring pattern 120 .

The internal conductive shielding layer 165 may prevent electromagnetic interference between the electronic component included in the semiconductor package 10f and the antenna structure 150a. In addition, the internal conductive shielding layer 165 may improve the gain of the antenna structure 150a by reflecting a radio signal radiated from the antenna structure 150a or a radio signal to be received by the antenna structure 150a. .

15A is a cross-sectional view illustrating a semiconductor package 10g according to exemplary embodiments of the present invention. 15B is a cross-sectional view taken along line B2-B2' of FIG. 15A. In the following, duplicates of those described above will be omitted or simplified.

The semiconductor package 10g shown in FIGS. 15A and 15B may be substantially the same as or similar to the semiconductor package 10f described with reference to FIGS. 14A and 14B except for the structure of the internal conductive shielding layer 165 . have. Hereinafter, the semiconductor package 10g shown in FIGS. 15A and 15B will be described with a focus on differences from the semiconductor package 10f described with reference to FIGS. 14A and 14B .

15A and 15B , the internal conductive shielding layer 165a may include a cover part 1651 and a sidewall part 1653 . The cover part 1651 may cover the upper surface of the semiconductor chip 130 and may extend in a generally horizontal direction (eg, an X-direction and/or a Y-direction). The cover part 1651 may have a plate shape having a planar area covering electronic components such as the semiconductor chip 130 . The sidewall portion 1653 may have a ring shape surrounding the side surface of the semiconductor chip 130 in a plan view. The sidewall part 1653 may have a ring shape surrounding the side surface of the semiconductor chip 130 in a plan view, and the antenna structure 150a may have a ring shape surrounding the sidewall part 1653 in a plan view. The side wall portion 1653 may continuously extend along the edge of the cover portion 1651 in a plan view. The sidewall part 1653 may extend from the edge of the cover part 1651 to the upper surface 109 of the package substrate 101 in the vertical direction (Z direction).

In exemplary embodiments, the molding layer 140a is formed by forming the inner molding layer 141 on the inside of the inner conductive shielding layer 165a and the outer molding layer 143 on the outside of the inner conductive shielding layer 165a. may include The inner molding layer 141 and the outer molding layer 143 may be partitioned and separated by the inner conductive shielding layer 165a. In some example embodiments, the molding layer 140a may be formed through a first molding process for forming the inner molding layer 141 and a second molding process for forming the outer molding layer 143 . More specifically, to form the semiconductor package 10g, a step of mounting an electronic component such as a semiconductor chip 130 on the package substrate 101, a first molding process step for forming the inner molding layer 141 , forming the antenna structure 150a, forming the inner molding layer 141 and the outer molding layer 143 covering the antenna structure 150a may be sequentially performed.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure, and not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

10: semiconductor package 101: package substrate
130: semiconductor chip 140: molding layer
210: antenna structure

Claims (15)

a package substrate including a wiring pattern;
a semiconductor chip on the package substrate;
a molding layer disposed on the package substrate to cover the semiconductor chip;
a connection conductor penetrating the molding layer, extending from a lower surface to an upper surface of the molding layer, electrically connected to the wiring pattern of the package substrate, and including a first metal;
an antenna structure on the molding layer;
a conductive connection terminal disposed between the connection conductor and the connection pad of the antenna structure to electrically connect the connection conductor and the connection pad of the antenna structure, the conductive connection terminal including a second metal different from the first metal; and
a conductive interface layer disposed between the connection conductor and the conductive connection terminal, the conductive interface layer extending along a surface of the connection conductor facing the conductive connection terminal, and including the first metal and the second metal;
including,
The antenna structure is spaced apart by the molding layer, and a gap is formed between the antenna structure and the molding layer. The method of claim 1,
The first metal is solder and the second metal is copper. The method of claim 1,
A lower portion of the conductive connection terminal is buried in a connection conductor, and the semiconductor package extends from the top surface of the molding layer toward the bottom surface of the molding layer. The method of claim 1,
A vertical height and a maximum horizontal width of the connecting conductor are greater than a vertical height of the semiconductor chip,
The vertical height of the connecting conductor is between 300 micrometers and 1400 micrometers. The method of claim 1,
A distance between the upper surface of the molding layer and the antenna structure is between 4 micrometers and 25 micrometers. The method of claim 1,
The connecting conductor has an outwardly convex sidewall,
The horizontal width of the lower portion of the connecting conductor becomes smaller as it approaches the package substrate,
The horizontal width of the upper portion of the connecting conductor becomes smaller as it approaches the upper surface of the molding layer. The method of claim 1,
The connecting conductor is
a core portion including a first conductive material; and
a shell part including a second conductive material different from the first conductive material and surrounding the core part;
A semiconductor package comprising a. The method of claim 1,
The connecting conductor has a pillar shape having a straight sidewall, and a semiconductor package including solder. The method of claim 1,
A lower surface of the antenna structure facing the upper surface of the molding layer includes a first edge and a second edge opposite to each other,
The ratio between the distance between the first edge of the lower surface of the antenna structure and the upper surface of the molding layer and the distance between the second edge of the lower surface of the antenna structure and the upper surface of the molding layer is 80% to A semiconductor package that is between 110%. A semiconductor package comprising a first region and a second region separated from each other, the semiconductor package comprising:
a package substrate including a wiring pattern and an antenna pattern in the first region;
a semiconductor chip on the package substrate;
a molding layer disposed on the package substrate to cover the semiconductor chip; and
an external conductive shielding layer partially covering the molding layer;
including,
The external conductive shielding layer is provided in the second region, the semiconductor package spaced apart from the first region. 11. The method of claim 10,
The molding layer entirely covers the upper surface of the package substrate,
The external conductive shielding layer,
a portion of the upper surface of the molding layer in the second region is covered;
The semiconductor package does not cover the other portion of the upper surface of the molding layer so that another portion of the upper surface of the molding layer in the first region is exposed to the outside. 11. The method of claim 10,
The molding layer is
a portion of the upper surface of the package substrate in the second region is covered;
The semiconductor package does not cover the other portion of the upper surface of the package substrate so that another portion of the upper surface of the package substrate in the first region is exposed to the outside. 11. The method of claim 10,
Further comprising a cover insulating layer in contact with the upper surface of the molding layer and at least partially covering the upper surface of the molding layer,
The cover insulating layer is a semiconductor package including polyimide. a package substrate including a wiring pattern;
a semiconductor chip on the package substrate;
a molding layer disposed on the package substrate to cover the semiconductor chip;
an internal conductive shielding layer extending in a vertical direction in the molding layer and enclosing a side surface of the semiconductor chip; and
an antenna pattern extending in the vertical direction within the molding layer, disposed between the inner conductive shielding layer and an outer surface of the molding layer, and electrically connected to the semiconductor chip through the wiring pattern;
A semiconductor package comprising a. 15. The method of claim 14,
The internal conductive shielding layer,
a cover part covering an upper surface of the semiconductor chip; and
a sidewall portion extending to surround the side surface of the semiconductor chip and extending from an edge of the cover portion toward the package substrate;
A semiconductor package comprising a.

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