KR20230105759A - Semiconductor package including antenna - Google Patents

Abstract

The present invention relates to a semiconductor package including an antenna to increase the emission characteristics of an antenna. According to the present invention, the semiconductor package comprises: an antenna structure including a dielectric layer and an active antenna pattern on a first surface of the dielectric layer; a gapping insulating layer provided on the first surface of the dielectric layer; a lower vertical connection conductor penetrating the gapping insulating layer and electrically connected to the active antenna pattern; a first redistribution line structure provided on the gapping insulating layer and including a first conductive layer electrically connected to the active antenna pattern through the lower vertical connection conductor and a ground layer electrically grounded to an antenna ground layer; a semiconductor chip mounted on the first redistribution line structure and electrically connected to the active antenna pattern through the first conductive layer and the lower vertical connection conductor; a molding layer provided on the first redistribution line structure and surrounding a side surface of the semiconductor chip; upper vertical connection conductors laterally spaced from the semiconductor chip and penetrating the molding layer; and a second redistribution line structure provided on the molding layer and the semiconductor chip and including a second conductive layer connected to the upper vertical connection conductors.

Description

Semiconductor package including an antenna {SEMICONDUCTOR PACKAGE INCLUDING ANTENNA}

The technical idea of the present invention relates to a semiconductor package, and more particularly, to a semiconductor package including an antenna for transmitting and receiving a radio signal.

In electronic devices, integrated circuits are widely applied due to their advantages of small size, light weight, high reliability, and easy mass production. An integrated circuit package device may integrate all components required by a circuit having a specific function into one chip and package the chip on a package substrate. Components may include devices such as semiconductors, resistors, and capacitors, and connecting wires between devices. If the chip needs to receive or transmit radio signals, an antenna may be placed in the integrated circuit packaged device.

An object to be solved by the technical idea of the present invention is to provide a semiconductor package including an antenna.

An antenna structure comprising a dielectric layer and an active antenna pattern on a first surface of the dielectric layer; a gapping insulating layer provided on the first side of the dielectric layer; a lower vertical connection conductor passing through the gapping insulating layer and electrically connected to the active antenna pattern; a first redistribution structure provided on the gapping insulation layer and including a first conductive layer electrically connected to the active antenna pattern through the lower vertical connection conductor and an antenna ground layer electrically grounded; a semiconductor chip mounted on the first redistribution structure and electrically connected to the active antenna pattern through the first conductive layer and the lower vertical connection conductor; a molding layer provided on the first redistribution structure and surrounding side surfaces of the semiconductor chip; upper vertical connection conductors spaced apart from the semiconductor chip in a lateral direction and penetrating the molding layer; and a second redistribution structure including a second conductive layer provided on the molding layer and the semiconductor chip and connected to the upper vertical connection conductors.

In exemplary embodiments, a distance between the active antenna pattern and the antenna ground layer is between 200 micrometers and 500 micrometers.

In example embodiments, the upper vertical connection conductors may include first upper vertical connection conductors for signal transmission configured to transmit a signal input to the semiconductor chip or a signal output from the semiconductor chip; and second upper vertical connection conductors electrically grounded and configured to shield electromagnetic interference with the semiconductor chip.

In example embodiments, a horizontal distance between the second upper vertical connection conductors is smaller than a horizontal distance between the first upper vertical connection conductors.

In example embodiments, a heat dissipation pad at least partially covering one surface of the semiconductor chip may be included.

In example embodiments, an external heat dissipation terminal provided on the first region of the second redistribution structure and connected to the heat dissipation pad through a heat dissipation conductive layer and a heat dissipation via pattern provided in the second redistribution structure; and an external connection terminal provided on the second region of the second redistribution structure surrounding the first region of the second redistribution structure in plan view and connected to the second conductive layer.

In exemplary embodiments, the antenna structure further includes a parasitic antenna pattern provided on a second side opposite to the first side of the dielectric layer.

In exemplary embodiments, the thickness of the dielectric layer is between 100 micrometers and 300 micrometers.

In example embodiments, the first redistribution structure includes a redistribution insulation layer provided on the gapping insulation layer, and the redistribution insulation layer includes a material different from that of the dielectric layer.

In example embodiments, the active antenna pattern may include a first active antenna pattern configured to radiate or receive a radio signal of a first wavelength band; and a second active antenna pattern configured to radiate or receive radio signals of a second wavelength band different from the first wavelength band.

According to exemplary embodiments of the present invention, one side of the semiconductor chip on which the chip pad is formed faces the antenna structure, and the semiconductor chip is connected through the active antenna pattern of the antenna structure and the first conductive connection structure of the first redistribution structure. can be electrically connected. Accordingly, the length of the signal transmission path between the semiconductor chip and the antenna structure is reduced, thereby reducing signal loss and improving antenna radiation characteristics.

1 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
2A to 2D are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 1 .
FIG. 3 is a layout diagram showing some configurations of the semiconductor package of FIG. 1 .
4 is a layout diagram showing some configurations of a semiconductor package according to exemplary embodiments of the present invention.
5 is a cross-sectional view illustrating a first vertical connection conductor and a second vertical connection conductor of the semiconductor package of FIG. 1 .
6 is a cross-sectional view illustrating a portion of a semiconductor package according to exemplary embodiments of the present invention.
7 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the inventive concept.
8 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
9A to 9D are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 8 .

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, exemplary embodiments of the present disclosure may be modified in many different forms, and the scope of the present disclosure should not be construed as being limited due to the embodiments described below. Exemplary embodiments of the present disclosure are preferably interpreted as being provided to more completely explain the concept of the present disclosure to those with average knowledge in the art. The same sign means the same element throughout. Further, various elements and areas in the drawings are schematically drawn. Accordingly, the concepts of the present disclosure are not limited by the relative sizes or spacings drawn in the accompanying drawings.

Terms such as first and second may be used to describe various components, but the components are not limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and conversely, a second element may be termed a first element, without departing from the scope of the present disclosure.

Terms used in the present disclosure are used only to describe specific embodiments, and are not intended to limit the concept of the present disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the expression "comprises" or "has" is intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features or It should be understood that the presence or addition of a number, operation, component, part, or combination thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the concepts of the present disclosure belong. In addition, commonly used terms as defined in the dictionary should be interpreted as having a meaning consistent with what they mean in the context of the technology to which they relate, and in an overly formal sense unless explicitly defined herein. It will be understood that it should not be interpreted.

1 is a cross-sectional view illustrating a semiconductor package 10 according to exemplary embodiments of the present invention.

Referring to FIG. 1 , a semiconductor package 10 includes an antenna structure 110, a first redistribution structure 120, a semiconductor chip 130, a molding layer 143, a vertical connection conductor 150, and a second redistribution structure. A linear structure 160 and a heat dissipation pad 171 may be included.

The antenna structure 110 may include a dielectric layer 111 , an active antenna pattern 113 , and a parasitic antenna pattern 115 .

The dielectric layer 111 may include a first surface 111U and a second surface 111L opposite to each other. The dielectric layer 111 may have a substantially flat plate shape, and the first surface 111U and the second surface 111L may be planar. The first surface 111U and the second surface 111L of the dielectric layer 111 may be parallel to each other.

Hereinafter, the horizontal direction is defined as a direction parallel to the first surface 111U of the dielectric layer 111 (eg, the X direction and/or the Y direction), and the vertical direction is defined as a direction parallel to the first surface 111U of the dielectric layer 111 ( 111U) in a direction perpendicular to (eg, Z direction). In addition, the horizontal width or horizontal distance is defined as a length along the horizontal direction (eg, X direction and / or Y direction), and the thickness, vertical width or vertical distance is defined as a length along the vertical direction (eg, Z direction) Defined by length.

For example, the dielectric layer 111 may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are impregnated with glass fibers together with an inorganic filler, prepreg, or Ajinomoto Build-up (ABF). Film), FR-4, bismaleimide triazine (BT), and photo imagable dielectric (PID).

The dielectric layer 111 may have low dielectric constant and low dielectric loss characteristics. For example, the dielectric constant of the dielectric layer 111 may be 4 or less, 3.5 or less, 3 or less, or 2.5 or less. For example, the dissipation factor of the dielectric layer 111 may be 0.009 or less, 0.007 or less, 0.005 or less, or 0.003 or less.

In exemplary embodiments, the thickness of the dielectric layer 111 may be between 50 microns and 350 microns, between 100 microns and 300 microns, or between 150 microns and 250 microns. In exemplary embodiments, the thickness of the dielectric layer 111 may be 200 micrometers.

The active antenna pattern 113 may be disposed on the first surface 111U of the dielectric layer 111 facing the semiconductor chip 130 . In example embodiments, the active antenna pattern 113 may have a structure and shape suitable for performing communication in a predetermined wavelength band. In exemplary embodiments, the active antenna pattern 113 may be configured to radiate or receive a radio signal in the millimeter wavelength band. The active antenna pattern 113 may function as a radiator of an antenna and/or a director of an antenna. For example, the active antenna pattern 113 may include a patch antenna or a dipole antenna.

In exemplary embodiments, the spacing between two neighboring active antenna patterns 113 is between 10% and 400%, between 30% and 300%, or between 50% and 400% of the horizontal width of the active antenna pattern 113. It can be between 150%. In some exemplary embodiments, a spacing between two neighboring active antenna patterns 113 may be equal to a horizontal width of the active antenna pattern 113 .

In exemplary embodiments, the active antenna pattern 113 includes at least one first active antenna pattern configured to radiate or receive a radio signal of a first wavelength band and a radio signal of a second wavelength band different from the first wavelength band. It may include at least one second active antenna pattern configured to radiate or receive. The at least one first active antenna pattern and the at least one second active antenna pattern may be electrically connected to the semiconductor chip 130 through different electrical connection paths. The at least one first active antenna pattern and the at least one second active antenna pattern may have different shapes and/or different dimensions (eg, different horizontal widths).

The parasitic antenna pattern 115 may be disposed on the second surface 111L of the dielectric layer 111 . For example, the parasitic antenna pattern 115 may function to extend the bandwidth of wireless communication using the active antenna pattern 113. The parasitic antenna pattern 115 may be spaced apart from the active antenna pattern 113 in a vertical direction (eg, a Z direction) with the dielectric layer 111 interposed therebetween. The parasitic antenna pattern 115 may be a patch antenna having a polygonal shape such as a circle or a quadrangular in plan view, or may be a line shape formed on the second surface 111L of the dielectric layer 111 . The antenna structure 110 may further include a protective insulating layer 119 covering the second surface 111L of the dielectric layer 111 and the parasitic antenna pattern 115 .

In exemplary embodiments, the parasitic antenna pattern 115 may have the same shape as the active antenna pattern 113 in a plan view, and the parasitic antenna pattern 115 and the active antenna pattern 113 may overlap in a plan view. can In other exemplary embodiments, the shape of the parasitic antenna pattern 115 may be different from the shape of the active antenna pattern 113 .

In example embodiments, the parasitic antenna pattern 115 may be exposed to the outside. For example, the protective insulating layer 119 may be omitted so that the parasitic antenna pattern 115 is exposed to the outside.

In exemplary embodiments, the protective insulating layer 119 may be omitted, and the parasitic antenna pattern 115 may be at least partially buried in the dielectric layer 111 . The parasitic antenna pattern 115 is partially buried in the dielectric layer 111, but a portion of the parasitic antenna pattern 115 may be exposed to the outside. For example, the lower surface of the parasitic antenna pattern 115 may be exposed to the outside.

The active antenna pattern 113 and the parasitic antenna pattern 115 may include a conductive material. For example, the active antenna pattern 113 and the parasitic antenna pattern 115 may include a metal such as copper (Cu) or aluminum (Al).

The first redistribution structure 120 is provided on the first surface 111U of the dielectric layer 111 and may function as a mounting substrate on which the semiconductor chip 130 is mounted. The first redistribution structure 120 may include a plurality of first redistribution insulating layers 121 and a first conductive connection structure 123 .

The plurality of first redistribution insulating layers 121 may be stacked on the first surface 111U of the dielectric layer 111 in a vertical direction (eg, a Z direction). The plurality of first redistribution insulating layers 121 may be formed of an insulating polymer, epoxy, or a combination thereof. In example embodiments, each of the plurality of first redistribution insulating layers 121 may be formed of a material different from a material constituting the dielectric layer 111 . In example embodiments, the dielectric constant of each of the plurality of first redistribution insulating layers 121 may be different from that of the dielectric layer 111 .

The first conductive connection structure 123 includes the first conductive layers 1231 disposed on one of the top and bottom surfaces of each of the plurality of first redistribution insulating layers 121, and the plurality of first redistribution layers 123. It may include first conductive via patterns 1233 penetrating at least one of the insulating layers 121 and extending in a vertical direction (eg, a Z direction). The first conductive layers 1231 may be disposed at different vertical levels to form a multilayer structure. Each of the first conductive layers 1231 may include a line pattern extending in a line shape on one of upper and lower surfaces of each of the plurality of first redistribution insulating layers 121 . The first conductive layer 1231 provided on the uppermost insulating layer among the plurality of first redistribution insulating layers 121 includes pads to which chip connection bumps 141 for electrical connection with the semiconductor chip 130 are attached. , lower pads to which the vertical connection conductors 150 are connected. The first conductive via patterns 1233 may electrically connect first conductive layers 1231 disposed at different vertical levels. The first conductive via pattern 1233 provided in the lowest insulating layer among the plurality of first redistribution insulating layers 121 may be connected to the active antenna pattern 113 .

The semiconductor chip 130 may be mounted on the first redistribution structure 120 in a flip chip method. The semiconductor chip 130 may include upper and lower surfaces opposite to each other, and the lower surface of the semiconductor chip 130 may be a pad surface on which the chip pad 131 is provided. The semiconductor chip 130 may be mounted on the first redistribution structure 120 so that the lower surface on which the chip pads 131 are provided faces the first redistribution structure 120 . Chip connection bumps 141 such as micro bumps may be disposed between the semiconductor chip 130 and the first redistribution structure 120 . The semiconductor chip 130 may be electrically connected to the first conductive connection structure 123 of the first redistribution structure 120 through the chip connection bump 141 .

A plurality of individual devices of various types may be formed in the semiconductor chip 130 . For example, the plurality of individual elements may be various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-oxide-semiconductor transistor (CMOS transistor), a system large scale LSI (large scale integration), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), a power management (PM) IC, an active element, a passive element, and the like.

In example embodiments, the semiconductor chip 130 is a communication semiconductor chip electrically or signal-transmitably connected to the antenna structure 110, and a signal processing circuit for processing a radio signal transmitted and received through the antenna structure 110. etc. may be included. For example, the semiconductor chip 130 may include a Radio-Frequency Integrated Circuit (RFIC).

In example embodiments, the semiconductor chip 130 may be, for example, a memory chip. The memory chip is, for example, a volatile memory chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM ( It may be a non-volatile memory chip such as Ferroelectric Random Access Memory) or Resistive Random Access Memory (RRAM).

Alternatively, in example embodiments, the semiconductor chip 130 may be a logic chip. For example, the semiconductor chip 130 may be a Central Processor Unit (CPU), Micro Processor Unit (MPU), Graphic Processor Unit (GPU), or Application Processor (AP).

The semiconductor package 10 may include one semiconductor chip 130 or may include two or more semiconductor chips 130 . The two or more semiconductor chips 130 included in the semiconductor package 10 may be of the same type or of different types. In example embodiments, the semiconductor package 10 may be a system in package in which different types of semiconductor chips and various electronic components are electrically connected to each other to operate as a system.

In example embodiments, a passive component 145 may be mounted on the first redistribution structure 120 . The passive component 145 may be spaced apart from the semiconductor chip 130 in a lateral direction. The passive component 145 may include a capacitor, an inductor, a resistor, an integrated passive device (IPD), and the like.

The molding layer 143 is provided on the first redistribution structure 120 and may cover at least a portion of the semiconductor chip 130 and at least a portion of the passive component 145 . In example embodiments, the molding layer 143 may cover the side surface of the semiconductor chip 130 but may not cover the top surface of the semiconductor chip 130 . In this case, the upper surface of the molding layer 143 and the upper surface of the semiconductor chip 130 may be on the same plane. In other exemplary embodiments, the molding layer 143 may cover top and side surfaces of the semiconductor chip 130 . In addition, the molding layer 143 fills the gap between the semiconductor chip 130 and the first redistribution structure 120 and forms a chip connection bump 141 between the semiconductor chip 130 and the first redistribution structure 120 . ) can be surrounded. The molding layer 143 may be formed of, for example, an epoxy molding compound, but is not limited thereto.

The vertical connection conductor 150 is provided in the molding layer 143 and may be spaced apart from the semiconductor chip 130 in a lateral direction. The vertical connection conductor 150 extends in a substantially vertical direction (eg, Z direction) within the molding layer 143 and may pass through the molding layer 143 . The vertical connection conductor 150 may have a pillar shape extending in a vertical direction (eg, Z direction) within the molding layer 143 . A lower surface of the vertical connection conductor 150 may contact the first redistribution structure 120 and an upper surface of the vertical connection conductor 150 may contact the second redistribution structure 160 . More specifically, the lower surface of the vertical connection conductor 150 is in contact with the lower pad of the first conductive layer 1231 on the uppermost insulating layer among the plurality of first redistribution insulating layers 121, and is vertically connected. An upper surface of the conductor 150 may contact an upper pad of the second conductive layer 1631 in the lowermost insulating layer among the plurality of second redistribution insulating layers 161 described later.

For example, the vertical connection conductor 150 is copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au), palladium (Pd) or a combination thereof.

In exemplary embodiments, the diameter (or horizontal width) of the vertical connection conductor 150 may be between 20 micrometers and 50 micrometers.

In example embodiments, the vertical connection conductor 150 may be a conductive post formed through a plating process and containing copper.

In example embodiments, the vertical connection conductor 150 may include a conductive wire formed through a bonding wire process. For example, when the vertical connection conductor 150 is formed of a conductive wire, a bonding wire process is performed on the lower pad of the first conductive layer 1231 on the first redistribution insulating layer 121 of the uppermost layer. A step of forming a conductive wire through a molding step, a molding step of forming a molding material constituting a molding layer 143 covering the semiconductor chip 130 and the conductive wire, and removing a portion of the molding material to expose the conductive wire. A polishing step and a step of forming the second redistribution structure 160 on the molding layer 143 may be sequentially performed.

The second redistribution structure 160 may be provided on the molding layer 143 and the semiconductor chip 130 . The second redistribution structure 160 may include a plurality of second redistribution insulating layers 161 and a second conductive connection structure 163 .

A plurality of second redistribution insulating layers 161 are provided on the upper surface of the molding layer 143 and may be mutually stacked in a vertical direction (eg, a Z direction). The plurality of second redistribution insulating layers 161 may be formed of an insulating polymer, epoxy, or a combination thereof. In example embodiments, the plurality of second redistribution insulating layers 161 may be formed of a material different from a material constituting the dielectric layer 111 . In example embodiments, the dielectric constant of each of the plurality of second redistribution insulating layers 161 may be different from that of the dielectric layer 111 .

The second conductive connection structure 163 includes second conductive layers 1631 disposed on one of upper and lower surfaces of each of the plurality of second redistribution insulating layers 161 and a plurality of second redistribution layers 163 . It may include second conductive via patterns 1633 penetrating at least one of the insulating layers 161 and extending in a vertical direction (eg, Z direction). The second conductive layers 1631 may be disposed at different vertical levels to form a multilayer structure. Each of the second conductive layers 1631 may include a line pattern extending in a line shape on one of upper and lower surfaces of each of the plurality of second redistribution insulating layers 161 . The second conductive layer 1631 provided on the uppermost insulating layer among the plurality of second redistribution insulating layers 161 may constitute an external pad to which the external connection terminal 191 is attached. The second conductive layer 1631 provided in the lowermost insulating layer among the plurality of second redistribution insulating layers 161 may constitute an upper pad connected to the vertical connection conductor 150 . The second conductive via patterns 1633 may electrically connect second conductive layers 1631 disposed at different vertical levels.

In example embodiments, the horizontal width of the upper pad of the second conductive layer 1631 attached to the top of the vertical connection conductor 150 is the first conductive layer attached to the bottom of the vertical connection conductor 150. It may be greater than or equal to the horizontal width of the lower pad of (1231). For example, the horizontal width of the upper pad of the second conductive layer 1631 may be between 1 and 10 times or between 3 and 10 times the horizontal width of the lower pad of the first conductive layer 1231 . When the vertical connection conductor 150 is formed of a conductive wire, the conductive wire is shifted from a predetermined target position during a molding process for forming the molding layer 143, and the conductive wire is shifted to a second position by the shift of the conductive wire. A problem of not being able to contact the conductive layer 1631 may occur. In the present embodiments, by forming the horizontal width of the upper pad of the second conductive layer 1631 to be greater than or equal to the horizontal width of the lower pad of the first conductive layer 1231, a vertical connection conductor implemented with a conductive wire Reliability of an electrical connection between the layer 150 and the upper pad of the second conductive layer 1631 may be improved.

The external connection terminal 191 is attached on the second redistribution structure 160 and can electrically connect the semiconductor package 10 and an external device. For example, the external connection terminal 191 may include a solder ball or a solder bump. A signal provided from an external device (eg, a data signal, a control signal, a power signal, and/or a ground signal) is transmitted through the external connection terminal 191, the second conductive connection structure 163 of the second redistribution structure 160, will be provided to the semiconductor chip 130 through a signal transmission path sequentially passing through the vertical connection conductor 150, the first conductive connection structure 123 of the first redistribution structure 120, and the chip connection bump 141. can In addition, the signal output from the semiconductor chip 130 is connected to the chip connection bump 141, the first conductive connection structure 123 of the first redistribution structure 120, the vertical connection conductor 150, and the second redistribution structure. It may be provided to an external device through a signal transmission path sequentially passing through the second conductive connection structure 163 of 160 and the external connection terminal 191 .

The vertical connection conductor 150 includes first vertical connection conductors 151 for signal transmission configured to transmit an input signal input to the semiconductor chip 130 or an output signal output from the semiconductor chip 130; Second vertical connection conductors 153 configured to shield electromagnetic interference (EMI) from the semiconductor chip 130 may be included.

The first vertical connection conductors 151 may be configured to transmit a data signal, a control signal, a power signal, and/or a ground signal transmitted to the semiconductor chip 130, or an output output from the semiconductor chip 130. It can be configured to transmit a signal.

The second vertical connection conductors 153 are arranged to surround the semiconductor chip 130 in plan view, and prevent electromagnetic interference between an external environment and electronic components such as the semiconductor chip 130 included in the semiconductor package 10. It can play a shielding role. In example embodiments, as shown in FIG. 1 , the second vertical connection conductors 153 may be arranged to surround a region including the semiconductor chip 130 and the passive component 145 in a plan view. there is.

In example embodiments, the distance between the first vertical connection conductors 151 and/or the distance between the second vertical connection conductors 153 may be determined according to a frequency band supported by the semiconductor chip 130. .

The second vertical connection conductors 153 may be electrically grounded. For example, the second vertical connection conductors 153 include an external connection terminal 191 to which a ground signal (or ground voltage) provided from the outside is applied, a first conductive layer 1231, and a first conductive via pattern. It may be configured to receive a ground signal through 1233. In some example embodiments, a ground signal provided from the outside may be applied to the chip pad 131 of the semiconductor chip 130 via at least one of the second vertical connection conductors 153 .

Furthermore, the second redistribution structure 160 may include a first conductive shielding layer 169 configured to be electrically grounded to shield electromagnetic interference to the semiconductor chip 130 . The first conductive shielding layer 169 may be disposed on any one of upper and lower surfaces of each of the plurality of second redistribution insulating layers 161, and may be disposed on the first surface 111U of the dielectric layer 111. can be extended in parallel. The first conductive shielding layer 169 may have a plane or flat plate shape covering a region where electronic components such as the semiconductor chip 130 are mounted.

The first conductive shielding layer 169 may be electrically grounded. For example, the first conductive shielding layer 169 may be electrically connected to the second vertical connection conductor 153 that is electrically grounded.

The heat dissipation pad 171 may contact the top surface of the semiconductor chip 130 and cover at least a portion of the top surface of the semiconductor chip 130 . In example embodiments, the heat dissipation pad 171 may entirely cover the upper surface of the semiconductor chip 130 . In example embodiments, the heat dissipation pad 171 may partially cover the upper surface of the semiconductor chip 130 .

In example embodiments, the heat dissipation pad 171 may be positioned at the same level as the second conductive layer 1631 positioned at the lowermost layer among the second conductive layers 1631 . For example, the heat dissipation pad 171 may be formed together through a metal wiring process for forming the second conductive layer 1631 positioned at the lowermost layer among the second conductive layers 1631 . In this case, the heat dissipation pad 171 may include the same material as that of the second conductive layer 1631 . In other exemplary embodiments, the heat dissipation pad 171 may be formed in a separate step different from a metal wiring process for forming the second conductive layer 1631 positioned at the lowermost layer among the second conductive layers 1631 . may be

In example embodiments, the heat dissipation pad 171 may cover the upper surface of the semiconductor chip 130 and may protrude laterally from the side surface of the semiconductor chip 130 to further cover the upper surface of the molding layer 143 . The planar area of the heat dissipation pad 171 may be greater than that of the semiconductor chip 130 , and may cover the entire top surface of the semiconductor chip 130 and a portion of the top surface of the molding layer 143 around the semiconductor chip 130 from a plan view. can be formed

A plurality of heat dissipation conductive layers 173 and a plurality of heat dissipation via patterns 175 thermally coupled to the heat dissipation pad 171 may be provided in the second redistribution structure 160 . The plurality of heat dissipation conductive layers 173 may be disposed on any one of upper and lower surfaces of each of the plurality of second redistribution insulating layers 161 , and the plurality of heat dissipation via patterns 175 may be disposed on the plurality of second redistribution insulating layers 161 . It may extend in a vertical direction (eg, Z direction) through at least one layer of the redistribution insulating layer 161 . The plurality of heat dissipation conductive layers 173 may be disposed at different vertical levels to form a multilayer structure. At least one external heat dissipation terminal 193 may be attached to the heat dissipation conductive layer 173 disposed on the top surface of the uppermost second redistribution insulating layer 161 among the plurality of heat dissipation conductive layers 173 . The plurality of heat dissipation via patterns 175 may connect heat dissipation conductive layers 173 disposed at different vertical levels. The plurality of heat dissipation conductive layers 173 and the plurality of heat dissipation via patterns 175 include metal for forming the second conductive layers 1631 and the second conductive via patterns 1633 of the second redistribution structure 160 . They can be formed together through a wiring process. Each of the plurality of heat dissipation conductive layers 173 may be formed of the same material as the material of the second conductive layer 1631, and each of the plurality of heat dissipation via patterns 175 may be formed of the same material as that of the second conductive via pattern 1633. can be formed According to the exemplary embodiments, heat generated in the semiconductor chip 130 can be quickly discharged to the outside through the heat dissipation pad 171, the plurality of heat dissipation conductive layers 173, and the plurality of heat dissipation via patterns 175. , heat generation issues of the semiconductor chip 130 can be alleviated.

The external heat dissipation terminal 193 is disposed in the first region of the second redistribution structure 160, and the external connection terminal 191 is disposed in the second region of the second redistribution structure 160 separated from the first region. can be placed. In example embodiments, the first region of the second redistribution structure 160 where the external heat dissipation terminal 193 is disposed is the central portion of the second redistribution structure 160 and the external connection terminal 191 is disposed. The second region of the second redistribution structure 160 may be an outer portion of the second redistribution structure 160 . In example embodiments, the second region of the second redistribution structure 160 where the external connection terminal 191 is disposed is the top of the second redistribution structure 160 where the external heat dissipation terminal 193 is disposed in a plan view. It may surround the first region.

In some exemplary embodiments, the heat dissipation pad 171 , the plurality of heat dissipation conductive layers 173 , the plurality of heat dissipation via patterns 175 , and at least one external heat dissipation terminal 193 may be connected to the semiconductor chip 130 . It can be distinguished from the second conductive connection structure 163 in that it is not electrically connected.

In some exemplary embodiments, the heat dissipation pad 171, the plurality of heat dissipation conductive layers 173, the plurality of heat dissipation via patterns 175, and the external heat dissipation terminal 193 may be electrically grounded, and the semiconductor chip A path for passing a ground signal to 130 may be configured.

When the heat dissipation pad 171, the plurality of heat dissipation conductive layers 173, and the plurality of heat dissipation via patterns 175 are electrically grounded, the heat dissipation pad 171 and/or the plurality of heat dissipation conductive layers 173 have a first conductivity Similar to the shielding layer 169 , it may function to shield electromagnetic wave interference with respect to the semiconductor chip 130 .

In some exemplary embodiments, the heat dissipation pad 171 may pass through the plurality of second redistribution insulating layers 161 . The heat dissipation pad 171 is formed to have a thickness similar to the total thickness of the plurality of second redistribution insulating layers 161 and may be exposed to the outside. In this case, the plurality of heat dissipation conductive layers 173 , the plurality of heat dissipation via patterns 175 , and the external heat dissipation terminal 193 may be omitted.

In example embodiments, the second redistribution structure 160 may include an antenna ground layer 181 . The antenna ground layer 181 may have a plane or flat plate shape extending along the surface of any one of the plurality of second redistribution insulating layers 161 . For example, the antenna ground layer 181 is along the upper surface of the second redistribution insulating layer 161 under the uppermost second redistribution insulating layer 161 among the plurality of second redistribution insulating layers 161. may be extended. The antenna ground layer 181 is substantially parallel to each of the active antenna patterns 113, and capacitance may be formed between the antenna ground layer 181 and the active antenna patterns 113. As shown in the cross-sectional view, the horizontal width of the antenna ground layer 181 may be greater than the horizontal width of each of the active antenna patterns 113 . For example, from a plan view, an area where the antenna ground layer 181 is disposed may be larger than an area where the active antenna patterns 113 are disposed. In other words, from a plan view, a region including all of the active antenna patterns 113 may be within a region including the antenna ground layer 181 .

The antenna ground layer 181 may be electrically grounded. For example, the antenna ground layer 181 is formed through an external connection terminal 191 to which a ground signal (or ground voltage) provided from the outside is applied, the first conductive layer 1231, and the first conductive via pattern 1233. It may be configured to receive a ground signal.

The size of the antenna ground layer 181, the vertical distance (VD) between the antenna ground layer 181 and the active antenna pattern 113, and each of the materials provided between the antenna ground layer 181 and the active antenna pattern 113 The dielectric constant may affect antenna radiation characteristics using the antenna structure 110 .

In exemplary embodiments, a vertical distance (VD) between the antenna ground layer 181 and the active antenna pattern 113 may be between 200 micrometers and 500 micrometers, or between 300 micrometers and 400 micrometers.

In example embodiments, in order to adjust antenna radiation characteristics, dielectric constants of material(s) provided between the antenna ground layer 181 and the active antenna pattern 113 may be adjusted. For example, in order to adjust antenna radiation characteristics, the dielectric constant of the first redistribution insulating layer 121, the dielectric constant of the molding layer 143, and/or the dielectric constant of the second redistribution insulating layer 161 may be adjusted. can be adjusted

According to exemplary embodiments of the present invention, the semiconductor chip 130 has one surface on which the chip pad 131 is formed facing the antenna structure 110, and the semiconductor chip 130 is an active antenna of the antenna structure 110. The pattern 113 may be electrically connected through the first conductive connection structure 123 of the first redistribution structure 120 . Accordingly, the length of the signal transmission path between the semiconductor chip 130 and the antenna structure 110 is reduced, thereby reducing signal loss and improving antenna radiation characteristics.

2A to 2D are cross-sectional views illustrating a method of manufacturing the semiconductor package 10 shown in FIG. 1 . Hereinafter, a method of manufacturing the semiconductor package 10 illustrated in FIG. 1 will be described with reference to FIGS. 2A to 2D.

Referring to FIG. 2A , an antenna structure 110 is prepared. For example, the antenna structure 110 forms an active antenna pattern 113 and a parasitic antenna pattern 115 on the first surface 111U and the second surface 111L of the dielectric layer 111 provided in the form of a film. and forming a protective insulating layer 119 on the second surface 111L of the dielectric layer 111 . Optionally, after forming the antenna structure 110, a test process for performance testing of the antenna structure 110 may be performed. A subsequent manufacturing process is performed on the antenna structure 110 determined to be good in the test process, and the antenna structure 110 determined to be defective is discarded or undergoes a repair process to remove defective elements.

Referring to FIG. 2B , a first redistribution structure 120 is formed on the antenna structure 110 . In order to form the first redistribution structure 120, a first step of forming a first redistribution insulating layer 121 including a via hole, and a first redistribution insulating layer 121 extending along an upper surface of the first redistribution layer 121 A second step of forming a first conductive via pattern 1233 in the via hole of the first conductive layer 1231 and the first redistribution insulating layer 121 is performed, and the first and second steps are repeated several times. can do.

Referring to FIG. 2C , after forming the first redistribution structure 120 , a semiconductor chip 130 and a passive component 145 are mounted on the first redistribution structure 120 .

Referring to FIG. 2D , after the semiconductor chip 130 and the passive component 145 are mounted on the first redistribution structure 120, the vertical connection conductors 150 are formed on the first redistribution structure 120. and forming a molding layer 143 . For example, after forming the vertical connection conductor 150, a molding material covering the semiconductor chip 130 and the vertical connection conductors 150 is formed on the first redistribution structure 120, and the semiconductor chip is formed. A polishing process may be performed to remove a portion of the molding material and a portion of the semiconductor chip 130 until the 130 and the vertical connection conductors 150 are exposed. Another part of the molding material remaining after the polishing process may constitute the molding layer 143 . The polishing process may include a planarization process such as chemical mechanical polishing. Through the polishing process, a portion of the molding material, a portion of the semiconductor chip 130, and a portion of each of the vertical connection conductors 150 may be removed. can The top surface of the molding layer 143 obtained through the polishing process, the top surface of the semiconductor chip 130, and the top surfaces of the vertical connection conductors 150 may be planarized surfaces, and the top surface of the molding layer 143, the semiconductor The top surface of the chip 130 and the top surfaces of the vertical connection conductors 150 may be on the same plane.

Referring to FIG. 1 , after forming the vertical connection conductors 150 and the molding layer 143, a second redistribution structure 160 is formed on the upper surface of the semiconductor chip 130 and the upper surface of the molding layer 143. can form The method of forming the second redistribution structure 160 may be substantially the same as or similar to the method of forming the first redistribution structure 120 . The heat dissipation pad 171, the heat dissipation conductive layers 173, the heat dissipation via patterns 175, and the antenna ground layer 181 constitute the second conductive connection structure 163 of the second redistribution structure 160. The second conductive layers 1631 and the second conductive via patterns 1633 may be formed together through a metal wiring process. After forming the second redistribution structure 160 , an external connection terminal 191 may be formed on the second redistribution structure 160 .

FIG. 3 is a layout diagram showing some configurations of the semiconductor package 10 of FIG. 1 .

Referring to FIG. 3 together with FIG. 1 , the second vertical connection conductors 153 for electromagnetic wave shielding of the semiconductor chip 130 may be arranged along an edge of the semiconductor chip 130 in a plan view. The second vertical connection conductors 153 may be arranged to surround the semiconductor chip 130 in plan view. In other words, the second vertical connection conductors 153 may be disposed along an imaginary line, for example, a quadrangular imaginary line, that surrounds the mounting area where the semiconductor chip 130 is disposed in a plan view.

As illustrated, the second vertical connection conductors 153 may be spaced apart from each other at relatively narrow intervals. In example embodiments, the horizontal distance 153P between the second vertical connection conductors 153 may be smaller than the horizontal distance 151P between the first vertical connection conductors 151 .

4 is a layout diagram showing some configurations of a semiconductor package according to exemplary embodiments of the present invention.

Referring to FIG. 4 , the second vertical connection conductors 153 may be disposed between the semiconductor chip 130 and the passive component 145 . When viewed from a plan view, the second vertical connection conductors 153 are disposed to surround the semiconductor chip 130, and the passive component 145 includes the second vertical connection conductors 153 and the first vertical connection conductors. (151).

FIG. 5 is a cross-sectional view illustrating the first vertical connection conductor 151 and the second vertical connection conductor 153 of the semiconductor package 10 of FIG. 1 .

Referring to FIG. 5 together with FIG. 1 , the first vertical connection conductor 151 includes a first core conductor 1511 and a first barrier conductive layer 1513 covering the outer surface of the first core conductor 1511 . ) may be included. The first core conductor 1511 may have a pillar shape extending in a vertical direction (eg, a Z direction) within the molding layer 143 . The first barrier conductive layer 1513 is disposed between the side surface of the first core conductor 1511 and the molding layer 143 and may entirely cover the side surface of the first core conductor 1511 . The first barrier conductive layer 1513 may have a cylindrical shape surrounding the side surface of the first core conductor 1511 .

The first core conductor 1511 and the first barrier conductive layer 1513 may be formed of different materials. For example, the first core conductor 1511 may include a material having higher electrical conductivity than the first barrier conductive layer 1513 . For example, the first core conductor 1511 may be formed of copper, and the first barrier conductive layer 1513 may be formed of palladium.

Also, the second vertical connection conductor 153 may include a second core conductor 1531 and a second barrier conductive layer 1533 covering an outer surface of the second core conductor 1531 . The second core conductor 1531 may be substantially the same as the first core conductor 1511, and the second barrier conductive layer 1533 may be substantially the same as the first barrier conductive layer 1513. , detailed descriptions thereof are omitted.

6 is a cross-sectional view illustrating a portion of a semiconductor package according to exemplary embodiments of the present invention.

Referring to FIG. 6 , the heat dissipation pad 171 is buried in the molding layer 143 , and side surfaces of the heat dissipation pad 171 may contact the molding layer 143 . The top surface of the semiconductor chip 130 may be positioned at a level lower than the top surface of the molding layer 143 , and the heat dissipation pad 171 may be provided between the top surface of the semiconductor chip 130 and the top surface of the molding layer 143 .

7 is a cross-sectional view illustrating a semiconductor package 12 according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 12 shown in FIG. 7 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1 .

Referring to FIG. 7 , the semiconductor package 12 includes an antenna structure 110a, a first redistribution structure 120a, a semiconductor chip 130, a molding layer 143, a vertical connection conductor 150, and a second redistribution structure. A linear structure 160 and a heat dissipation pad 171 may be included.

The antenna structure 110a includes a dielectric layer 111 including a first surface 111U and a second surface 111L opposite to each other, an active antenna pattern 113 on the second surface 111L of the dielectric layer 111, and a dielectric layer. The connection pad 116 on the first surface 111U of (111), the first antenna ground layer 117U on the first surface 111U of the dielectric layer 111, and the second surface 111L of the dielectric layer 111 A second antenna ground layer 117L may be included. A protective insulating layer 119 may be disposed on the second surface 111L of the dielectric layer 111 to cover the active antenna pattern 113 and the second antenna ground layer 117L.

The active antenna pattern 113 may be electrically connected to the connection pad 116 disposed on the first surface 111U of the dielectric layer 111 through the first antenna via pattern 114 extending through the dielectric layer 111. can The active antenna pattern 113 may be electrically connected to the semiconductor chip 130 through the first antenna via pattern 114, the connection pad 116, the first conductive connection structure 123a, and the chip connection bump 141. there is.

The first antenna ground layer 117U may be disposed on the first surface 111U opposite to the second surface 111L of the dielectric layer 111 on which the active antenna pattern 113 is disposed. The first antenna ground layer 117U is disposed to face at least a portion of each of the active antenna patterns 113, and capacitance may be formed between the first antenna ground layer 117U and the active antenna patterns 113. . The first antenna ground layer 117U may be electrically grounded. The first antenna ground layer 117U includes an external connection terminal 191 to which a ground signal (or ground voltage) provided from the outside is applied, a second conductive connection structure 163, a vertical connection conductor 150, and a first conductive It may be configured to receive a ground signal through the connection structure 123a body.

In exemplary embodiments, a vertical distance between the first antenna ground layer 117U and the active antenna pattern 113 may be between 200 micrometers and 500 micrometers, or between 300 micrometers and 400 micrometers. In example embodiments, a vertical distance between the first antenna ground layer 117U and the active antenna pattern 113 may be equal to the thickness of the dielectric layer 110a.

The second antenna ground layer 117L is disposed on the second surface 111L of the dielectric layer 111 on which the active antenna pattern 113 is disposed, and may be spaced apart from the active antenna pattern 113 in a lateral direction. The second antenna ground layer 117L may be electrically grounded, and the second antenna ground layer 117L may be connected to the first antenna ground layer (117L) through the second antenna via pattern 118 extending through the dielectric layer 111. 117U) can be electrically connected. The second antenna ground layer 117L may be disposed around the active antenna pattern 113 to remove noise signals.

In example embodiments, a horizontal distance between the second antenna ground layer 117L and the active antenna pattern 113 may be 400 micrometers or more. A horizontal distance between the second antenna ground layer 117L and the active antenna pattern 113 may be between 400 micrometers and 1000 micrometers, or between 500 micrometers and 900 micrometers.

In example embodiments, the first conductive wiring structure of the first redistribution structure 120a may include a second conductive shielding layer 1235 . The second conductive shielding layer 1235 may be disposed on any one of upper and lower surfaces of each of the plurality of first redistribution insulating layers 121 . The second conductive shielding layer 1235 may be formed together through a metal wiring process for forming the first conductive layers 1231, and the same vertical level as any one of the first conductive layers 1231. can be located in The second conductive shielding layer 1235 may include the same material as the first conductive layer 1231 .

The second conductive shielding layer 1235 may be electrically grounded. For example, the second conductive shielding layer 1235 may be electrically connected to the second vertical connection conductor 153 that is electrically grounded.

The second conductive shielding layer 1235 may extend parallel to the first surface 111U of the dielectric layer 111 and may extend in a vertical direction perpendicular to the first surface 111U of the dielectric layer 111 (eg, Z direction) may be disposed between the semiconductor chip 130 and the antenna structure 110a. The second conductive shielding layer 1235 may have a plane or flat plate shape that at least partially overlaps a region where an electronic component such as the semiconductor chip 130 is mounted, from a plan view. The second conductive shielding layer 1235 may function as an electromagnetic wave shielding member for electronic components such as the semiconductor chip 130, and furthermore, a radio signal radiated from the antenna structure 110a or a radio signal received through the antenna structure 110a. It can function to improve the antenna gain by reflecting the signal.

8 is a cross-sectional view illustrating a semiconductor package 14 according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 14 shown in FIG. 8 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1 .

Referring to FIG. 8 , the semiconductor package 12 includes an antenna structure 110, a first redistribution structure 120, a semiconductor chip 130, a molding layer 143, a vertical connection conductor 150, and a second redistribution structure. A line structure 160 , a heat dissipation pad 171 , an upper protective insulating layer 211 , a conductive connection pattern 213 , a gapping insulating layer 220 , and a third vertical connection conductor 230 may be included.

The upper protective insulating layer 211 may cover the first surface 111U of the dielectric layer 111 and the active antenna pattern 113 . The upper protective insulating layer 211 may be formed of an insulating polymer, epoxy, or a combination thereof. In example embodiments, the upper protective insulating layer 211 may be formed of a material different from a material constituting the dielectric layer 111 . In example embodiments, the dielectric constant of the upper protective insulating layer 211 may be different from that of the dielectric layer 111 .

The conductive connection pattern 213 may electrically connect the active antenna pattern 113 and the third vertical connection conductor 230 . The conductive connection pattern 213 may include a pad portion extending along the upper surface of the upper protective insulating layer 211 and a via structure penetrating the upper protective insulating layer 211 .

The gapping insulating layer 220 may be provided on the upper protective insulating layer 211 . The gapping insulating layer may be formed of an insulating polymer, epoxy, or a combination thereof. In example embodiments, the gapping insulating layer 220 may be formed of an epoxy molding compound. In example embodiments, the gapping insulating layer 220 may be formed of a material different from a material constituting the dielectric layer 111 . In example embodiments, the dielectric constant of the gapping insulating layer 220 may be different from that of the dielectric layer 111 .

The third vertical connection conductor 230 may be provided within the gapping insulating layer 220 . The third vertical connection conductor 230 extends in a substantially vertical direction (eg, Z direction) within the gapping insulation layer 220 and penetrates the gapping insulation layer 220. can The third vertical connection conductor 230 may have a pillar shape extending in a vertical direction (eg, a Z direction) within the gapping insulating layer 220 . The lower surface of the third vertical connection conductor 230 may contact the pad portion of the conductive connection pattern 213, and the upper surface of the third vertical connection conductor 230 may include a plurality of first redistribution insulating layers 121 It may contact the upper pad of the first conductive layer 1631 in the lowermost insulating layer among them. In this specification, the third vertical connection conductor 230 may be referred to as a lower vertical connection conductor, and the first vertical connection conductor 151 and the second vertical connection conductor 153 may be referred to as upper vertical connection conductors. there is.

For example, the third vertical connection conductor 230 is copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au) , palladium (Pd), or a combination thereof.

In example embodiments, the diameter (or horizontal width) of the third vertical connection conductor 230 may be between 20 micrometers and 110 micrometers. In exemplary embodiments, the diameter of the third vertical connection conductor 230 may be between 20 micrometers and 50 micrometers, between 50 micrometers and 80 micrometers, or between 80 micrometers and 110 micrometers.

In example embodiments, the third vertical connection conductor 230 may be a conductive post formed through a plating process and containing copper. When the third vertical connection conductor 230 is the conductive post, the third vertical connection conductor 230 may have a diameter of 50 micrometers or more.

In example embodiments, the third vertical connection conductor 230 may include a conductive wire formed through a bonding wire process. When the third vertical connection conductor 230 is a conductive wire, the diameter of the third vertical connection conductor 230 may be between 20 micrometers and 50 micrometers.

For example, when forming the third vertical connection conductor 230 with a conductive wire, forming a conductive wire extending from the pad portion of the conductive connection pattern 213 through a bonding wire process; A step of forming an insulating material constituting the covering insulating layer 220, a polishing step of removing a portion of the insulating material to expose the conductive wire, and a first redistribution structure on the gapping insulating layer 220 ( 120) may be performed sequentially.

In example embodiments, the horizontal width of the upper pad of the first conductive layer 1231 attached to the upper end of the third vertical connection conductor 230 is equal to that attached to the lower end of the third vertical connection conductor 230. It may be greater than or equal to the horizontal width of the pad portion of the first conductive connection pattern 213 . For example, the horizontal width of the upper pad of the first conductive layer 1231 may be 1 to 10 times or 3 to 10 times the horizontal width of the pad portion of the first conductive connection pattern 213 . When the third vertical connection conductor 230 is formed of a conductive wire, the conductive wire is shifted from a predetermined target position during the forming process of the gapping insulation layer 220, and the conductive wire is shifted to the first A problem of not being able to contact the conductive layer 1231 may occur. In the present embodiments, by forming the horizontal width of the upper pad of the first conductive layer 1231 to be greater than or equal to the horizontal width of the pad portion of the first conductive connection pattern 213, the third vertical connection conductive implemented with a conductive wire. Reliability of electrical connection between the body 230 and the upper pad of the first conductive layer 1231 may be improved.

In exemplary embodiments, the third vertical connection conductor 230 is similar to the first vertical connection conductor 151 and/or the second vertical connection conductor 153 described with reference to FIG. A pillar-shaped core conductor penetrating the insulating layer 220 and a barrier conductive layer covering an outer surface of the core conductor may be included. Similar to the first vertically connected conductor 151 and/or the second vertically connected conductor 153 described with reference to FIG. 5, the core conductor of the third vertically connected conductor 230 is the third vertically connected conductor. A material having higher electrical conductivity than the barrier conductive layer of the conductor 230 may be included. For example, the core conductor of the third vertical connection conductor 230 may be formed of copper, and the barrier conductive layer of the third vertical connection conductor 230 may be formed of palladium.

The semiconductor chip 130 activates the antenna structure 110 through the third vertical connection conductor 230, the first conductive connection structure 123 of the first redistribution structure 120, and the chip connection bump 141. It may be electrically connected to the antenna pattern 113 .

In exemplary embodiments, the active antenna pattern 113 of the antenna structure 110 includes a first active antenna pattern configured to radiate or receive a radio signal in a first wavelength band and a second wavelength band different from the first wavelength band. It may include a second active antenna pattern configured to radiate or receive a radio signal of. The first active antenna pattern and the second active antenna pattern may be electrically connected to the semiconductor chip 130 through different electrical connection paths. The at least one first active antenna pattern and the at least one second active antenna pattern may have different shapes and/or different dimensions (eg, different horizontal widths).

In example embodiments, the first redistribution structure 120 may include an antenna ground layer 181a. The antenna ground layer 181a may have a plane or flat plate shape extending along the surface of any one of the plurality of first redistribution insulating layers 121 . The antenna ground layer 181a may be disposed on any one of upper and lower surfaces of each of the plurality of first redistribution insulating layers 121 . The antenna ground layer 181a may be formed together through a metal wiring process for forming the first conductive layers 1231, and may be positioned at the same vertical level as any one of the first conductive layers 1231. can The antenna ground layer 181a may include the same material as the first conductive layer 1231 . For example, the antenna ground layer 181a extends along an upper surface of any one of the plurality of first redistribution insulating layers 121 and includes two first conductive layers 1231 spaced apart from each other in a vertical direction. ) can be located between.

The antenna ground layer 181a is substantially parallel to each of the active antenna patterns 113, and capacitance may be formed between the antenna ground layer 181a and the active antenna patterns 113. For example, from a plan view, the area where the antenna ground layer 181a is disposed may be larger than the area where the active antenna patterns 113 are disposed. In other words, from a plan view, an area including all of the active antenna patterns 113 may be within an area including the antenna ground layer 181a.

The antenna ground layer 181a may be electrically grounded. In exemplary embodiments, the antenna ground layer 181a includes an external connection terminal 191 to which a ground signal (or ground voltage) provided from the outside is applied, a second vertical connection conductor 153, and a first conductive layer 1231. ), and a ground signal may be applied through the first conductive via pattern 1233.

In exemplary embodiments, a vertical distance (VDa) between the antenna ground layer 181a and the active antenna pattern 113 may be between 200 micrometers and 500 micrometers, or between 300 micrometers and 400 micrometers. The thickness of the gapping insulation layer 220 may be adjusted so that the vertical distance VDa between the antenna ground layer 181a and the active antenna pattern 113 has a required value. In example embodiments, the thickness of the gapping insulation layer 220 may be between 50% and 95% of a vertical distance VDa between the antenna ground layer 181a and the active antenna pattern 113 .

9A to 9D are cross-sectional views illustrating a method of manufacturing the semiconductor package 14 shown in FIG. 8 . Hereinafter, a method of manufacturing the semiconductor package 14 illustrated in FIG. 8 will be described with reference to FIGS. 9A to 9D , and descriptions overlapping with those described above will be omitted or simplified.

Referring to FIG. 9A , an antenna structure 110 is prepared, and an upper protection covering the first surface 111U of the dielectric layer 111 and the active antenna pattern 113 on the first surface 111U of the dielectric layer 111 An insulating layer 211 is formed. After forming the upper protective insulating layer 211, the conductive connection pattern 213 including a pad part extending along the upper surface of the upper protective insulating layer 211 and a via structure filling the via hole of the upper protective insulating layer 211 form The conductive connection pattern 213 may be formed through a metal wiring process.

Referring to FIG. 9B , after forming the conductive connection pattern 213 , a third vertical connection conductor 230 and a gapping insulating layer 220 are formed on the upper surface of the upper protective insulating layer 211 . For example, after forming the third vertical connection conductor 230, an insulating material covering the upper protective insulating layer 211 and the third vertical connection conductor 230 is formed, and the third vertical connection conductor ( 230) may perform a polishing process to remove a portion of the insulating material until it is exposed. Another part of the insulating material remaining after the polishing process may constitute the gapping insulating layer 220 . The polishing process may include a planarization process such as chemical mechanical polishing, and through the polishing process, a portion of the insulating material and a portion of each of the third vertical connection conductors 230 may be removed. The top surface of the gapping insulating layer 220 and the top surfaces of the third vertical connection conductors 230 obtained through the polishing process may be planarized surfaces, and the top surface of the gapping insulation layer 220 and the third vertical connection conductor The top surfaces of s 230 may be coplanar.

Referring to FIG. 9C , after forming the third vertical connection conductor 230 and the gapping insulating layer 220 , the first redistribution structure 120 is formed on the upper surface of the gapping insulating layer 220 . After forming the first redistribution structure 120 , the semiconductor chip 130 and the passive component 145 are mounted on the first redistribution structure 120 .

Referring to FIG. 9D , after the semiconductor chip 130 and the passive component 145 are mounted on the first redistribution structure 120, the first redistribution is performed through a method similar to that described above with reference to FIG. 2D. Vertical connection conductors 150 and a molding layer 143 are formed on the structure 120 .

Referring to FIG. 8 , after forming the vertical connection conductors 150 and the molding layer 143, a second redistribution structure 160 is formed on the upper surface of the semiconductor chip 130 and the upper surface of the molding layer 143. can form After forming the second redistribution structure 160 , an external connection terminal 191 may be formed on the second redistribution structure 160 .

As above, exemplary embodiments have been disclosed in the drawings and specifications. Embodiments have been described using specific terms in this specification, but they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

10: semiconductor package 110: antenna structure
120: first redistribution structure 130: semiconductor chip
143: molding layer 150: vertical connection conductor
160: second redistribution structure 171: heat radiation pad
191: external connection terminal

Claims (11)

an antenna structure comprising a dielectric layer and an active antenna pattern on a first side of the dielectric layer;
a gapping insulating layer provided on the first side of the dielectric layer;
a lower vertical connection conductor passing through the gapping insulating layer and electrically connected to the active antenna pattern;
a first redistribution structure provided on the gapping insulation layer and including a first conductive layer electrically connected to the active antenna pattern through the lower vertical connection conductor and an antenna ground layer electrically grounded;
a semiconductor chip mounted on the first redistribution structure and electrically connected to the active antenna pattern through the first conductive layer and the lower vertical connection conductor;
a molding layer provided on the first redistribution structure and surrounding side surfaces of the semiconductor chip;
upper vertical connection conductors spaced apart from the semiconductor chip in a lateral direction and penetrating the molding layer; and
a second redistribution structure provided on the molding layer and the semiconductor chip and including a second conductive layer connected to the upper vertical connection conductors;
A semiconductor package comprising a. According to claim 1,
A distance between the active antenna pattern and the antenna ground layer is between 200 micrometers and 500 micrometers. According to claim 1,
The upper vertical connection conductors,
first upper vertical connection conductors for signal transmission configured to transmit a signal input to the semiconductor chip or a signal output from the semiconductor chip; and
second upper vertical connection conductors electrically grounded and configured to shield electromagnetic interference to the semiconductor chip;
A semiconductor package comprising a. According to claim 3,
A horizontal distance between the second upper vertical connection conductors is smaller than a horizontal distance between the first upper vertical connection conductors. According to claim 3,
Further comprising a passive component mounted on the first redistribution structure,
The second upper vertical connection conductors are arranged to surround the semiconductor chip in a plan view,
The second upper vertical connection conductors are disposed between the semiconductor chip and the passive component. According to claim 1,
The semiconductor package further includes a heat dissipation pad at least partially covering one surface of the semiconductor chip. According to claim 6,
an external heat dissipation terminal provided on the first region of the second redistribution structure and connected to the heat dissipation pad through a heat dissipation conductive layer and a heat dissipation via pattern provided in the second redistribution structure; and
an external connection terminal provided on a second region of the second redistribution structure surrounding the first region of the second redistribution structure in plan view and connected to the second conductive layer;
A semiconductor package further comprising a. According to claim 1,
The antenna structure further includes a parasitic antenna pattern provided on a second surface of the dielectric layer opposite to the first surface. According to claim 1,
The thickness of the dielectric layer is between 100 micrometers and 300 micrometers semiconductor package. According to claim 1,
The first redistribution structure includes a redistribution insulating layer provided on the gapping insulating layer;
The redistribution insulation layer is a semiconductor package including a material different from the dielectric layer. According to claim 1,
The active antenna pattern,
a first active antenna pattern configured to radiate or receive radio signals in a first wavelength band; and
a second active antenna pattern configured to radiate or receive radio signals of a second wavelength band different from the first wavelength band;
A semiconductor package comprising a.

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