KR20190064082A - Gate driver - Google Patents

Abstract

The present invention relates to a gate driving circuit capable of repairing a fault using a carry signal outputted from a carry signal output unit of another stage even if a fault occurs in a carry signal output unit of an arbitrary stage. The gate driving circuit includes a plurality of stages dependently connected to each other and individually having a carry signal output unit and a scan signal output unit to output carry and scan signals. The carry signals outputted from odd-numbered (or even-numbered) stages set two rear end stages and reset the two front end stages.

Description

Gate driver circuit {Gate driver}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit of a display device, and more particularly, to a gate driving circuit capable of repairing a defect in a carry output portion.

As an information-oriented society develops and various portable electronic devices such as a mobile communication terminal and a notebook computer develop, a demand for a flat panel display device that can be applied to the portable electronic device is gradually increasing.

As such a flat panel display device, an OLED display device using a liquid crystal display (LCD) and an organic light emitting diode (OLED) is used.

Such display devices include a display panel having a plurality of gate lines and a plurality of data lines for displaying an image, and a driving circuit for driving the display panel.

The driving circuit includes a gate driving circuit for driving the plurality of gate lines, a data driving circuit for driving the plurality of data lines, a timing controller for supplying timing data to the gate driving circuit and the data driving circuit, Controller and the like.

The display panel is defined as a non-active area (NA) that is a peripheral area of the display area AA and a display area (AA) that provides an image to the user.

A gate driving circuit and a data driving circuit are provided outside the non-display region or the display panel to provide a scan pulse and a data signal for driving each pixel of the plurality of gate lines and the plurality of data lines of the display panel Respectively.

The gate driving circuit may be constituted by at least one gate drive IC, but it is preferable that in the process of forming the sub-pixel and the plurality of signal lines (gate lines and data lines) of the display panel, Can be formed simultaneously on the region NA. As a result, the gate driving circuit is included in the display panel. This is called a gate-in-panel (GIP).

The gate driving circuit includes a plurality of stages that are equal to or greater than the number of gate lines in order to sequentially supply scan pulses to the gate lines.

That is, when the number of gate lines is n, n or more stages are provided.

2 is a block diagram of a conventional n-th stage, FIG. 3 is a circuit diagram of the output section 20 of FIG. 2, and FIG. 4 is a circuit diagram of a conventional gate driving circuit. Is a waveform diagram of the carry signals C (n-3) to C (n + 3) and the first node Q of the conventional (n-3) th to (n + 3)

As shown in Fig. 1, a conventional gate driving circuit includes a plurality of stages ((n-3) th stages to (n + 3) th stages which are connected in a dependent manner) And an output unit for sequentially generating the scan signal SCOUT and the carry signal C according to the applied clock signals SCCLKs and CRCLKs.

Specifically, the gate driving circuit receives a plurality of clock signals (SCCLKs, CRCLKs), a gate high voltage (VGH), a plurality of gate low voltages (VGLs), and a gate start pulse (VST) from the timing controller.

The plurality of clock signals SCCLKs and CRCLKs include a scan pulse output clock signal SCCLKs and a carry pulse output clock signal CRCLKs.

The scan signal SCOUT output from each stage is for sequentially driving the corresponding gate line. The carry signal C output from each stage may be reset by resetting the previous stage, Is a signal for setting.

Therefore, the nth stage ((n) th stage) is controlled by the carry signal C (n-3) output from the front stage ((n-3) th stage) or the start signal VST And reset by the carry signal C (n + 3) output from the succeeding stage ((n + 3) th stage) or the reset signal RST output from the timing control section to generate the carry signal C And a scan signal SCOUT (n).

As shown in Fig. 2, each of the above stages is set by a carry signal C output from the front stage and is reset by a carry signal C output from the rear stage to output to the first and second nodes A plurality of scan pulse output clock signals (SCCLKs) and a plurality of carry pulse output clock signals (CRCLKs); a plurality of scan pulse output clock signals And outputs the scan signal SCOUT (n) and the carry signal C (n) according to a voltage level of the first and second nodes Q and Qb, (20).

As shown in Fig. 3, the output unit 20 includes a carry signal output unit 21 and a scan signal output unit 22. [

The carry signal output unit 21 receives the carry signal output clock signal CRCLK (n) and the first gate low voltage signal group VGL1 (n), to which a carry pulse output clock signal of a plurality of carry clock signals CRCLKs is applied, A first pull-up transistor Tpc and a first pull-down transistor Tdc which are connected in series between the first pull-up transistor Tpc and the second pull-down transistor Tdc.

The first pull-up transistor Tpc is turned on / off according to the voltage level of the first node Q and the first pull-down transistor Tdc is turned on / off according to the voltage level of the second node Qb. And outputs the carry signal C (n).

The scan signal output section 22 includes a scan pulse output clock signal SCCLK (n) to which one scan pulse output clock signal of the plurality of scan pulse output clock signals SCCLKs is applied, and a second gate low voltage terminal A second pull-up transistor Td1 and a second pull-down transistor Td1 connected in series between the gate of the second pull-up transistor Tp1 and the source electrode VGL2 of the first pull- And a capacitor C1.

The second pull-up transistor Tp1 is turned on / off according to a voltage level of the first node Q and the second pull-down transistor Td1 is turned on / off according to a voltage level of the second node Qb. And outputs the scan signal SCOUT (n).

Here, the first pull-up transistor Tpc and the second pull-up transistor Tp1 of the carry signal output unit 21 and the scan signal output unit 22 have the weakest structure.

Therefore, the voltage waveforms of the first node Q of the (n) th and (n + 1) th stages are as shown in Fig.

That is, as described above, the (n) th stage ((n) th stage) is set by the carry signal C (n-3) output from the third front stage Th stage is reset by the carry signal C (n + 3) output from the third stage rear stage ((n + 3) th stage), the first node Q of the (n) (n-3), and becomes the gate low voltage VGH in synchronization with the carry signal C (n + 3). Then, it is boosted by the carry pulse output clock signal CRCLK (n) applied to the (n) th stage ((n) th stage) to become a high voltage (2VGH) state higher than the gate high voltage VGH .

Thus, in the state where the first node Q is bootstrapped, the carry pulse output clock signal CRCLK (n) is output as the carry signal C (n).

Similarly, the first node Q of the (n + 1) -stage becomes the gate high voltage (VGH) in synchronization with the carry signal C (n-2) ) To be in the gate-low voltage (VGL) state. Then, the carry pulse output clock signal CRCLK (n + 1) applied to the (n + 1) th stage ((n + 1) th stage) is boosted to a high voltage (2VGH) state.

Thus, the carry pulse output clock signal CRCLK (n + 1) is output as the carry signal C (n + 1) in the state where the first node Q is bootstrapped.

Thus, in the conventional gate driving circuit, since the plurality of stages are connected in a dependent manner, each stage is set by the carry signal outputted from the front stage, and is reset by the carry signal output from the rear stage, If a failure occurs in the first pull-up transistor Tpc of the signal output unit, signal transmission for setting and resetting each stage can not be performed, and the display panel is not driven.

SUMMARY OF THE INVENTION The present invention provides a gate driving circuit capable of repairing a carry signal output from a carry signal output unit of another stage while using a carry signal output from a carry signal output unit of another stage It has its purpose.

According to an aspect of the present invention, there is provided a gate driving circuit including a plurality of stages, each of which has a carry signal output unit and a scan signal output unit and outputs a carry signal and a scan signal, The carry signal output from the second (or even) stage is characterized by setting two rear stage stages and resetting the two front stage stages.

Here, the carry signal output from the even (or odd) stage is not used to set or reset another stage.

And the output terminal of the carry signal output section of the even (or odd) stage is superimposed on the output terminal of the carry signal output section of the odd (or even) stage.

(Or odd-numbered) stage and the odd-numbered (or odd-numbered) stage when the carry signal is not output from the carry signal output unit of the odd-numbered Or the output terminal of the carry signal output unit of the even-numbered stage is electrically connected and repaired.

the carry signal output from the carry signal output unit of the (n) -th stage sets the (n + 2) -th stage and the (n + 3) Is reset.

And the carry signal output unit and the scan signal output unit of each stage are driven by a clock signal of the same phase having the same phase.

The scan signal output unit of each stage is driven by a k-phase scan pulse output clock signal sequentially shifted by a 1 / 2H section, and the carry signal output unit of each stage is shifted so as not to overlap with each other, And is driven by an output clock signal.

And the same clock signal among the clock signals for carry-pulse output on the k / 2 phase is applied to two adjacent stages.

The gate driving circuit according to the present invention having the above-described features has the following effects.

That is, the carry signal output from the odd-numbered (or even-numbered) stage sets two rear-stage stages and resets two front-stage stages, and the carry signal output from the even- And the output stage of the carry signal output section of the even (or odd) stage is configured to overlap the output stage of the carry signal output section of the odd (or even) stage. Therefore, if the carry signal is not output in the odd (or even) stage, the output terminal of the carry signal output unit of the even (or odd) stage and the odd (or even) The output terminal of the carry signal output section of the stage can be electrically connected, so that the repair can be performed.

1 is a block diagram of a conventional gate driving circuit
2 is a block diagram of a conventional n-th stage
Fig. 3 is a circuit diagram of the output section 20 of Fig. 2
Fig. 4 is a diagram showing waveforms of the carry signals C (n-3) to C (n + 3) and the first node Q of the conventional (n-3)
5 is a schematic view showing a flat display device according to the present invention
6 is a block diagram of a gate driving circuit according to an embodiment of the present invention
7 is a block diagram of a gate driving circuit for explaining a repair method according to an embodiment of the present invention.
FIG. 8 is a timing chart of the scan signal SCOUT (SCLK1 to SCCLK6), the scan signals SCOUT (n-3) to SCOUT (n + 4) To Q (n + 1)
9 is a timing chart of the carry signal C (n-3) to C (n + 4) and the Q signal Q (n) of the clock signals (CRCLK1 to CRCLK6) for carry pulse output of the gate driving circuit according to the first embodiment of the present invention, n) to Q (n + 1)
Fig. 10 is a timing chart of the carry signal C (n-3) to C (n + 4) and the Q node Q (n) of the clock signal (CRCLK1 to CRCLK3) n) to Q (n + 1)

Hereinafter, a gate driving circuit and a flat panel display device having the same according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a configuration diagram briefly showing a flat panel display device according to the present invention.

The flat panel display device according to the present invention comprises a display panel 1, a gate driving circuit 2, a data driving circuit 3 and a timing controller 4 as shown in Fig.

The display panel 1 is provided with a plurality of gate lines GL and a plurality of data lines DL and a plurality of gate lines GL and a plurality of data lines DL in a crossing region of the plurality of gate lines GL and the plurality of data lines DL. A plurality of sub-pixels P are arranged in a matrix form. The plurality of subpixels P are arranged to receive an image corresponding to a video signal (data voltage) supplied from the plurality of data lines DL in response to a scan pulse G supplied from the gate lines GL Display.

When the display panel 1 is a display panel (liquid crystal display panel) of a liquid crystal display, the liquid crystal display panel includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, And a liquid crystal layer filled between the thin film transistor array substrate and the color filter array substrate.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, And one sub pixel region (Pixel P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub pixel region (P).

In the liquid crystal display panel thus constructed, a voltage is applied to an electric field generating electrode (pixel electrode and common electrode) to generate an electric field in the liquid crystal layer, and the arrangement state of the liquid crystal molecules in the liquid crystal layer is adjusted by the electric field, The image is displayed by controlling the polarization.

In addition, when the display panel 1 is an OLED display panel of an OLED display device, the OLED display panel has sub-pixels defined by the plurality of gate lines and a plurality of data lines intersecting with each other, And an organic light emitting layer between the cathode and the anode and the cathode, and a pixel circuit for independently driving the OLED.

The pixel circuit may be variously configured, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to control the amount of light emitted from the OLED.

The display panel 1 is defined as an active area AA for providing an image to a user and a non-active area NA for surrounding the display area AA.

 The gate driving circuit 2 is a GIP (gate in panel) type gate driver and is disposed in a non-display area of the display panel 1. [

The gate driving circuit 2 sequentially supplies a scan signal (gate driving signal, SCOUT) to each gate line GL in accordance with a plurality of gate control signals GCS provided from the timing controller 4, And a shift register.

The plurality of gate control signals GCS includes a plurality of clock signals CLK1-6 having different phases, a gate start signal VST indicating the start of driving of the gate driving circuit 2, a reset signal RST ), A gate high voltage (VGH), and gate low voltages (VGL1, VGL2).

The data driving circuit 3 converts the digital image data RGB input from the timing controller 4 into an analog data voltage using a reference gamma voltage and outputs the converted analog data voltage to the plurality of data lines DL. The data driving circuit 3 is controlled in accordance with a plurality of data control signals DCS provided from the timing controller 4. [

The timing controller 4 arranges image data RGB input from the outside in accordance with the size and resolution of the display panel 1 and supplies the image data RGB to the data driving circuit 3. The timing controller 4 receives the synchronization signals SYNC input from the outside such as a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, A plurality of gate control signals GCS and a plurality of data control signals DCS are generated and supplied to the gate driving circuit 2 and the data driving circuit 3, respectively.

The gate driving circuit 2 includes a plurality of stages for sequentially supplying a scan signal (gate driving signal, SCOUT (n)) to each of the plurality of gate lines GL.

Each stage of the gate drive circuit 2 according to the present invention outputs a scan signal to each gate line in the same manner as a conventional gate drive circuit but outputs a carry signal differently from a conventional gate drive circuit.

That is, the carry signals output from the odd-numbered (or even-numbered) stages set two rear-stage stages, reset the two front-stage stages, and the carry signals output from the even- Or does not reset the front stage.

6 is a block diagram of a gate driving circuit according to the present invention.

As shown in Fig. 6, the gate drive circuit according to the present invention includes a plurality of stages ((n-3) th stages to (n + 3) th stages that are connected in a dependent manner). One stage includes an output section that sequentially generates the scan signal SCOUT and the carry signal C in accordance with the clock signals SCCLKs and CRCLKs applied from the timing controller.

Specifically, the gate driving circuit receives a plurality of clock signals (SCCLKs, CRCLKs), a gate high voltage (VGH), a plurality of gate low voltages (VGLs), and a gate start pulse (VST) from the timing controller.

The plurality of clock signals SCCLKs and CRCLKs include a scan pulse output clock signal SCCLKs and a carry pulse output clock signal CRCLKs.

The stages ((n-3) th stage to (n + 3) th stage) output scan signals SCOUT (n-3) to SCOUT (n + 3) for driving the corresponding gate line.

However, each of the stages ((n-3) th stage to (n + 3) th stage) may be reset by resetting the front stage or by shifting the carry signal C (N-3) th stages to (n + 3) th stages) reset the front stage, or the next stage Do not set.

(N + 1) th stage, (n + 1) th stage, (n + 3) th stage, (N + 1), C (n + 3), ...) may be reset by resetting the front stage, Th stage, (n-1) th stage, (n + 1) th stage, (n-1) th stage, (n + 1), C (n + 1), C (n + 3), ...) It is not connected to the rear stage.

(N + 1) th stage, (n + 3) th stage, ...) of the odd-numbered (or even) (..., C (n-3), C (n-1), C (n + 1), C (n + 3), ... overlap the carry signal output terminals of the front stage and the rear stage.

On the other hand, the carry signals (..., (C (n-2) th stage, ..., (n-2) th stage, (n) th stage, 2), C (n), C (n + 2), ...) resets the two front stage stages and sets two rear stage stages. In other words, ..., C (n-2), C (n), C (n) th stages of ..., (n-2) th stage, (n) th stage, (n + 2), ...) are connected to two front stage and two rear stage.

That is, the carry signal C (n-2) of the (n-2) th stage ((n-2) th stage) (n-6) th stage and (n-5) th stage ((n-5) th stage) .

the carry signal C (n) of the (n) th stage ((n) th stage) is supplied to the (n + 2) th stage 3) th stage, and resets the (n-4) th stage ((n-4) th stage) and the (n-3) th stage

the carry signal C (n + 2) of the (n + 2) th stage ((n + 2) th stage) (N-2) th stage and the (n-1) th stage ((n-1) th stage) Set.

th stage and the (n + 7) th stage of the (n + 4) th stage ((n + (N) th stage and the (n + 1) th stage ((n-1) th stage) are reset.

In the gate driver circuit according to the present invention, the structure of each stage is as shown in Figs. 2 and 3 described in the above-mentioned prior art.

2, each stage is set by the carry signal C output from the front stage and is reset by the carry signal C output from the rear stage so that the first and second nodes One of a scan pulse output clock signal and a plurality of carry pulse output clock signals (CRCLKs) among the plurality of scan pulse output clock signals (SCCLKs); a node controller (10) And outputs the scan signal SCOUT (n) and the carry signal C (n) according to a voltage level of the first and second nodes Q and Qb, (20).

As shown in Fig. 3, the output unit 20 includes a carry signal output unit 21 and a scan signal output unit 22. [

The carry signal output unit 21 receives the carry signal output clock signal CRCLK (n) and the first gate low voltage signal group VGL1 (n), to which a carry pulse output clock signal of a plurality of carry clock signals CRCLKs is applied, A first pull-up transistor Tpc and a first pull-down transistor Tdc which are connected in series between the first pull-up transistor Tpc and the second pull-down transistor Tdc.

The first pull-up transistor Tpc is turned on / off according to the voltage level of the first node Q and the first pull-down transistor Tdc is turned on / off according to the voltage level of the second node Qb. And outputs the carry signal C (n).

The scan signal output section 22 includes a scan pulse output clock signal SCCLK (n) to which one scan pulse output clock signal of the plurality of scan pulse output clock signals SCCLKs is applied, and a second gate low voltage terminal A second pull-up transistor Td1 and a second pull-down transistor Td1 connected in series between the gate of the second pull-up transistor Tp1 and the source electrode VGL2 of the first pull- And a capacitor C1.

The second pull-up transistor Tp1 is turned on / off according to a voltage level of the first node Q and the second pull-down transistor Td1 is turned on / off according to a voltage level of the second node Qb. And outputs the scan signal SCOUT (n).

The repair method in the gate driving circuit according to the present invention will be described as follows.

7 is a block diagram of a gate driving circuit for explaining a repair method according to an embodiment of the present invention.

7 illustrates a case in which a carry signal C (n) is not output due to a defect in the carry signal output portion (refer to 21 in Fig. 3) of the (n) th stage ((n) th stage).

(N + 2) th stages and (n + 2) th stages and (n + 2) th stages are not output in the (n) th stage Th stage ((n-3) th stage) and (n-3) th stage Is not reset, the gate driving circuit is not operated.

If the carry signal C (n) is not outputted at the (n) -th stage (n) th stage and the gate driving circuit is not operated, as shown by the arrow in FIG. 7, (n + 1) th stage of the carry signal output stage of the (n + 1) th stage ((n) th stage) is overlapped with the carry signal output stage of the Th stage and the carry signal output terminal of the (n + 1) th stage ((n + 1) th stage).

Then, the carry signal output terminal of the (n) th stage (n) th stage and the (n) th stage (n) th stage are disconnected.

Therefore, the (n + 2) th stage (n + 2) th stage and the (n + 3) th stage th stage and the (n-3) th stage (n-1) th stage and the carry signal C (n + 1) Th stage is reset by the carry signal C (n + 1) output from the (n + 1) th stage ((n + 1) th stage).

(N + 2) th stages and (n + 2) th stages, even if the carry signal C (n) is not output at the (n) th stage Th stage is set by the carry signal C (n + 1) output from the (n + 1) th stage ((n + 1) th stage) Th stage and the (n-3) th stage (n-3) th stage and the (n-3) the carry signal C (n + 1) outputted from the stage C (n + 1) is reset, so that the gate drive circuit is driven.

Hereinafter, the operation of the gate driving circuit according to the present invention will be described.

FIG. 8 is a timing chart of the scan signal SCOUT (SCLK1 to SCCLK6), the scan signals SCOUT (n-3) to SCOUT (n + 4) FIG. 9 is a timing chart of the carry pulse output clock signals CRCLK1 to CRCLK6 and the carry signal C (n-3) of the gate driving circuit according to the first embodiment of the present invention, (N + 4) and Q nodes Q (n) to Q (n + 1).

As shown in Figs. 8 and 9, the scan pulse output clock signals SCCLK1 to SCCLK6 are sequentially shifted clock signals superimposed on the 1 / 2H section (1/2 horizontal section).

Likewise, the carry pulse output clock signals CRCLK1 to CRCLK6 are also sequentially shifted clock signals superimposed on the 1 / 2H section (1/2 horizontal section).

The scan pulse output clock signals SCCLK1 to SCCLK6 and the carry pulse output clock signals CRCLK1 to CRCLK6 have the same phase with each other.

That is, the scan pulse output clock signal SCCLK1 and the carry pulse output clock signal CRCLK1 have the same phase, the scan pulse output clock signal SCCLK2 and the carry pulse output clock signal CRCLK2 have the same phase, The output clock signal SCCLK3 and the carry pulse output clock signal CRCLK3 have the same phase and the scan pulse output clock signal SCCLK4 and the carry pulse output clock signal CRCLK4 have the same phase and the scan pulse output clock signal SCCLK5 and the carry pulse output clock signal CRCLK5 have the same phase and the scan pulse output clock signal SCCLK6 and the carry pulse output clock signal CRCLK6 have the same phase.

The first scan pulse output clock signal SCCLK1 and the first carry pulse output clock signal CRCLK1 are input to the (n-3) th stage ((n-3) th stage and th stage and the second carry pulse output clock signal SCCLK2 and the second carry pulse output clock signal CRCLK2 are applied to the (n-2) th stage ((n-2) th stage) th stage ((n + 4) th stage), the third scan pulse output clock signal SCCLK3 and the third carry pulse output clock signal CRCLK3 are applied to the (n-1) (n-1) th stage.

The fourth scan pulse output clock signal SCCLK4 and the fourth carry pulse output clock signal CRCLK4 are applied to the (n) th stage ((n2) th stage), the fifth scan pulse output clock signal SCCLK5, The fifth carry pulse output clock signal CRCLK5 is applied to the (n + 1) th stage ((n + 1) th stage) and the sixth scan pulse output clock signal SCCLK6 and the sixth carry pulse output clock signal CRCLK6 ) Is applied to the (n + 2)) th stage ((n + 2) th stage).

The (n) th stage and (n + 1) th stage ((n + 1) th stages) (N + 4) th stage of the (n + 4) th stage and the carry signal C (n + 2) Is reset.

Therefore, the first node Q of the (n) th stage ((n) th stage) and (n + 1) th stage ((n + 1) th stage) th stage ((n + 4) th stage) in synchronism with the carry signal C (n-2) of the (n + And becomes the gate-low voltage (VGL) state in synchronization with the signal C (n + 4).

The first node Q of the (n) th stage (n) th stage is boost-wrapped by the fourth scan pulse output clock signal SCCLK4 and the fourth carry pulse output clock signal CRCLK4 Becomes a high voltage (2VGH) state which is higher than the gate high voltage (VGH). The first node Q of the (n + 1) th stage ((n + 1) th stage) is connected to the fifth scan pulse output clock signal SCCLK5 and the fifth carry pulse output clock signal CRCLK5 And becomes a high voltage (2VGH) state which is higher than the gate high voltage (VGH).

In the state where the first node Q is bootstrapped, the (n) th stage ((n) th stage) outputs the fourth scan pulse output clock signal SCCLK4 and the fourth carry pulse output clock signal Th stage and the (n + 1) th stage are output as the scan signal SCOUT (n) and the carry signal C (n), respectively, And outputs the clock signal SCCLK5 and the fifth carry pulse output clock signal CRCLK5 to the scan signal SCOUT (n + 1) and the carry signal C (n + 1), respectively.

Therefore, the carry signal output ends of all the stages are normally operated, and the carry signal output from the odd (or even) stage sets two rear stage stages, resets two front stage stages, and the even (or odd) The carry signal outputted from the stage normally outputs the scan signal and the carry signal to sequentially drive the gate lines of the display panel without resetting the rear stage or resetting the front stage.

7, the carry signal output from the carry signal output terminal of the (n) th stage is not output, and the carry signal output from the (n + 1) th stage (N + 2) th stage and (n + 3) th stage ((n + 3) th stage) Th stage ((n + 4) th stage) and (n + 1) th stage output from the carry signal C Th stage is reset by the carry signal C (n + 1) output from the (n + 1) th stage ((n + 1) th stage) There is no problem in driving the display panel.

10 is a timing chart showing the operation of the gate drive circuit according to the second embodiment of the present invention in which the carry pulse output clock signals CRCLK1 to CRCLK3, the carry signals C (n-3) to C (n + 4) Q (n) to Q (n + 1)).

8, the first scan pulse output clock signal SCCLK1 is supplied to the scan signal output stage 22 and the (n + 3) th stage ((n-3) th stage (n-2) th stage of the (n-2) th stage, and the second scan pulse output clock signal SCCLK2 is applied to the scan signal output terminal 22 of the Th stage (22) and the (n + 4) th stage ((n + 4) th stage) and the third scan pulse output clock signal (SCCLK3) (n-1) th stage and the fourth scan pulse output clock signal SCCLK4 is applied to the scan signal output stage 22 of the (n) th stage ((n2) th stage) And the fifth scan pulse output clock signal SCCLK5 is applied to the scan signal output stage 22 of the (n + 1) th stage ((n + 1) th stage), and the sixth scan pulse output clock signal SCCLK6 (N + 2) th stage ((n + 2) th stage) Is output to the call (22) to, so that, the scan signals are sequentially output as described in Fig.

On the other hand, as shown in Fig. 10, the carry pulse output clock signals (CRCLK1 to CRCLK3) use a three-phase clock signal shifted so as not to overlap each other.

That is, the scan pulse output clock signals SCCLK1 to SCCLK6 use a 6-phase clock signal as described in FIG. 8 and the carry pulse output clock signals CRCLK1 to CRCLK3 are shifted so as not to overlap each other .

Therefore, the first carry pulse output clock signal CRCLK1 is input to the (n-2) th stage ((n-2) th stage), (n-1) Th stage ((n + 4) th stage) and the second carry pulse output clock signal CRCLK2 is applied to the (n) th stage th stage and the third carry pulse output clock signal CRCLK3 is applied to the (n-4) th stage, the (n-3) th stage, Th stage, the (n + 2) th stage, and the (n + 3) th stage.

Therefore, the (n) th stage (n) th stage and the (n + 1) th stage (n + Is set by the carry signal C (n-2) and is reset by the carry signal C (n + 4) of the (n + 4) th stage ((n + 4) th stage).

Therefore, the first node Q of the (n) th stage ((n) th stage) and the (n + 1) th stage ((n + 4) th stage) in synchronism with the carry signal C (n-2) of the (n + And becomes the gate-low voltage (VGL) state in synchronization with the signal C (n + 4).

The first node Q of the (n) th stage (n) th stage and the (n + 1) th stage (n + 1) th stage receives the second carry pulse output clock signal CRCLK2, (2VGH) state which is higher than the gate high voltage VGH.

(N) th stage and (n + 1) th stage ((n + 1) th stage) in the state where the first node Q is bootstrapped, And outputs the two-carry pulse output clock signal CRCLK2 as the carry signals C (n) and C (n + 1), respectively.

Therefore, the carry signal output ends of all the stages are normally operated, and the carry signal output from the odd (or even) stage sets two rear stage stages, resets two front stage stages, and the even (or odd) The carry signal outputted from the stage normally outputs the scan signal and the carry signal to sequentially drive the gate lines of the display panel without resetting the rear stage or resetting the front stage.

7, the carry signal output from the carry signal output terminal of the (n) th stage is not output, and the carry signal output from the (n + 1) th stage C (n + 1)).

That is, since the carry signal C (n) of the (n) th stage is in phase with the carry signal C (n + 1) of the (n + 1) .

Although Fig. 10 shows a clock pulse for three-phase carry pulse output, it is not limited thereto.

8, the scan pulse output clock signal is an 8-phase clock signal that is sequentially shifted by superimposing in the 1 / 2H section (1/2 horizontal section), and the carry pulse output clock signal is shifted Phase clock signal. And can be applied in various ways as described above.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1: display panel 2: gate driving circuit
3: Data driving circuit 4: Timing controller

Claims (8)

And a plurality of stages connected in a dependent manner and each having a carry signal output unit and a scan signal output unit for outputting a carry signal and a scan signal,
The carry signal output from the odd-numbered (or even-numbered) stage sets two subsequent stages and resets the two preceding stages. The method according to claim 1,
The carry signal output at the even (or odd) stage is not used to set or reset another stage. The method according to claim 1,
And the output terminal of the carry signal output section of the even (or odd) stage is superimposed on the output terminal of the carry signal output section of the odd (or even) stage. The method of claim 3,
(Or odd-numbered) stage and the odd-numbered (or odd-numbered) stage when the carry signal is not output from the carry signal output unit of the odd-numbered Or an even-numbered) stage of the carry signal output section. The method according to claim 1,
the carry signal output from the carry signal output unit of the (n) -th stage sets the (n + 2) -th stage and the (n + 3) A gate driving circuit for resetting the gate driving circuit. The method according to claim 1,
Wherein the carry signal output unit of each stage and the scan signal output unit are driven by a clock signal of the same phase having the same phase. The method according to claim 1,
The scan signal output unit of each stage is driven by a clock pulse for outputting a scan pulse of k phase superimposed on a 1 / 2H section and sequentially shifted,
And a carry signal output unit of each stage is driven by a carry pulse output clock signal of k / 2 phase shifted so as not to overlap with each other. 8. The method of claim 7,
And the same clock signal among the clock signals for carry-pulse output on the k / 2 phase is applied to two adjacent stages.

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