KR102437181B1 - Flat panel display device - Google Patents

Abstract

The present invention relates to a flat panel display device capable of improving a deviation between a clock signal supplied to upper stages of a gate driving circuit and a clock signal supplied to lower stages of a gate driving circuit, comprising: a timing controller outputting a plurality of clock signals; a gate driving circuit having a plurality of stages connected to each other to sequentially output scan signals in accordance with the timing of the plurality of clock signals, and a first clock supplying the plurality of clock signals to the upper stages of the gate driving circuit A signal bus line and a second clock signal bus line for supplying the plurality of clock signals to the lower stages of the gate driving circuit.

Description

Flat panel display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a flat panel display device for improving deviation of a clock signal supplied from a timing controller to a gate driving circuit.

As the information society develops and various portable electronic devices such as mobile communication terminals and notebook computers develop, the demand for a flat panel display device that can be applied thereto is gradually increasing.

As such a flat panel display, a liquid crystal display (LCD) using liquid crystal and an OLED display using an organic light emitting diode (OLED) are used.

Such display devices include a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

The driving circuit includes a gate driving circuit driving the plurality of gate lines, a data driving circuit driving the plurality of data lines, and timing for supplying image data and various control signals to the gate driving circuit and the data driving circuit. controller, etc.

The gate driving circuit as described above is configured to include a plurality of stages equal to or greater than the number of gate lines in order to sequentially supply scan pulses to each gate line.

That is, when the number of gate lines is n, n or more stages are provided.

1 is a block diagram of a conventional gate driving circuit.

As shown in FIG. 1, the conventional gate driving circuit is cascaded through a carry signal line transmitting carry signals CROUT(1) to (CROUT(n)) to generate a clock signal CLK. A plurality of stages ST(1) to ST(n) that sequentially output scan signals SCOUT(1) to SCOUT(n) and carry signals CROUT(1) to (CROUT(n)) according to timing is comprised of

Each stage is enabled or set by the start signal VST or the carry signal output from the previous stage, and is disabled or reset by the carry signal output from the rear stage. do.

The clock signal CLK is composed of a plurality of clock signals having different phases by being shifted by a predetermined time, and supplied from the timing controller to all stages of the gate driving circuit.

That is, the plurality of clock signals having different phases output from the timing controller are transmitted from the first stage constituting the gate driving circuit through one clock signal bus line having signal lines corresponding to the plurality of clock signals. supplied until the last stage.

Accordingly, there is a problem in that the image quality is deteriorated due to a deviation between the scan signal output of the upper stages and the scan signal output of the lower stages due to the load resistance of the clock signal bus line.

In particular, as the display panel 1 has a larger area, the output deviation of the upper stages and the output of the lower stages becomes more severe.

An object of the present invention is to provide a flat panel display capable of improving a deviation between a clock signal supplied to upper stages of a gate driving circuit and a clock signal supplied to lower stages of a gate driving circuit in order to solve the problems as in the prior art. have.

A flat panel display device according to the present invention for achieving the above object is provided with a timing controller for outputting a plurality of clock signals, and a plurality of stages connected to each other and sequentially outputting scan signals in accordance with the timings of the plurality of clock signals. a gate driving circuit comprising: a first clock signal bus line for supplying the plurality of clock signals to the upper stages of the gate driving circuit; It is characterized in that it has a second clock signal bus line.

Here, the first clock signal bus line supplies the plurality of clock signals to the upper stages of the gate driving circuit through a damping resistor.

The sum of the line resistance of the first clock signal bus line and the damping resistance is equal to the line resistance of the second clock signal bus line.

The flat panel display device according to the present invention having the above characteristics has the following effects.

first and second clock signal bus lines, wherein the first clock signal bus line supplies the plurality of clock signals to the upper stages of the gate driving circuit, and the second clock signal bus line drives the gate The plurality of clock signals are supplied to stages at the lower end of the circuit.

Accordingly, a deviation between the clock signal supplied to the upper stages of the gate driving circuit and the clock signal supplied to the lower stages may be improved.

In addition, since the RC load applied to the clock signal bus line is reduced compared to the conventional one, even if the clock signal bus line is added compared to the conventional one, the same bezel size as that of the conventional flat panel display is maintained or the conventional flat panel display Compared to that, the bezel size can be reduced.

1 is a block diagram of a conventional gate driving circuit;
2 is a block diagram schematically illustrating a flat panel display device according to the present invention;
3 is an explanatory diagram of clock signal bus lines for supplying a clock signal between a timing controller and a gate driving circuit of a flat panel display according to the present invention;
4 is a detailed configuration diagram of a clock signal output terminal of a timing controller of a flat panel display according to the first embodiment of the present invention;
5 is a block diagram of a k-th stage according to the present invention;
6 is a circuit diagram of the output unit of FIG. 5
7 is a detailed configuration diagram of a clock signal output terminal of a timing controller of a flat panel display device according to a second embodiment of the present invention;

A flat panel display device according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

2 is a schematic diagram illustrating a flat panel display device according to the present invention.

As shown in FIG. 2 , a flat panel display according to the present invention includes a display panel 1 , a gate driving circuit 2 , a data driving circuit 3 , and a timing controller 4 .

In the display panel 1 , a plurality of gate lines GL and a plurality of data lines DL are disposed, and a plurality of gate lines GL and a plurality of data lines DL are disposed in an intersection region of the display panel 1 . A plurality of sub-pixels P are arranged in a matrix form. The plurality of sub-pixels P display an image according to an image signal (data voltage) supplied from the plurality of data lines DL in response to a scan pulse G supplied from the gate lines GL. indicate

When the display panel 1 is a display panel of a liquid crystal display device, the liquid crystal display panel includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, and a color filter on which a color filter array is formed on the glass substrate. An array substrate and a liquid crystal layer filled between the thin film transistor array substrate and the color filter array substrate are provided.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, and each gate line and one sub-pixel area Pixel (P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub-pixel area P.

The liquid crystal display panel configured as described above applies a voltage to an electric field generating electrode (a pixel electrode and a common electrode) to generate an electric field in the liquid crystal layer, and adjusts an arrangement state of liquid crystal molecules of the liquid crystal layer by the electric field to increase the amount of incident light. Display an image by controlling the polarization.

In addition, when the display panel 1 is an OLED display panel of an OLED display device, in the OLED display panel, a plurality of gate lines and a plurality of data lines intersect to define a sub-pixel, and each sub-pixel is an anode and an OLED including a cathode and an organic light emitting layer between the anode and the cathode, and a pixel circuit independently driving the OLED.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

The display panel 1 is defined as an active area AA that provides an image to a user and a non-active area NA that is a peripheral area of the display area AA.

The gate driving circuit 2 may include at least one gate driving IC, but in the process of forming the plurality of signal lines (gate lines and data lines) and sub-pixels of the display panel 1 , the It may be simultaneously formed on the non-display area NA of the display panel. As a result, the gate driving circuit is included in the display panel. This is called a Gate-In-Panel (hereinafter also referred to as “GIP”). Recently, in the GIP gate driving circuit, the GIP gate driving circuit is constructed using an oxide semiconductor device.

The gate driving circuit 2 sequentially supplies a scan signal (a gate driving signal, SCOUT) to each of the gate lines GL according to a plurality of gate control signals GCS provided from the timing controller 4 . It consists of shift registers.

The plurality of gate control signals GCS include a plurality of clock signals CLK having different phases, a gate start signal VST for instructing the start of driving of the gate driving circuit 2 , a reset signal RST, The gate high voltage VGH and the gate low voltages VGL1 and VGL2 are included.

Here, the plurality of clock signals CLK may include clock signals CRCLKs for outputting a plurality of carry signals and clock signals SCCLKs for outputting a plurality of scan signals.

The data driving circuit 3 converts digital image data RGB input from the timing controller 4 into an analog data voltage using a reference gamma voltage, and converts the converted analog data voltage to the plurality of data lines ( DL). The data driving circuit 3 is controlled according to a plurality of data control signals DCS provided from the timing controller 4 .

The timing controller 4 aligns image data RGB input from the outside according to the size and resolution of the display panel 1 and supplies it to the data driving circuit 3 . In addition, the timing controller 4 may include synchronization signals SYNC input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. is used to generate a plurality of gate control signals GCS and a plurality of data control signals DCS and respectively supply them to the gate driving circuit 2 and the data driving circuit 3 .

The gate driving circuit 2 includes a plurality of stages to sequentially supply scan signals (gate driving signals, SCOUT(1) to SCOUT(n)) to each of the plurality of gate lines GL. do.

3 is an explanatory diagram of clock signal bus lines for supplying a clock signal between the timing controller 4 and the gate driving circuit 2 of the flat panel display according to the present invention.

As shown in FIG. 3 , the gate driving circuit 2 of the flat panel display according to the present invention is dependently connected ( A plurality of stages ST that are cascade connected and sequentially output scan signals SCOUT(1) to SCOUT(n) and carry signals CROUT(1) to (CROUT(n)) in accordance with the timing of the clock signal CLK (1) to ST(n)) are included.

Each stage is enabled or set by the start signal VST or the carry signal output from the previous stage, and is disabled or reset by the carry signal output from the rear stage. do.

In FIG. 3, for convenience of explanation, the k (k is a natural number)-th stage is enabled or set by the start signal VST or the carry signal output from the previous stage (k-1) stage, and , which is disabled or reset by the carry signal output from the subsequent (k+1) stage, but is not limited thereto.

That is, the k-th stage is enabled or set by the carry signal output from the (k-2, k-3 or k-4)-th stage, and (k+2, k+3 or k) It may be disabled or reset by the carry signal output from the +4) th stage.

In addition, the plurality of clock signals CLK supplied from the timing controller 4 to the gate driving circuit 2 are shifted by a predetermined time and are composed of a plurality of clock signals having different phases, and have at least one horizontal shift. A high level may be obtained during the period 1H, and a high period may overlap between clock signals. In addition, the plurality of clock signals CLK are configured in two or more phases.

The plurality of clock signals CLK are supplied from the timing controller 4 to the gate driving circuit 2 by two clock signal bus lines 11 and 12 .

A first clock signal bus line 11 is connected to the upper stages of the gate driving circuit 2 having a plurality of stages ST(1) to ST(n) that are cascade connected. A plurality of clock signals CLK are supplied to the lower stages of the gate driving circuit 2 including the plurality of cascade-connected stages ST(1) to ST(n). The plurality of clock signals CLK are supplied by the two clock signal bus line 12 .

That is, the same plurality of clock signals CLK are transmitted to the plurality of stages ST(1) to ST(n) of the gate driving circuit 2 through the first and second clock signal bus lines 11 and 12 . The upper/lower output deviation of the gate driving circuit 2 including the plurality of stages ST(1) to ST(n) is improved by applying to the upper and lower ends of the poles.

4 is a detailed configuration diagram of a clock signal output terminal of the timing controller of the flat panel display according to the first embodiment of the present invention.

4 shows the first and second clock signal bus lines 11 and 12 for supplying six-phase clock signals for convenience of explanation, but the present invention is not limited thereto, and clock signals of at least two or more phases are supplied. .

In the flat panel display according to the first embodiment of the present invention, the first and second clock signal bus lines 11 and 12 are branched from the clock signal output terminal of the timing controller 4 . The first clock signal bus line 11 supplies the plurality of clock signals CLK to the upper stages of the gate driving circuit 2 , and the second clock signal bus line 12 is The plurality of clock signals CLK are supplied to lower stages of the gate driving circuit 2 .

In this case, the first clock signal bus line 11 supplies the plurality of clock signals CLK to the upper stages of the gate driving circuit 2 through the damping resistor 13 .

The damping resistor 13 is formed for two purposes.

That is, when the timing controller 4 supplies a plurality of clock signals to the gate driving circuit 2 , a resistance must be reflected in each clock signal supply line in order to improve current and heat generation characteristics.

In addition, the first clock signal bus line 11 supplies the plurality of clock signals CLK to the upper stages of the gate driving circuit 2 , and the second clock signal bus line 12 is Since the plurality of clock signals CLK are supplied to the lower stages of the gate driving circuit 2 , the length of the second clock signal bus line 12 is smaller than the length of the first clock signal bus line 11 . is longer Accordingly, the line resistance A of the second clock signal bus line 12 has a larger value than the line resistance B of the first clock signal bus line 11 .

As such, when the line resistance A of the first clock signal bus line 11 and the line resistance B of the second clock signal bus line 12 are different from each other, the upper and lower stages of the gate driving circuit Output deviation will occur.

Therefore, in order to solve this problem, the sum of the line resistance A of the first clock signal bus line 11 and the damping resistance 13 is the line resistance ( Adjust the damping resistor 13 to be equal to B).

As described above, in the flat panel display device according to the present invention, the first and second clock signal bus lines 11 and 12 are provided, and the first clock signal bus line 11 is connected to the gate driving circuit 2 . The plurality of clock signals CLK are supplied to upper stages, and the second clock signal bus line 12 applies the plurality of clock signals CLK to lower stages of the gate driving circuit 2 . supply

Accordingly, a deviation between the clock signal supplied to the upper stages of the gate driving circuit and the clock signal supplied to the lower stages may be improved.

In addition, the load resistance and capacitance of the clock signal bus lines are reduced compared to the conventional flat panel display device.

That is, when a clock signal is supplied from the first stage to the last stage constituting the gate driving circuit through one clock signal bus line as in the prior art, the load resistance of the clock signal bus line in the 55U class flat panel display is about 400Ω. and the capacitance was about 630 pF.

However, as in the present invention, with the first and second clock signal bus lines 11 and 12 , the first clock signal bus line 11 is connected to the upper stages of the gate driving circuit 2 . A plurality of clock signals CLK are supplied, and the second clock signal bus line 12 supplies the plurality of clock signals CLK to the lower stages of the gate driving circuit 2, so that the 55U class flat panel In the display device, the load resistance of the clock signal bus lines according to the present invention was about 200Ω, and the capacitance of the clock signal bus lines was about 315pF.

Accordingly, the RC load applied to the clock signal bus line of the flat panel display device according to the present invention is reduced by about 1/4 compared to the RC load applied to the clock signal bus line of the conventional flat panel display device.

As described above, since the RC load applied to the clock signal bus line of the flat panel display according to the present invention is reduced compared to the conventional one, even if the clock signal bus line is added compared to the conventional one, the bezel size is the same as that of the conventional flat panel display. ) or reduce the bezel size compared to the conventional flat panel display.

Meanwhile, each stage constituting the gate driving circuit may be driven by one type of clock signal CLK, but the output unit of each stage may have a carry signal output unit and a scan signal output unit separately. .

5 is a block diagram of a k-th stage according to the present invention, and FIG. 6 is a circuit diagram of the output unit 20 of FIG. 5 .

Each stage of the gate driving circuit according to the present invention is set by the carry signal CROUT output from the previous stage and reset by the carry signal CROUT output from the subsequent stage, as shown in FIG. a node controller 10 for controlling voltages of the first and second nodes Q and Qb; and a clock signal for outputting one scan signal among the plurality of clock signals for outputting scan signals SCCLKs and a clock for outputting the plurality of carry signals Receives one of the signals CRCLKs for outputting the carry signal, and receives the scan signal SCOUT(k) and the carry signal CROUT(k) according to the voltage levels of the first and second nodes Q and Qb. )) to output the output unit 20 is configured to include.

As shown in FIG. 6 , the output unit 20 includes a carry signal output unit 21 and a scan signal output unit 22 .

The carry signal output unit 21 includes a carry pulse output clock signal terminal CRCLK(k) to which one of a plurality of carry signal output clock signals CRCLKs is applied, and a first gate low voltage terminal ( VGL1) is composed of a first pull-up transistor (Tpc) and a first pull-down transistor (Tdc) connected in series.

The first pull-up transistor Tpc is turned on/off according to the voltage level of the first node Q, and the first pull-down transistor Tdc is turned on/off according to the voltage level of the second node Qb. to output the carry signal CROUT(k).

The scan signal output unit 22 includes a scan signal output clock signal terminal SCCLK(k) to which one of a plurality of scan signal output clock signals SCCLKs is applied, and a second gate low voltage terminal. A second pull-up transistor Tp1 and a second pull-down transistor Td1 connected in series between VGL2, and a first for boosting connected between the gate electrode and the source electrode of the second pull-up transistor Tp1 Consists of a capacitor (C1).

The second pull-up transistor Tp1 is turned on/off according to the voltage level of the first node Q, and the second pull-down transistor Td1 is turned on/off according to the voltage level of the second node Qb. and output the scan signal SCOUT(k).

5 and 6, a clock signal for outputting one of the plurality of scan signal output clock signals SCCLKs and a clock signal for outputting the plurality of carry signals to the output unit 20 of each stage A clock signal for outputting one carry signal among (CRCLKs) may be applied.

Even in this case, the clock signals SCCLKs for outputting the plurality of scan signals and the clock signals CRCLKs for outputting the plurality of carry signals may be respectively supplied to upper and lower stages of the gate driving circuit through two clock signal bus lines. .

7 is a detailed configuration diagram of a clock signal output terminal of a timing controller of a flat panel display according to a second exemplary embodiment of the present invention.

As shown in FIG. 7 , the timing controller 4 of the flat panel display according to the second embodiment of the present invention includes a plurality of clock signal output terminals SCCLKs for outputting scan signals, and a plurality of clock signals CRCLKs for outputting carry signals. ) is provided with an output stage.

In addition, two clock signal bus lines 11a, 11b, 12a, and 12b respectively at the output terminal of the clock signal SCCLKs for outputting the plurality of scan signals and the output terminal of the clock signal CRCLKs for outputting the plurality of carry signals of the timing controller 4 . ) is branched.

The first clock signal bus line 11a supplies the plurality of scan signal output clock signals SCCLKs to the scan signal output units 22 of the upper stages of the gate driving circuit 2, and the second clock signal The signal bus line 12a supplies the plurality of carry signal output clock signals SCCLKs to the scan signal output units 22 of the lower stages of the gate driving circuit 2 .

The third clock signal bus line 11b supplies the plurality of carry signal output clock signals CRCLKs to the carry signal output units 21 of the upper stages of the gate driving circuit 2, and a fourth clock signal The bus line 12b supplies the plurality of carry signal output clock signals CRCLKs to the carry signal output units 21 of the lower stages of the gate driving circuit 2 .

At this time, the first clock signal bus line 11a supplies the plurality of scan signal output clock signals SCCLKs to the upper stages of the gate driving circuit 2 through a first damping resistor 13a, , the third clock signal bus line 11b supplies the plurality of carry signal output clock signals CRCLKs to the upper stages of the gate driving circuit 2 through a second damping resistor 13b.

Similarly, the sum of the line resistance A of the first clock signal bus line 11a and the first damping resistance 13a is equal to the line resistance B of the second clock signal bus line 12a The first damping resistor 13a is adjusted so that the sum of the line resistance C of the third clock signal bus line 11b and the second damping resistor 13b is equal to the fourth clock signal bus line 12b. ), the second damping resistor 13b is adjusted to be equal to the line resistance D.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

1: Display panel 2: Gate driving circuit
3: Data driving circuit 4: Timing controller
10: node control unit 20: output unit
11a, 11b, 12a, 12b: clock signal bus line
13a, 13b: damping resistor

Claims (6)

a timing controller outputting a plurality of clock signals;
a gate driving circuit having a plurality of stages connected to each other and sequentially outputting scan signals according to timings of the plurality of clock signals;
a first clock signal bus line for supplying the plurality of clock signals output from the timing controller to upper stages of the gate driving circuit; and
a second clock signal bus line for supplying the plurality of clock signals output from the timing controller to the lower stages of the gate driving circuit;
the first clock signal bus line supplies the plurality of clock signals to the upper stages of the gate driving circuit through a damping resistor;
The sum of the line resistance of the first clock signal bus line and the damping resistance is equal to the line resistance of the second clock signal bus line. delete delete a timing controller for outputting a plurality of scan signal output clock signals and a plurality of carry signal output clock signals;
a gate driving circuit having a plurality of stages sequentially connected to output a scan signal and a carry signal according to timings of the clock signal for outputting the scan signal and the plurality of clock signals for outputting the carry signal;
a first clock signal bus line for supplying the clock signals for outputting the plurality of scan signals outputted from the timing controller to the scan signal output units of the upper stages of the gate driving circuit;
a second clock signal bus line for supplying the clock signals for outputting the plurality of scan signals outputted from the timing controller to the scan signal output units of the lower stages of the gate driving circuit;
a third clock signal bus line for supplying the clock signals for outputting the plurality of carry signals outputted from the timing controller to carry signal output units of the upper stages of the gate driving circuit;
and a fourth clock signal bus line for supplying the clock signals for outputting the plurality of carry signals output from the timing controller to carry signal output units of stages at the lower end of the gate driving circuit,
The first and third clock signal bus lines supply the plurality of scan signal output clock signals and carry signal output clock signals to the upper stages of the gate driving circuit through first and second damping resistors, respectively;
a sum of the line resistance of the first clock signal bus line and the first damping resistance is equal to the line resistance of the second clock signal bus line;
The sum of the line resistance of the third clock signal bus line and the second damping resistance is equal to the line resistance of the fourth clock signal bus line. delete delete

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