KR20160094531A - Gate shift register and display device using the same - Google Patents

Abstract

The present invention relates to a gate shift register and a display device capable of reducing the falling time of scan pulse to quickly operate gate lines. The gate shift register and display device using the same comprise: a node control unit for controlling the voltage of a first node and a second node in response to a first carry signal, provided by a previous stage, and a second carry signal, provided by a next stage; and an output unit for outputting the scan pulse repeating the first through third voltages according to the level of a voltage of the first node and second node. The node control unit, in response to the second carry signal, may include a falling control unit which applies a third voltage, the lowest among the first through third voltages, at a falling timing of the scan pulse, in response to the second carry signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate shift register,

The present invention relates to a gate shift register, and more particularly, to a gate shift register capable of driving a gate line faster by reducing a polling time of a scan pulse, and a display using the gate shift register.

2. Description of the Related Art Recently, a display device widely used includes a liquid crystal display device and an organic light emitting display device.

In general, a display device includes a display panel for displaying an image, a gate driver for supplying a scan pulse to gate lines of the display panel, a data driver for supplying a data voltage to data lines of the display panel, And a timing controller for controlling the data driver.

The gate driver includes a gate shift register for driving a plurality of gate lines, and the gate shift register includes a plurality of stages for sequentially outputting scan pulses.

On the other hand, recent display devices have become larger and larger, have increased resolution, and have increased frame frequency. Therefore, there is a continuing need for a technology capable of driving the gate line more quickly.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and it is an object of the present invention to provide a gate shift register capable of driving a gate line faster by reducing a polling time of a scan pulse and a display device using the gate shift register.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

According to an aspect of the present invention, there is provided a gate shift register and a display apparatus using the gate shift register. The gate shift register includes a first carry signal provided from a previous stage and a second carry signal provided from a next stage, And an output unit for outputting a scan pulse for cyclically repeating the first to third voltages according to a voltage level of the first and second nodes, And a polling control unit for applying the third lowest voltage among the first to third voltages to the output terminal at the time of polling the scan pulse in response to the scan pulse.

According to the solution of the above-mentioned problems, the present invention has the following effects.

The present invention can reduce the polling time of the scan pulse and drive the gate line more quickly.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or may be apparent to those skilled in the art from the description and the description.

1 is a configuration diagram of a display device having a gate shift register according to an embodiment of the present invention.
2 is a configuration diagram of a gate shift register constituting the gate driver 4 shown in FIG.
3 is an output waveform diagram of a clock pulse (CLKs) according to an example of the present invention.
Fig. 4 is a configuration diagram of any k-th stage shown in Fig. 2. Fig.
5 is a configuration diagram of the second node control unit shown in FIG.
6 is a driving waveform diagram of the stage shown in Fig.
7A to 7D are circuit diagrams for explaining the driving method of the stage shown in FIG. 4 step by step.

The meaning of the terms described herein should be understood as follows. The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms. It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one. The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of a gate shift register and a display device using the gate shift register according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a display device having a gate shift register according to an embodiment of the present invention.

1 includes a display panel 2, a gate driver 4, a data driver 6, and a timing controller 8. The display panel 2 includes a display panel 2, a gate driver 4, a data driver 6,

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL intersecting with each other and a plurality of pixels P are provided at intersections of the display lines GL and DL. Each pixel P displays an image according to a video signal (data voltage) supplied from the data line DL in response to the scan pulse G supplied from the gate line GL. The display panel 2 may be a liquid crystal display panel, a field emission display panel, a plasma display panel, an organic light emitting diode display panel, an electrophoretic display panel, or the like.

The gate driver 4 is a GIP (gate in panel) type gate driver and is disposed in a non-display area of the display panel 2. [ The gate driver 4 includes a gate shift register for supplying a plurality of gate lines GL with a scan pulse G in accordance with a plurality of gate control signals GCS provided from the timing controller 8. [ The plurality of gate control signals GCS include a plurality of clock signals CLKs having different phases and a gate start signal VST for instructing start of driving of the gate driver 4. [

The gate shift register is selectively connected to the lines to which a plurality of clock signals are supplied to sequentially output the scan pulses and includes a plurality of stages composed of a plurality of transistors. Particularly, in the present invention, the scan pulse G is outputted so as to repeatedly repeat the first to third voltages. The present invention can reduce the polling time of the scan pulse (G) and drive the gate line faster. At this time, the node control unit includes a plurality of transistors constituting each stage. The node control unit controls the polling of the first, second, third, And a control unit. The gate shift register of the present invention will be described later in detail with reference to FIG. 2 to FIG.

The data driver 6 converts the digital image data RGB inputted from the timing controller 8 into a data voltage using a reference gamma voltage and supplies the converted data voltage to a plurality of data lines DL. This data driver 6 is controlled in accordance with a plurality of data control signals DCS provided from the timing controller 8. [

The timing controller 8 arranges image data (RGB) input from the outside in accordance with the size and resolution of the display panel 2 and supplies the image data to the data driver 6. The timing controller 8 generates a plurality of signals by using synchronizing signals SYNC input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, and a vertical synchronizing signal Vsync And supplies the gate and data control signals GCS and DCS to the gate driver 4 and the data driver 6, respectively.

2 is a configuration diagram of a gate shift register constituting the gate driver 4 shown in FIG. 3 is an output waveform diagram of a clock pulse (CLKs) according to an example of the present invention.

Referring to FIG. 2, a gate shift register according to an embodiment of the present invention includes a plurality of stages ST1 to STn, which are connected in a dependent manner.

The stages ST1 to STn receive any one of the plurality of clock pulses CLKs, the high potential voltage VDD and the first and second low potential potentials VSS1 and VSS2. The high-potential voltage VDD is set to a voltage higher than the first and second low-potential voltages VSS1 and VSS2, and the high-potential voltage VDD is defined as the above-described second voltage as the gate-on voltage VGH. And the second low potential voltage VSS2 is defined as the above-mentioned first voltage as the gate-off voltage VGL. The first low potential voltage VSS1 is defined as the third voltage described above as a voltage lower than the second low potential potential VSS2.

The plurality of clock pulses CLKs may be composed of eight-phase clock pulses CLKs shifted by one horizontal period and overlapped with each other for four horizontal periods, as shown in FIG. However, the present invention is not limited to eight-phase clock pulses (CLKs).

The stages ST1 to STn are provided with two input terminals and two output terminals and are connected to the scan signals G1, G2, G3, ... and the first and second carry signals CR1 , CR2. The first carry signal (CR1) is supplied to at least one subsequent stage, and the second carry signal (CR2) is supplied to at least one previous stage. Here, the "previous single stage" is located above the reference stage ST. For example, the front stage based on k (1 < k & K-1 stage STk-1 ". Stage from the (k + 1) th stage STk + 1 to the (n + 1) th stage STn, &Lt; / RTI &gt;

Each of the stages ST1 to STn operates in response to the first carry signal CR1 from the previous stage and the second carry signal CR2 from the next stage.

In the illustrated example, the carry signal output from any k-th stage is supplied to the (k + 4) -th stage as the first carry signal CR1 and is supplied to the (k-4) -th stage as the second carry signal CR2 Respectively. In this case, different gate start signals VSTs are supplied as the first carry signal CR1 to the first to fourth stages ST1 to ST4, respectively.

Fig. 4 is a configuration diagram of any k-th stage shown in Fig. 2. Fig. In the illustrated example, the fifth clock pulse CLK5 is supplied from the eight-phase clock pulse to the k-th stage.

Referring to FIG. 4, each of the stages ST includes a first carry signal CR1 provided from a (k-4) th stage and a second carry signal CR2 provided from a (k + An output unit for outputting a scan pulse Gk for cyclically repeating the first to third voltages according to the voltages of the first and second nodes Q and QB; (S2).

The node controller charges the voltage of the first node Q in response to the first carry signal CR1 and simultaneously discharges the voltage of the second node QB. In addition, the node controller charges the voltage of the second node QB while discharging the voltage of the first node Q in response to the second carry signal CR2. The node control unit applies the third lowest voltage among the first to third voltages to the output terminal at the time of polling the scan pulse output from each stage. To this end, the node controller includes a first node controller S1 for controlling the voltage of the first node Q, a second node controller 10 for controlling the voltage of the second node QB, And a polling control unit for controlling the time.

The first node control unit S1 includes first, third, and fourth transistors T1, T3, and T4. The first transistor Tl supplies a high potential voltage VDD to the first node Q in response to a first carry signal CR1. The third and fourth transistors T3 and T4 supply a first low potential voltage VSS1 to the first node Q in accordance with the voltage level of the second node QB. In the illustrated example, the second node QB includes a QB1 node QB1 driven for an odd frame period and a QB2 node QB2 driven for an even frame period.

5 is a configuration diagram of the second node control unit shown in FIG.

Referring to FIG. 5, the second node controller 10 includes fifth to ninth transistors T5 to T9. The fifth transistor T5 supplies a first low potential voltage VSS1 to the QB1 node QB1 in response to the first carry signal CR1.

The sixth transistor T6 supplies a first low potential voltage VSS1 to the QB2 node QB2 in response to the first carry signal CR1. The seventh transistor T7 supplies an odd high voltage VDD_O to the QB1 node QB1 in response to an odd high voltage VDD_O supplied in an odd frame period. The eighth transistor T8 supplies an even higher high voltage VDD_E to the QB2 node QB2 in response to an even higher voltage VDD_E supplied in an even frame period. The ninth transistor T9 supplies a first low potential voltage VSS1 to the QB1 and QB2 nodes QB1 and QB2 according to the voltage level of the first node Q. [

4, the polling control unit includes a second transistor T2 for supplying a third voltage, i.e., a first low potential voltage VSS1, to the output terminal in response to the second carry signal CR2 .

The output unit S2 includes first and second pull-up transistors PU1 and PU2 and first and second pull-down transistors PD1 and PD2.

The first pull-up transistor PU1 supplies a high-potential voltage VDD to the output terminal in accordance with the voltage level of the first node Q.

The second pull-up transistor PU2 supplies the clock pulse CLK5 input to the output terminal in accordance with the voltage level of the first node Q.

The first pull-down transistor PD1 supplies a first voltage, that is, a second low potential voltage VSS2 to the carry signal output terminal in accordance with the voltage level of the second node QB. To this end, the first pull-down transistor PD1 includes a first sub pull-down transistor PDO1 controlled by the QB1 node QB1 and a second sub pull-down transistor PDE1 controlled by the QB2 node QB2 .

The second pull-down transistor PD2 supplies a third voltage, that is, a first low potential voltage VSS1 to the carry signal output terminal in accordance with the voltage level of the second node QB. To this end, the second pull-down transistor PD2 includes a third sub pull-down transistor PDO2 controlled by the QB1 node QB1 and a fourth sub pull-down transistor PDE2 controlled by the QB2 node QB2 .

The carry signal output through the carry signal output terminal is supplied to at least one subsequent stage as the first carry signal CR1 and at least one previous stage as the second carry signal CR2.

6 is a driving waveform diagram of the stage shown in Fig. 7A to 7D are circuit diagrams for explaining the driving method of the stage shown in FIG. 4 step by step.

Hereinafter, a method of driving a gate shift register according to an example of the present invention will be described with reference to FIGS. 6 to 7. FIG.

First, in the first period (P1), the first carry signal (CR1) provided from the previous stage and the gate start signal are supplied to the stage. Then, in response to the first carry signal (CR1) of the node controller, the voltage of the first node (Q) is precharged and the voltage of the second node (QB) is discharged.

In the second period P2, any one of the plurality of clock pulses CLKs, for example, the fifth clock signal CLK5 is turned on at the gate-on voltage (VGH) state by the drain of the second pull- Is supplied to the electrode. Then, the voltage level of the first node Q is bootstrapped and raised to a level higher than the gate-on voltage VGH by the parasitic capacitance of the second pull-up transistor PU2. Thus, the first and second pull-up transistors PU1 and PU2 are brought into a complete turn-on state, and a pulse of the second voltage, that is, the gate-on voltage (VGH) state is output through the output terminal and the carry signal output terminal .

Then, in the third period P3, the second carry signal CR2 supplied from the next stage is supplied to the stage. Then, the polling control unit, that is, the second transistor T2 is turned on to supply the first low potential voltage VSS1 to the output terminal. Accordingly, the output terminal is discharged to a third voltage lower than the gate-off voltage VGL. The present invention can reduce the polling time of the scan pulse and drive the gate line faster. Specifically, as a result of the experiment, it was confirmed that the scan pulse output from the gate shift register according to the related art had a polling time of about 768.39 ns, whereas the gate shift register according to the present invention had a scan pulse polling time reduced to about 665.72 ns .

Meanwhile, in the third period P3, the second node QB is charged from the second node control unit, so that the first node Q is discharged to the first low potential voltage VSS1.

Subsequently, in the fourth period P4, the first and second pull-down transistors PD1 and PD2 operate according to the second node QB charged in the third period P3. That is, the first pull-down transistor PD1 is turned on in accordance with the voltage level of the second node QB2 to supply the second low potential voltage VSS2 to the output terminal. The second pull-down transistor PD2 is turned on according to the voltage level of the second node QB2 to supply the first low potential voltage VSS1 to the carry signal output terminal.

As described above, the present invention can reduce the polling time of the scan pulse by applying a voltage lower than the gate off voltage to the output terminal at the time of polling the scan pulse. Therefore, the present invention can drive the gate line more quickly.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of. Therefore, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention.

T2: second transistor (polling control section)
Q: First node
QB1, QB2: the second node
10:

Claims (6)

A node controller for controlling the voltages of the first and second nodes in response to a first carry signal provided from the previous stage and a second carry signal provided from the next stage; And
And an output unit for outputting a scan pulse for cyclically repeating the first to third voltages according to the voltage levels of the first and second nodes;
Wherein the node control unit comprises a polling control unit for applying a third lowest voltage among the first to third voltages to an output terminal at the time of polling the scan pulse in response to the second carry signal. The method according to claim 1,
The polling control unit
And a transistor for supplying the third voltage to the output terminal in response to the second carry signal. The method according to claim 1,
The first voltage is a gate-off voltage,
The second voltage is a gate-on voltage,
And the third voltage is a voltage lower than the gate-off voltage. The method according to claim 1,
The output
A first pull-up transistor for supplying the second voltage to the output terminal according to a voltage level of the first node;
A second pull-up transistor for supplying a clock signal inputted according to a voltage level of the first node to a carry signal output terminal;
A first pull-down transistor for supplying the first voltage to the output terminal according to a voltage level of the second node; And
And a second pull-down transistor for supplying the third voltage to the carry signal output terminal in accordance with the voltage level of the second node. 5. The method of claim 4,
Wherein a signal output via the carry signal output terminal is supplied to the at least one subsequent stage as the first carry signal and to the at least one previous stage as the second carry signal. A display panel having a plurality of gate lines; And
And a gate shift register embedded in a non-display area of the display panel to drive the plurality of gate lines;
Wherein the gate shift register comprises the gate shift register according to any one of claims 1 to 5.

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