KR20140095926A - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display, comprising a display panel on which data lines and gate lines are crossed and pixels are disposed in a matrix type; a source drive IC which supplies negative polarity data voltage and positive polarity data voltage to the data lines; and a common voltage compensating unit which supplies common voltage to a common electrode of the pixels. The source drive IC includes a first output buffer which supplies the positive polarity data voltage to the data lines and a second output buffer which supplies the negative polarity data voltage to the data lines. A ground terminal of the first output buffer is connected to a drive power terminal of an inversion amplifier.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device that varies a driving frequency of data.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. Liquid crystal cells of a liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

BACKGROUND ART [0002] A liquid crystal display device has been widely applied to a display device of a portable information terminal such as a smart phone, a tablet, a laptop computer or a notebook computer, and a medium and large display device such as a monitor or a television.

The important performance indicators of small information terminals are lightweight, thin, use time and battery performance. Liquid crystal display devices applied to small information terminals are also required to be lightweight and low in power consumption.

As a method for lowering the power consumption of a liquid crystal display device, a method of applying a half VDD (Half VDD) technique to a source drive IC (Integrated Circuit) is known. The source drive IC supplies the data voltages to the data lines of the display panel. Half VDD technology can reduce power consumption by applying a half VDD voltage (HVDD) which is set to a power supply voltage applied to the output buffer of the source drive IC to a voltage which is set to about 1/2 voltage with respect to the high level supply voltage (VDD). However, some of the liquid crystal display devices can not apply the half VDD technique because of their driving characteristics.

The present invention provides a liquid crystal display device capable of reducing power consumption of a source drive IC even in a liquid crystal display device in which half VDD application is difficult.

A liquid crystal display of the present invention includes: a display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix type; A source drive IC for supplying a positive data voltage and a negative data voltage to the data lines; And a common voltage compensation unit for supplying a common voltage to the common electrode of the pixels.

The source driver IC includes a first output buffer for supplying the positive data voltage to the data lines and a second output buffer for supplying the negative data voltage to the data lines.

The ground terminal of the first output buffer is connected to the driving power terminal of the inverting amplifier.

The present invention connects the ground terminal of the output buffer formed in the source drive IC and the driving power terminal of the common voltage compensating unit. As a result, the present invention can reduce the power consumption of the source drive IC even in a liquid crystal display device in which half VDD application is difficult.

Furthermore, the present invention can reduce the battery consumption of the information terminal to which the liquid crystal display device is applied, increase the use time, and reduce the battery size, thereby improving the light weight and thinness of the information terminal.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
2 is a waveform diagram showing a data voltage, a gate pulse, and a voltage charged in the liquid crystal cell output from the source drive IC.
3 is a waveform diagram illustrating gamma reference voltages.
FIG. 4 is a view showing gamma reference voltages applied to a liquid crystal display of some IPS modes. FIG.
5 is a diagram showing the circuit configuration of the source drive IC (SDIC).
6 is a diagram showing the power supply voltage condition of the half VDD technique applied to the output buffer of the source drive IC (SDIC).
7 is a view showing an output buffer and a common voltage compensating unit of a source driver IC according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a display panel 10, a timing controller 20, a data driver 12, a gate driver 14, a power source 16, (18) and the like.

In the display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes pixels arranged in a matrix form by an intersection structure of the data lines S1 to Sm and the gate lines G1 to Gn. The pixels are divided into a red subpixel, a green subpixel, and a blue subpixel as shown in FIG. Each of the subpixels includes liquid crystal cells Clc, a TFT, and a storage capacitor Cst.

The pixel array in which the input image is displayed on the display panel 10 is divided into a TFT array and a color filter array. On the lower glass substrate of the display panel 10, a TFT array is formed. The TFT array includes TFTs connected to the pixel electrodes 1 of the liquid crystal cells Clc, gate lines G1 to Gn crossing the data lines S1 to Sm, data lines S1 to Sm, And a storage capacitor Cst. The liquid crystal cells Clc are connected to the TFT and are driven by the liquid crystal molecules driven by the electric field between the data voltage applied to the pixel electrode 1 and the common voltage CVcom applied to the common electrode 2, Vdata) to adjust the light transmittance. On the upper glass substrate of the display panel 10, a color filter array including a black matrix, a color filter and the like is formed. On the upper glass substrate and the lower glass substrate of the display panel 10, an alignment film for attaching a polarizing plate and setting a pre-tilt angle of liquid crystal is formed.

The common electrode (2) is supplied with the common voltage (CVcom) output from the common voltage compensating unit (18). The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The display panel 10 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 20 supplies the digital video data of the input image input from the host system 30 to the data driver 12. The timing controller 20 receives a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock CLK from the host system 30.

The timing controller 20 generates timing control signals for controlling the operation timing of the data driver 12 and the gate driver 14 based on the timing signal input from the host system 30. [ The timing control signals include a gate timing control signal for controlling the operation time of the gate driver 14 and a data timing control signal for controlling the operation timing of the data driver 12 and the vertical polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the start timing of the gate drive IC constituting the gate driver 14. [ The gate shift clock GSC controls the shift timing of the gate pulse by a clock signal commonly input to the gate drive ICs. The gate output enable signal GOE controls the output timing of the gate drive ICs.

The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, a source output enable signal SOE, and the like. The source start pulse SSP controls the data sampling start timing of the source drive ICs constituting the data driver 12. [ The source sampling clock SSC is a clock signal for controlling the sampling timing of data in each of the source drive ICs. The source output enable signal SOE controls the output timing of the source drive ICs. The source start pulse SSP and the source sampling clock SSC may be omitted if the interface for signal transmission between the timing controller 20 and the data driver 12 is a mini LVDS (low voltage differential signaling).

The data driver 12 includes one or more source drive ICs. Each of the source drive ICs includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. A data timing control signal is input to the source drive ICs together with the digital video data of the input image from the timing controller 20. [ Gamma reference voltages GMA1 to GMA14, a high potential direct current power source voltage VDD and a half VDD voltage HVDD (HGND) are input from the power supply section 16 to the source drive ICs. HVDD (HGND) is a voltage that is lower than VDD and higher than the ground voltage (GND or VSS), and can be set to about half of the voltage as VDD. The gamma reference voltages GMA1 to GMA4 include the positive gamma reference voltages GMA1 to GMA7 and the negative gamma reference voltages GMA8 to 14 as shown in FIGS. The source driver IC divides the gamma reference voltages GMA1 to GMA14 using the built-in voltage divider circuit to generate the positive gamma compensation voltages PGMA and the negative gamma compensation voltages NGMA corresponding to the gradation levels of the data, .

The source drive ICs latch digital video data (RGB) under the control of the timing controller 20. The source drive ICs convert the digital video data (RGB) to analog positive / negative gamma compensation voltages (PGMA, NGMA) to generate a data voltage and in response to the polarity control signal POL, . The source drive ICs output the positive / negative polarity data voltage to the data lines S1 to Sm through the output buffer in response to the source output enable signal SOE.

The gate drive ICs of the gate driver 14 include a shift register and a level shifter. The gate driver 14 sequentially supplies gate pulses to the gate lines G1 to Gn in synchronization with the positive / negative data voltages in response to the gate timing control signal. The gate pulse swings between the gate high voltage (Vgh) and the gate low voltage (Vgl).

The host system 30 may be implemented in any one of a television system, a home theater system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a phone system. The host system 30 scales the digital video data RGB of the input image according to the resolution of the display panel 10. The host system 30 transmits the timing signals Vsync, Hsync, DE, and MCLK to the timing controller 20 together with the digital video data RGB of the input image.

The power source unit 16 converts the DC source power from the host system 30 using the DC-DC converter to generate the DC power source voltages VDD and HVDD (HGND), the gamma reference voltages GMA1 to GMA14, Vcom, and gate voltages Vgh and Vgl, which are necessary for driving the display panel 10.

The common voltage compensating section 18 inverts and amplifies the difference voltage between the source common voltage Vcom input from the power supply section 16 and the common voltage VcomFB fed back from the common electrode 2 of the display panel 10 To the common electrode (2). Since the common voltage CVcom applied to the common electrode 2 is coupled to the pixel electrode 1, the data lines S1 to Sm and the gate lines G1 to Gm, the data voltage Vdata Can be changed according to the gate voltages (Vgh, Vgl). Since the common voltage CVcom is the reference voltage of the liquid crystal cell Clc, the variation should be minimized. The common voltage compensating unit 18 supplies the feedback common voltage VcomFB and the voltage CVcom whose phase is inverted to the common electrode 2 to suppress the fluctuation of the common electrode voltage.

The liquid crystal display device is driven in an inversion mode in which the polarity of the data voltage charged in the adjacent liquid crystal cells is opposite to each other and the polarity of the data voltage is periodically inverted in order to reduce direct current residual image and prevent deterioration of the liquid crystal. To this end, the source drive IC (SDIC) outputs a data voltage (Vdata) whose polarity is inverted every one horizontal period as shown in FIG.

2, the voltage (+ Vp) of the first liquid crystal cell charged with the positive data voltage Vdata (+) is lowered by? Vp due to the parasitic capacitance of the TFT or the like. The voltage -Vp of the second liquid crystal cell charged with the negative data voltage Vdata (+) is lowered by? Vp due to the parasitic capacitance of the TFT or the like. Therefore, the common voltage (CVcom) is generally tuned to a voltage lower by ΔVp than the ideal voltage so that the positive voltage and the negative voltage charged in the liquid crystal cells are symmetrical with respect to the common voltage (CVcom). Assuming no? Vp, the common voltage CVcom is equal to HVDD (HGND), which is the intermediate voltage between GMA7 and GMA8 in FIG. In Fig. 2, "GP1, GP2" means a gate pulse synchronized with the data voltage (Vdata (+/-)).

3 is a waveform diagram showing gamma reference voltages (GMA1 to GMA14). In Figure 3, the abscissa is the gradation of the data and the ordinate is the gamma reference voltages (GMA1-14). 4 is a view showing gamma reference voltages applied to a liquid crystal display of some IPS modes.

3 and 4, the gamma reference voltages GMA1 to GMA14 are divided between the high potential power supply voltage VDD and the ground voltage GND through the voltage dividing circuit of the power supply unit 16. [ The high-potential power supply voltage VDD is a direct-current voltage of about 7.5 V or more in the case of FIG. 4, and the ground voltage GND is 0V. The gamma reference voltages (GMA1 to GMA14) are divided into positive gamma reference voltages (PGMA) and negative gamma reference voltages (NGMA).

The liquid crystal display of the IPS mode is driven in a normally black mode. As can be seen from the transmittance versus voltage (TV) curve of FIG. 4, the Normold Black mode has a higher transmittance as the data voltage applied to the liquid crystal cell is higher.

4, when the lowest positive polarity gamma compensation voltage PGMA is the seventh gamma reference voltage GMA7 and the positive polarity data voltage Vdata (+) applied to the liquid crystal cell is GMA7, the light transmittance of the liquid crystal cell is It is minimized. The maximum positive polarity gamma compensation voltage PGMA is the first gamma reference voltage GMA1 and the light transmission amount of the liquid crystal cell is maximized when the positive polarity data voltage Vdata (+) applied to the liquid crystal cell is GMA1. Therefore, the white gradation voltage of the positive polarity data voltage Vdata (+) is set to the voltage of GMA1, and the black gradation voltage of the negative polarity data voltage Vdata (+) is set to the voltage of GMA7.

The lowest negative polarity gamma compensation voltage PGMA is the eighth gamma reference voltage GMA8 and the light transmittance of the liquid crystal cell is minimized when the negative polarity data voltage Vdata (-) applied to the liquid crystal cell is GMA8. The maximum negative gamma compensation voltage NGMA is the 14th gamma reference voltage GMA14 and the light transmission amount of the liquid crystal cell is maximized when the negative polarity data voltage applied to the liquid crystal cell is GMA14. Therefore, the white gradation voltage of the negative data voltage Vdata (-) is set to the voltage of GMA 14, and the black gradation voltage of the negative data voltage Vdata (-) is set to the voltage of GMA8.

5 is a diagram showing the circuit configuration of the source drive IC (SDIC).

5, each of the source drive ICs (SDIC) drives k (k is a positive integer less than m) data lines and includes a data register 51, a shift register 52, And includes a latch array 53, a second latch array 54, a digital-to-analog converter (hereinafter referred to as DAC) 55, a charge share circuit 56 and an output circuit 57 do.

The data register 51 receives the digital video data (RGBWodd, RGBeven) input through the mini LVDS interface transmission system and supplies the digital video data (RGBWodd, RGBeven) to the first latch array 53. The shift register 52 shifts the sampling signal in accordance with the source sampling clock SSC. In addition, the shift register 52 generates a carry signal (CAR) when data exceeding the number of latches of the first latch array 53 is supplied. The first latch array 53 samples and latches the digital video data RGBWodd and RGBWeven from the data restoring unit 52 in response to a sampling signal sequentially input from the shift register 52 and then latches and outputs the same. The second latch array 54 latches the data input from the first latch array 53 and then forwards the data to the second latch array 54 of the other source drive IC during the low logic period of the source output enable signal SOE Simultaneously outputs the latched data. The DAC 55 converts the digital video data input from the second latch array 54 using the positive gamma compensation voltages PGMA and the negative gamma compensation voltages NGMA to a positive polarity data voltage and a negative polarity data voltage & . The DAC 55 outputs a data voltage whose polarity is inverted in the N horizontal period period in response to the polarity control signal POL. For this purpose, the DAC 55 includes a P-decoder for receiving positive gamma compensation voltages (PGMA) and digital video data and outputting positive polarity data voltages, negative polarity gamma compensation voltages NGMA and digital video data A N-decoder for receiving the negative data voltage, a multiplexer for selecting the output of the P-decoder and the output of the N-decoder in response to the polarity control signal POL, and the like.

The charge share circuit 56 shorts the neighboring data output channels during the high logic period of the source output enable signal SOE to output the average value of the neighboring data voltages to the charge sharing voltage. The output circuit 57 supplies the positive polarity data voltage and the negative polarity data voltage to the data lines using the output buffer shown in FIG. The output buffer provides positive and negative data voltages to the data lines without reducing the effects of panel load variations and signal attenuation. To reduce the power consumption in these output buffers, half VDD technology can be applied to the output buffers. However, it is difficult to apply the half VDD technique to the output buffer in the liquid crystal display of some IPS mode as shown in Fig. This will be described with reference to FIG.

6, the P output buffer 61 receives the positive polarity data voltage VPx and adjusts the current flowing between VDD and the output terminal according to the data voltage VPx to generate the positive polarity data voltage Vdata (+), ) To the data line. The N output buffer 62 receives the negative data voltage VNx and adjusts the current flowing between VDD and the output terminal according to the data voltage VNx to supply the negative data voltage Vdata do.

The half VDD driving condition that can assure the reliability of the P output buffer 61 is that the dynamic range of the P output buffer 61 is VDD-0.2V to HGND + 0.2V. HGND is the same voltage as HVDD. A voltage of VDD-0.2V is applied to the driving power supply terminal of the P output buffer 61 and a ground terminal of HGND + 0.2 is applied to the ground terminal of the P output buffer 61 in order to satisfy the half VDD driving condition of the P output buffer 61. [ V is applied.

The half VDD driving condition that can guarantee the reliability of the N output buffer 62 is that the dynamic range of the N output buffer 62 is HVDD-0.2V to GND + 0.2V. HGND is input to the ground terminal of the P output buffer 61 as a voltage such as HVDD. Therefore, in order to satisfy the half VDD driving condition of the N output buffer 62, a voltage of HVDD-0.2V is applied to the driving power supply terminal of the N output buffer 62, and a ground terminal of the N output buffer 62 is connected to GND A voltage of +0.2 V is applied.

The IPS mode liquid crystal display device shown in Fig. 4 does not satisfy the half VDD driving condition that can guarantee reliability. In order to satisfy the half VDD driving conditions of the P output buffer 61 and the N output buffer 62, the seventh gamma holding voltage (GMA7), which is the positive polarity black gradation voltage, and the eighth gamma reference The voltage difference between the voltage (GMA8) should be at least 0.4 V. However, in some IPS mode liquid crystal displays, the voltage difference between GMA7 and GMA8 is less than 0.4V.

In the case of FIG. 4, the voltage difference between GMA7 and GMA8 is 0.36V. In order to meet the half VDD driving condition, GMA7 can be increased and GMA8 can be lowered. However, when the GMA7 is increased, as shown in FIG. 4, the brightness of the black gradation becomes higher, so that the contrast ratio (CNR) of the image reproduced in the liquid crystal display device is lowered and the image quality deteriorates. For example, in FIG. 4, HVDD (HGND) is 4.1 V, which is the intermediate voltage between GMA7 and GMA8. In order to satisfy the half VDD driving condition of the P output buffer 61, a voltage of 4.10 + 0.2 = 4.30 V or more should be applied to the ground terminal of the P output buffer 61, but in the IPS mode liquid crystal display device of FIG. 4, GMA7, which is the gradation voltage, is 4.280V.

The present invention lowers the power consumption of the source drive IC (SDIC) by connecting the source driver IC (SDIC) and the common voltage compensator 18 as shown in 7 when the half VDD driving condition is not satisfied.

7 is a diagram showing output buffers 61 and 62 and a common voltage compensator 18 of a source drive IC according to an embodiment of the present invention.

Referring to Fig. 7, the VDD voltage is supplied to the driving power supply terminal of the P output buffer 61. [ The ground terminal of the P output buffer 61 is connected to the driving power supply terminal of the common voltage compensating unit 18. [

In the common voltage compensating unit 18, the common voltage VcomFB fed back from the common electrode 2 is inputted to the inverting input terminal (-) of the inverting amplifier, 16 are supplied with the source common voltage Vcom. A voltage higher than the ground VDD (HVDD) and higher than the ground voltage (GND) is applied to the driving power supply terminal of the common voltage compensating unit 18 because of the common voltage optimization considering? Vp. A ground voltage (GND) is applied to the ground terminal of the common voltage compensating unit (18).

The common voltage CVcom is tuned to a voltage lower by? Vp than HVDD as described above. To this end, a voltage (HVDD (HGND)) lower than the high potential supply voltage (VDD) and higher than the ground voltage is applied to the driving power supply terminal of the inverting amplifier of the common voltage compensating section (18). When the voltage applied to the driving power supply terminal of the common voltage compensating unit 18 is supplied to the ground terminal of the P output buffer 61, the P output buffer 61 can reduce the power consumption without lowering the contrast ratio.

The N output buffer 61 is driven separately from the P output buffer 61 and driven to the high potential power supply voltage VDD without being driven by the half VDD. The high power supply voltage VDD is applied to the driving power supply terminal of the N output buffer 61 and the ground voltage GND is applied to the ground terminal of the N output buffer 61.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 12: data driver
14: Gate driver 16: Power supply
18: common voltage compensation unit 20: timing controller
61, 62: Output buffer of the source drive IC

Claims (5)

A display panel in which data lines and gate lines are crossed and pixels are arranged in a matrix type;
A source drive IC for supplying a positive data voltage and a negative data voltage to the data lines; And
And a common voltage compensation unit for supplying a common voltage to the common electrode of the pixels,
Wherein the source driver IC includes a first output buffer for supplying the positive data voltage to the data lines and a second output buffer for supplying the negative data voltage to the data lines,
Wherein the common voltage compensating unit supplies the common voltage to the common electrode through an inverting amplifier for inverting and amplifying a difference voltage between a source common voltage input from the power supply unit and a common voltage fed back from the common electrode,
And the ground terminal of the first output buffer is connected to the driving power terminal of the inverting amplifier. The method according to claim 1,
Wherein a high potential power supply voltage (VDD) is applied to a driving power supply terminal of the first output buffer and a ground voltage is applied to a ground terminal of the first output buffer and a driving power supply terminal of the inverting amplifier, And a voltage higher than the voltage is applied to the liquid crystal layer. The method according to claim 1,
Wherein the high power supply voltage (VDD) is applied to a driving power supply terminal of the second output buffer, and the ground voltage is applied to a ground terminal of the second output buffer. The method according to claim 1,
Wherein the common voltage compensating unit supplies the common voltage to the common electrode through an inverting amplifier for inverting and amplifying a difference voltage between a source common voltage inputted from a power supply unit and a common voltage fed back from the common electrode, . 5. The method according to any one of claims 1 to 4,
Wherein the voltage difference between the black gradation voltage of the positive data voltage and the black gradation voltage of the negative data voltage is less than 0.4V.

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