KR20140092145A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device according to one embodiment of the present invention includes first and second lower electrodes. According to one embodiment of the present invention, the first and the second lower electrodes have different horizontal cross-section shapes. According to one embodiment of the present invention, the horizontal cross-section of the first lower electrodes has a convex surface.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor memory device and a manufacturing method thereof,

Technical aspects of the present invention relate to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device including a capacitor.

As the area of the area where the unit memory cells are formed due to the reduction of the design rule in a semiconductor memory device such as a dynamic random access memory (DRAM) is reduced, a capacitor occupying a large area in the unit memory cell is formed I am having difficulties. Particularly, due to the limitations of the process technology, for example, the technical limitations of the photolithography process and the etching process, it is difficult to form and separate the lower electrodes of the respective capacitors formed at a high density in a limited area, And the reliability is lowered.

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor memory device including a lower electrode having a novel structure that can satisfy a very small design rule by overcoming the limitations of a process technology and can improve characteristics and reliability, .

A semiconductor memory device according to an aspect of the present invention includes a plurality of first and second lower electrodes, wherein the plurality of first and second lower electrodes have different horizontal cross-sectional shapes .

In some embodiments, the plurality of first and second lower electrodes may be alternately arranged one by one in the row direction and the column direction on the first plane to form a matrix shape.

In some embodiments, the horizontal cross-sectional shape of the plurality of first lower electrodes may have an outwardly convex curved surface, and the horizontal cross-sectional shape of the plurality of second lower electrodes may have at least four vertices, It may have a curved surface.

In some embodiments, the plurality of third lower electrodes may further include a plurality of third lower electrodes positioned on the same plane as the plurality of first and second lower electrodes, And the second lower electrodes may have different horizontal cross-sectional shapes.

In some embodiments, the plurality of first to third lower electrodes may be arranged in a matrix shape in a row direction and a column direction on a first plane, wherein in the first row and the first column, And the second lower electrodes may be arranged alternately one by one, and in the second row neighboring the first row and the second row neighboring the first row, the plurality of second and third lower electrodes may be arranged alternately And may be alternately arranged one by one.

In some embodiments, the horizontal cross-sectional shape of the plurality of first lower electrodes may have an outwardly convex curved surface, and the horizontal cross-sectional shapes of the plurality of second and third lower electrodes may each include at least four vertices And has concave curved surfaces on the outside, and the directions of lines connecting the opposed vertices may be different from each other.

In some embodiments, one first lower electrode and two second lower electrodes may alternately be arranged along the row direction and the column direction.

In some embodiments, the horizontal cross-sectional shape of the plurality of first lower electrodes may have an outwardly convex curved surface, and the horizontal cross-sectional shape of the plurality of second lower electrodes may have at least three vertices, It may have a curved surface.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: forming a plurality of first through-holes in a mold layer on a substrate having a plurality of conductive regions, Forming a plurality of first spacers on the inner walls of each of the plurality of first holes and exposing the conductive regions to define a plurality of first lower electrode regions having a first horizontal cross sectional shape, Filling the plurality of first lower electrode regions with a conductive material to form a plurality of first lower electrodes; exposing an outer wall of the plurality of first spacers by removing the mold layer; A plurality of second spacers are formed on an outer wall of the first spacers of the first spacer, and adjacent second spacers are brought into contact with each other, Exposing all regions to define a plurality of second lower electrode regions having a second horizontal cross-sectional shape, and filling the plurality of second lower electrode regions with a conductive material to form a plurality of second lower electrodes do.

In some embodiments, removing the plurality of first and second spacers to expose an outer wall of the plurality of first and second lower electrodes may include exposing a plurality of first and second lower electrodes Forming a plurality of third lower electrode regions having a third horizontal cross-sectional shape by exposing the conductive regions to form third spacers of the plurality of third spacers, wherein the plurality of third spacers are adjacent to each other, 3) filling the lower electrode regions with a conductive material to form a plurality of third lower electrodes.

According to the semiconductor memory device and the method of manufacturing the same according to the present invention, the lower electrodes having various horizontal cross-sectional shapes are employed as the storage electrodes of the capacitor, so that the limit of the process technology can be overcome, And the characteristics and reliability can be ensured even in the case of super-high integration.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a perspective view showing a partial structure of a semiconductor memory device according to a first embodiment of the present invention.
FIGS. 2A and 2B to FIGS. 7A and 7B are diagrams according to a process sequence for explaining an exemplary manufacturing method of a semiconductor device according to the first embodiment of the present invention. , ... And FIG. 7A are plan views illustrating planar shapes of some of the components, and FIGS. 2B, 3B,... , And Fig. 7B is a cross-sectional view taken along line II-II of Fig. 2A, Fig. And FIG. 7A is a cross-sectional view illustrating the structure of the AA-AA 'cross section and the AX-AX' cross section of FIG. 7A.
8 is a perspective view showing a partial structure of a semiconductor memory device according to a second embodiment of the present invention.
FIGS. 9 to 15 are diagrams illustrating a method of manufacturing an exemplary semiconductor memory device according to a second embodiment of the present invention. Referring to FIGS. 9 to 15, FIG.
16 is a perspective view showing a partial structure of a semiconductor memory device according to a third embodiment of the present invention.
17 to 21 are diagrams illustrating a method of fabricating a semiconductor memory device according to a third embodiment of the present invention. Referring to FIGS. 17 to 21, FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and a duplicate description thereof will be omitted.

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various elements, regions, layers, regions and / or elements, these elements, components, regions, layers, regions and / It should not be limited by. These terms do not imply any particular order, top, bottom, or top row, and are used only to distinguish one member, region, region, or element from another member, region, region, or element. Accordingly, the first member, region, region, or element described below may refer to a second member, region, region, or element without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used, predefined terms are to be interpreted as having a meaning consistent with what they mean in the context of the relevant art, and unless otherwise expressly defined, have an overly formal meaning It will be understood that it will not be interpreted.

If certain embodiments are otherwise feasible, the particular process sequence may be performed differently from the sequence described. For example, two processes that are described in succession may be performed substantially concurrently, or may be performed in the reverse order to that described.

In the accompanying drawings, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein, but should include variations in shape resulting from, for example, manufacturing processes.

1 is a perspective view showing a partial structure of a semiconductor memory device according to a first embodiment of the present invention.

1, a semiconductor memory device 100 includes a semiconductor substrate 101 having a predetermined lower structure, a plurality of conductive regions 102 and an insulating layer 103, a plurality of first lower electrodes 110 And a plurality of second lower electrodes 120.

A plurality of transistor structures (not shown) constituting unit memory cells together with the plurality of first lower electrodes 110 or the plurality of second lower electrodes 120 are formed in the semiconductor substrate 101, (Not shown) extending in a first direction (X direction in FIG. 1) and a plurality of word lines (not shown) extending in a second direction (Y direction in FIG. 1) Bit lines (not shown) may be formed. Hereinafter, for convenience of description, the plurality of transistor structures, the plurality of word lines, and the structures including the plurality of bit lines are collectively referred to as a lower structure, and a detailed description of the lower structure is omitted. Of the.

A plurality of conductive regions 102 are formed on the semiconductor substrate 101 to connect the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 to corresponding transistor structures of the lower structure. And an insulating layer 103 separating the plurality of conductive regions 102 from each other. An etch stop layer 104 may be formed on the plurality of conductive regions 102 and the insulating layer 103. These will be described in more detail below with reference to Figures 2a and 2b through 7a and 7b.

A plurality of first lower electrodes 110 and a plurality of second lower electrodes 120 may be formed on the etch stop layer 104. The plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 may extend in a row direction orthogonal to each other on a first plane (e.g., an XY plane in FIG. 1) on the etch stop layer 104 , The X direction in FIG. 1) and the column direction (e.g., the Y direction in FIG. 1), so that a matrix shape including a plurality of rows and columns as a whole can be achieved. It is noted that FIG. 1 shows only three rows and columns, respectively, including a first row (Row1) and a first column (Col1) for convenience of illustration.

The plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 pass through the etch stop layer 104 so that the lower surface contacts the plurality of conductive regions 102, And a pillar shape extending in a third direction (Z direction in Fig. 1, the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 each have a predetermined width and extend in the third direction. However, the present invention is not limited thereto. The plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 may have a columnar shape that gradually increases in width in the third direction or extends so that the width gradually decreases. In FIG. 1, the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 have the same vertical length, but are not limited thereto. As will be described later, the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 may have different horizontal cross-sectional shapes from each other. In order to ensure a uniform capacitance, 1 lower electrodes 110 and the plurality of second lower electrodes 120 may have different vertical lengths from each other.

The plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 may have different horizontal cross-sectional shapes. The plurality of first lower electrodes 110 may have a sidewall including a curved outer surface, and the plurality of second lower electrodes 120 may have sidewalls including a curved outer surface. However, the horizontal cross-sectional shapes of the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 may be substantially the same in area to ensure a uniform capacitance.

The plurality of first lower electrodes 110 may have a circular horizontal cross-sectional shape, for example, as shown in FIG. 1, but may have an elliptical cross-sectional shape having long and short axes of different lengths. The plurality of first lower electrodes 110 may have a horizontal cross-sectional shape such as a polygon such as a triangle, a tetragon, a pentagon, or the like. The plurality of second lower electrodes 120 may have, for example, a horizontal cross-sectional shape of a polygon having four vertices as shown in FIG. 1, the plurality of second lower electrodes 120 have curved surfaces concaved from the outer side of the four vertexes connecting adjacent vertexes. However, the present invention is not limited thereto. One surface may have an outer convex surface.

The plurality of first lower electrodes 110 and the plurality of second lower electrodes 120 may be formed of the same conductive material but are not limited thereto and may be formed of different conductive materials.

A dielectric film (not shown) may be formed on the surfaces of the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120, and the plurality of An upper electrode (not shown) facing each of the first lower electrodes 110 and the plurality of second lower electrodes 120 may be formed.

FIGS. 2A and 2B to FIGS. 7A and 7B illustrate an exemplary manufacturing method of the semiconductor memory device 100 (see FIG. 1) according to the first embodiment of the present invention, As shown in the figures, Figures 2A, 3A, ... And FIG. 7A are plan views illustrating planar shapes of some of the components, and FIGS. 2B, 3B,... , And Fig. 7B is a cross-sectional view taken along line II-II of Fig. 2A, Fig. And FIG. 7A is a cross-sectional view illustrating the structure of the AA-AA 'cross section and the AX-AX' cross section of FIG. 7A. In Figs. 2A and 2B to Figs. 7A and 7B, the same reference numerals as those in Fig. 1 denote the same members, and redundant detailed descriptions are omitted for the sake of simplicity.

2A and 2B, a plurality of word lines (not shown), a plurality of bit lines (not shown), and transistor structures (not shown) constituting unit memory cells as described above are formed on a semiconductor substrate 101 0.0 > a < / RTI >

A plurality of conductive regions 102 made of a conductive material and an insulating layer 103 electrically separating the plurality of conductive regions 102 are formed on the lower structure. The plurality of conductive regions 102 may electrically connect a plurality of first lower electrodes 110 and a plurality of second lower electrodes 120 to an active region (not shown) of the transistor structures. In this case, the layers interposed between the plurality of conductive regions 102 and the active regions of the transistor structures may include various contacts, such as buried contacts, such that the plurality of conductive regions 102, The active areas of the structures can be electrically connected.

An etch stop layer 104 is formed to cover the plurality of conductive regions 102 and the insulating layer 103 and a mold layer 140 is sequentially formed on the etch stop layer 104. In some embodiments, the etch stop layer 104 may comprise a silicon nitride film. In some embodiments, the mold layer 140 may comprise a silicon oxide film. However, the materials constituting each of the etch stop layer 104 and the mold layer 140 are not limited to those illustrated above, and may be formed using a single material selected from a variety of materials, Can be used in combination.

2A and 2B, a plurality of first lower electrodes 110 and a plurality of second lower electrodes 120, which are formed in a subsequent process, are formed on the sidewalls of the mold layer 140, A supporter (not shown) layer may be formed to support them so as not to collapse or tilt during the forming process. The supporter layer may be formed of at least two layers that are vertically spaced from each other according to the vertical lengths of the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120.

A hard mask layer (not shown) is formed on the mold layer 140, and then the hard mask layer is patterned using a photolithography process to form a plurality of first holes 150H exposing the etch stop layer 104, . As illustrated in FIG. 2A, the plurality of first holes 150H may be arranged in a row in the X direction and the Y direction, respectively, but may be arranged in a line in a zigzag shape, that is, along the C direction. May be formed corresponding to the positions of the plurality of first lower electrodes 110 to be formed.

In the mold layer 140, a plurality of first holes 150H aligned in a line in a direction C, which is a diagonal direction in FIG. 2A, maintains a first gap D1 between them, A plurality of first holes 150H aligned in a line along the first hole 150H may be arranged to maintain a second spacing D2 therebetween. The first spacing D1 and the second spacing D2 are set so as to secure a distance at which a plurality of second spacers 162 formed in a subsequent process and a plurality of second lower electrodes 120 can be formed, .

The plurality of first holes 150H may have a substantially circular cross-sectional shape in horizontal section. However, the horizontal cross-sectional shape of the plurality of first holes 150H is not limited to that illustrated in FIG. 2A, and may be formed to have various geometric shapes as needed. In some embodiments, the horizontal cross-sectional shape of the plurality of first holes 150H may have any shape selected from a polygonal shape such as a triangular shape, a tetragonal shape, a pentagonal shape, or an elliptical shape.

The plurality of first holes 150H may each have a diameter of a first width W1. The size of the first width W1 is set in consideration of the widths of the plurality of first spacers 161 (see FIGS. 3A and 3B) and the plurality of first lower electrodes 110 formed in the subsequent process . The size of the first width W1 is the same as the size of the plurality of first lower electrodes 110 and the plurality of second lower electrodes 120, Or may be larger than the width of the case in which a plurality of through holes are formed in the mold layer to form a similar density. Accordingly, the photolithography process and the etching process for forming the plurality of first holes 150H can be made easier.

3A and 3B, a plurality of first spacers 161 are formed in the plurality of first holes 150H, and the etch stop layer 104 is removed to form the conductive regions 102 Thereby defining a plurality of first lower electrode regions 110H.

In some embodiments, an insulating film (not shown) is formed to cover the inner walls of the plurality of first holes 150H with a uniform thickness, and then the insulating film covering the upper surfaces of the plurality of first holes The plurality of first spacers 161 having a circular planar shape corresponding to the circular contour of the plurality of first holes 150H can be formed. The plurality of first spacers 161 may be formed of a material having an etch selectivity with the mold layer 140. For example, when the mold layer 140 is formed of a silicon oxide film, the plurality of first spacers 161 may be formed of a silicon nitride film. The etch stop layer 140 may be further etched to remove the etch stop layer 140 after etch back to form the plurality of first spacers 161.

The plurality of first lower electrodes regions 110H may be defined by forming the plurality of first spacers 161 and removing the etch stop layer 140 exposed in the inner region of the plurality of first spacers 161. [ can do. The plurality of first lower electrode regions 110H may have a circular planar shape such as the plurality of first holes 150H and the plurality of first spacers 161. [

The plurality of first lower electrode regions 110H may have a third width W3. The size of the third width W3 may be set considering the width of the conductive regions 102. By adjusting the size of the second width W2 of the plurality of first spacers 161, The size can be determined. For example, as shown in FIG. 3B, when the plurality of first lower electrode regions 110H have a third width W3 corresponding to the size of the conductive regions 102, (161) may be formed to have a width that does not cover the conductive regions (102). When the third width W3 of the first lower electrode regions 110H is smaller than the width of the conductive regions 102, the plurality of first spacers 161 are electrically connected to the conductive regions 102 May be formed to have a width covering a part thereof.

4A and 4B, a plurality of first lower electrodes 110 are formed by filling a plurality of first lower electrode regions 110H with a conductive material, and the mold layer 140 is removed to form a plurality of first spacers 110. [ (Not shown).

In some embodiments, the plurality of first lower electrodes 110 may comprise the conductive material, such as TiN, Ti, TaN, Ta, or combinations thereof. The plurality of first lower electrodes 110 may be formed by depositing the conductive material on the plurality of first lower electrode regions 110a, 120b, and 120c using ALD (atomic layer deposition), CVD (chemical vapor deposition), or PVD 110H, and the upper surface of the mold layer 140, and performing node separation using a CMP process.

After forming the plurality of first lower electrodes 110, the mold layer 110 may be removed, e.g., lifted off, to expose the outer walls of the plurality of first spacers 161, The upper surface of the etch stop layer 104 can be exposed.

5A and 5B, a plurality of second spacers 162 are formed on the outer walls of the plurality of first spacers 161 so as to be in contact with one another, and two adjacent first lower electrodes 110 And a plurality of second lower electrode regions 120H are formed by exposing the conductive region 102 by removing the etch stop layer 140 corresponding to the island shape, define.

In some embodiments, an insulating film (not shown) is formed to cover the outer wall and the upper surface of the plurality of first spacers 161 and the upper surface of the plurality of first lower electrodes 110 to a uniform thickness, The insulating film covering the upper surface of the first spacer 161 and the plurality of first lower electrodes 110 is etched back to form a plurality of the plurality of first spacers 161 having a circular planar shape corresponding to the circular contour of the plurality of first spacers 161 Of the second spacers 162 are formed.

Particularly, the second spacer 162 formed on the outer wall of one first spacer 161 has a size of the fourth width W5 such that the second spacer 162 is in contact with the four second spacers 162 surrounding the first spacer 162, By forming the plurality of second spacers 162 with the island-shaped horizontal cross-sectional shape. The plurality of second lower electrode regions 120H can be defined by removing the etch stop layer 104 exposed in the region having the island shape horizontal cross-sectional shape. The plurality of second lower electrode regions 120H may have a polygonal horizontal cross-sectional shape having four vertices, and may have a horizontal cross-sectional shape having a convex sidewall when viewed from the inside thereof.

The width D2- (2 * W5) of the plurality of second lower electrode regions 120H may be set in consideration of the width of the conductive regions 102, and the plurality of second spacers 162 can be determined by adjusting the size of the fourth width W5. For example, as shown in FIG. 5B, when the plurality of second lower electrode regions 120H have a width corresponding to the size of the conductive regions 102, the plurality of second spacers 162 And may be formed to have a size that does not cover the conductive regions 102. When the width of the plurality of second lower electrode regions 120H is smaller than the width of the conductive regions 102, the plurality of second spacers 162 may have a width covering a part of the conductive regions 102 As shown in FIG.

Referring to FIGS. 6A and 6B, a plurality of second lower electrodes 120 are formed by filling a plurality of second lower electrode regions 120H with a conductive material.

In some embodiments, the plurality of second lower electrodes 120 may be formed of the conductive material, such as TiN, Ti, TaN, Ta, or combinations thereof. The plurality of second lower electrodes 120 may be formed of the same material as the plurality of first lower electrodes 110, or may be formed of materials different from each other. The plurality of second lower electrodes 120 may be formed through a process substantially the same as the process of forming the plurality of first lower electrodes 110 described above.

7A and 7B, a plurality of first spacers 161 and a plurality of second spacers 162 are removed, e.g., lifted off, to form a plurality of first lower electrodes 110 and a plurality of second lower Thereby exposing the outer wall of the electrodes 120. As a result, the upper surface of the etch stop layer 104 is also exposed. As shown in FIG. 1, a plurality of first lower electrodes 110 having a different horizontal cross-sectional shape and a plurality of second lower electrodes 120 may be formed.

As described above, the plurality of first lower electrodes 110 may be formed first and the plurality of first lower electrodes 110 may be formed in a horizontal cross-sectional shape In the case of forming a plurality of second lower electrodes 120 having a horizontal cross-sectional shape different from that of the first lower electrodes 120, And the etching process can be easily performed. Therefore, it is possible to solve the problem of the characteristic change and the reliability reduction of the semiconductor memory device due to the technical limitations of the processes.

8 is a perspective view showing a part of the structure of the semiconductor memory device 200 according to the second embodiment of the present invention. FIG. 8 shows a semiconductor memory device 200 having lower electrodes having three different horizontal cross-sectional shapes, unlike the semiconductor memory device 100 according to the first embodiment of FIG. 8, a semiconductor substrate 201, a plurality of conductive regions 202 and an insulating layer 203, a etch stop layer 204, a plurality of first lower electrodes 210, Since the electrodes 220 are substantially the same as those shown in FIG. 1, a detailed description thereof will be omitted and differences will be mainly described.

A plurality of first lower electrodes 210, a plurality of second lower electrodes 220, and a plurality of third lower electrodes 230 may be formed on the etch stop layer 204. The plurality of first to third lower electrodes 210, 220 and 230 may extend in a row direction orthogonal to each other on a first plane (e.g., an XY plane in FIG. 8) on the etch stop layer 204 (E.g., the X direction in FIG. 8) and the column direction (e.g., the Y direction in FIG. 8) so as to have a matrix shape including a plurality of rows and columns as a whole. Specifically, in the first row (Row1) and the first column (Col1), the plurality of first lower electrodes 210 and the plurality of second lower electrodes 220 may be alternately arranged one by one (Row2) adjacent to the first row (Row1) and a second column (Col2) adjacent to the first column (Col1), the plurality of second lower electrodes (220) and the plurality The third lower electrodes 230 may be alternately arranged one by one. In FIG. 8, for convenience of illustration, only five rows and columns are shown including the first and second rows (Row1, Row2), the first and second columns (Col1, Col2), but are not limited thereto .

The plurality of third lower electrodes 230 each penetrate the etch stop layer 204 and are in contact with the plurality of conductive regions 202 and extend from the plurality of conductive regions 202 in a third direction (Z direction in Fig. 8). 8 illustrates an example in which the third lower electrodes 230 have a predetermined width and extend in the third direction. However, the present invention is not limited thereto. The plurality of third lower electrodes 230 may have a columnar shape that gradually increases in width in the third direction or extends so that the width gradually decreases. 8, the plurality of third lower electrodes 230 are shown to have the same vertical length as the plurality of first and second lower electrodes 210 and 220, but the present invention is not limited thereto. As described later, the plurality of third lower electrodes 230 may have a horizontal cross-sectional shape different from that of the plurality of first and second lower electrodes 210 and 220, thereby ensuring a uniform electrostatic capacity Or may have a different vertical length from the plurality of first lower electrodes 210 and / or the plurality of second lower electrodes 220.

The plurality of third lower electrodes 230 may have a horizontal cross-sectional shape different from that of the plurality of first and second lower electrodes 210 and 220. The plurality of third lower electrodes 230 may have sidewalls including concave curved surfaces like the plurality of second lower electrodes 220. However, the plurality of third lower electrodes 230 may have a horizontal cross-section of the plurality of second lower electrodes 220 The direction of the line E1 connecting the opposite vertexes of the third lower electrodes 230 may be different from the direction of the line E2 connecting the vertexes of the third lower electrodes 230 that face each other. The horizontal cross-sectional shapes of the plurality of third lower electrodes 230 may be substantially equal to the area of the horizontal cross-sectional shapes of the first and second lower electrodes 210 and 220 for securing a uniform capacitance. Can be the same.

8, the third lower electrodes 230 may have a horizontal cross-sectional shape of a polygon having four vertices, and connect neighboring vertexes of the four vertices At least one of the faces may have an outer convex curved surface.

The plurality of third lower electrodes 230 may be formed of the same conductive material as the plurality of first lower electrodes 210 and / or the plurality of second lower electrodes 220, .

FIGS. 9 to 15 are diagrams illustrating the exemplary manufacturing method of the semiconductor memory device 200 according to the second embodiment of the present invention. Referring to FIGS. 9 to 15, Fig. 2B, 3B, ... And the cross-sectional structure of the semiconductor memory device 200 corresponding to the plan view shown in Figs. 9 to 15 through the cross-sections shown in Fig. 7B can be easily understood, so that detailed illustration of the cross-sectional structure is omitted . In Figs. 9 to 15, the same reference numerals as in Fig. 8 denote the same members, and redundant detailed descriptions are omitted for the sake of simplicity. For the sake of simplicity, the detailed description overlapping with the drawings shown in Figs. 2A and 2B to Figs. 7A and 7B will be omitted and the differences will be mainly described.

Referring to FIG. 9, a plurality of conductive regions and an insulating layer, an etch stop layer 204, and a mold layer 240 are sequentially formed on a semiconductor substrate having a predetermined substructure formed thereon.

A plurality of first holes 250H exposing the etch stop layer 204 by patterning the hard mask layer using a photolithography process after a hard mask layer (not shown) is formed on the mold layer 240, . As illustrated in FIG. 9, the plurality of first holes 250H may be arranged in a row in the X direction and the Y direction orthogonal to each other to form a matrix, and a plurality of first sub- And may be formed corresponding to the positions of the electrodes 210.

In the mold layer 240, the plurality of first holes 250H aligned in a row along the X direction in FIG. 9 are spaced apart from each other by a third interval D3 between them, The plurality of first holes 250H aligned may be arranged to maintain a fourth spacing D4 therebetween. The third spacing D3 and the fourth spacing D4 correspond to a plurality of second spacers 262 (see FIG. 12) and a plurality of third lower electrodes 230 ) Can be formed. The plurality of first holes 150H may have a substantially circular shape in horizontal cross section, but is not limited thereto, and may have a diameter of a fifth width W5. The size of the fifth width W5 may be set to be the same or similar density as the plurality of first to third lower electrodes 210, 220, and 230, The width of the mold layer may be larger than that of the case of forming a plurality of through holes in the mold layer. Accordingly, the photolithography process and the etching process for forming the plurality of first holes 250H can be made easier.

Referring to FIG. 10, a plurality of first spacers 261, each having a size of a sixth width W6, are formed in the plurality of first holes 250H, and the etch stop layer 204 And exposes the conductive region 202 to define a plurality of first lower electrode regions 210H. The plurality of first spacers 261 may have a circular planar shape corresponding to the circular contour of the plurality of first holes 250H, and similarly, the plurality of first lower electrode regions 210H may have a seventh width And a circular shape having a diameter of the wobbles W7 may have a first horizontal cross-sectional shape.

Referring to FIG. 11, a plurality of first lower electrodes 210 are formed by filling a plurality of first lower electrode regions 210H with a conductive material, and the mold layer 140 is lifted off to form a plurality of first spacers 261 And the etch stop layer 204 are exposed.

Referring to FIG. 12, a plurality of second spacers 262 are formed on the outer walls of the plurality of first spacers 261 so as to be in contact with one another, so that two second spacers 262 are formed between two neighboring first lower electrodes 210 A plurality of third lower electrode regions 230H are defined by defining an isolated island shape and exposing the conductive region 202 by removing the etch stop layer 204 corresponding to the island shape.

Specifically, the second spacers 262 formed on the outer wall of one first spacer 261 are spaced apart from each other by an eighth width (" W8, the second horizontal spacers 262 can be defined to define a third horizontal cross-sectional shape of an isolated island shape. Accordingly, the third lower electrode regions 230H have four vertexes in the third horizontal cross-sectional shape, and have a concave sidewall when viewed from the inside thereof, and a line connecting opposing vertexes of the four vertexes And may have a horizontal cross-sectional shape corresponding to the X direction or the Y direction.

Referring to FIG. 13, a plurality of third lower electrode regions 230 are formed by filling a plurality of third lower electrode regions 230H with a conductive material, and a plurality of first and second spacers 261 and 262 The upper surfaces of the plurality of first lower electrodes 210, the outer walls of the third lower electrodes 230, and the upper surface of the etch stop layer 204 are exposed.

Referring to FIG. 14, a plurality of third spacers 263 are formed on outer side walls of a plurality of first lower electrodes 210 and a plurality of third lower electrodes 230, An isolated island shape is defined between two first lower electrodes 210 that are adjacent to each other and between two neighboring third lower electrodes 230, and an etch stop layer 204 in a region corresponding to the island shape is removed Thereby defining a plurality of second lower electrode regions 220H by exposing the conductive region 202. [

Specifically, the third spacers 263 formed on the outer wall of one first lower electrode 210 may have a ninth width W9 such that the third spacers 263 are in contact with each other, , The second horizontal cross-sectional shape of the isolated islands can be defined. As a result, the plurality of second lower electrode regions 220H have four vertexes, like the third horizontal cross-sectional shape described above, and have concave sidewalls when viewed from the inside thereof, but the vertexes of the four vertexes And a second horizontal cross-sectional shape different from the third horizontal cross-sectional shape at a point where a line extending in the x-direction and a y-direction intersecting the oblique direction.

Referring to FIG. 15, a plurality of third spacers 263 are lifted off to expose the upper surface of the etch stop layer 204 and the outer walls of the first to third lower electrodes 210, 220, and 230. Accordingly, as shown in FIG. 8, the plurality of first to third lower electrodes 210, 220, 230 having different horizontal cross-sectional shapes may be formed.

In this manner, a plurality of first lower electrodes 210 are formed, and a plurality of third lower electrodes 230 having different horizontal cross-sectional shapes by a self-aligning method using the pattern of the plurality of first lower electrodes 210, And a plurality of second lower electrodes 220 having another horizontal cross-sectional shape are formed by a self-aligning method using the patterns of the first and third lower electrodes 210 and 230 again The photolithography process and the etching process can be easily performed even if the number of design rules is reduced compared with the case where a plurality of lower electrodes having the same horizontal cross-sectional shape are formed through one mask. Therefore, It is possible to solve the problem of characteristic change and reliability degradation.

16 is a perspective view showing a part of the structure of the semiconductor memory device 300 according to the third embodiment of the present invention. 16 is a cross-sectional view of a semiconductor memory device 300 having two types of lower electrodes having different horizontal cross-sectional shapes as in the semiconductor memory device 100 according to the first embodiment of FIG. 1, Fig. 16, the semiconductor substrate 301, the plurality of conductive regions 302 and the insulating layer 303, the etch stop layer 304, and the plurality of first lower electrodes 310 are formed in the structure shown in FIG. 1 Therefore, a detailed description thereof will be omitted, and differences will be mainly described.

Referring to FIG. 16, a plurality of first lower electrodes 310 and a plurality of second lower electrodes 320 may be formed on the etch stop layer 304. The plurality of first and second lower electrodes 310 and 320 may be formed in at least one direction (for example, denoted by P1 and P2) on a first plane (for example, an XY plane in FIG. 16) on the etch stop layer 304 One first lower electrode 310 and two second lower electrodes 320 may alternately be arranged along one direction. 16, only the directions indicated by P1 and P2 are shown for convenience of illustration, but the present invention is not limited thereto.

The second lower electrodes 320 may have a sidewall including a curved outer surface, and may have a horizontal cross-sectional shape of a polygon having three vertexes. The second lower electrodes 320 may have at least one surface of the three vertexes connecting the neighboring vertexes with a convex surface that is convex from the outside.

17 to 21 are diagrams illustrating the exemplary manufacturing method of the semiconductor memory device 300 according to the third embodiment of the present invention. Referring to FIGS. 17 to 21, Fig. 2B, 3B, ... And the sectional views of the semiconductor memory device 300 corresponding to the plan views shown in FIGS. 17 to 21 through the illustrated cross-sections of FIG. 7B are easily understood, so that detailed illustration of the cross-sectional configuration is omitted. In Figs. 17 to 21, the same reference numerals as those in Fig. 16 denote the same members, and redundant detailed descriptions are omitted for the sake of simplicity. For the sake of simplicity, the detailed description overlapping with the drawings shown in Figs. 2A and 2B to Figs. 7A and 7B will be omitted and the differences will be mainly described.

17, a plurality of conductive regions and an insulating layer, an etch stop layer 304, and a mold layer 340 are sequentially formed on a semiconductor substrate on which a predetermined substructure is formed, and the mold layer 340, A plurality of first holes 350H are formed to expose the etch stop layer 304. Referring to FIG. As illustrated in FIG. 17, the plurality of first holes 350H may be arranged to form a honeycomb shape. In detail, the plurality of first holes 350H arranged in a line in the X direction, the Y direction, or the C direction on the mold layer 340 are arranged to maintain a fifth interval D5 therebetween . The plurality of first holes 350H may have a substantially circular cross-sectional shape in a horizontal section, but is not limited thereto and may have a diameter of a tenth width W10. The size of the tenth width W10 is determined by forming lower electrodes having the same horizontal cross-sectional shape in a limited area as described below at the same or similar density as the first and second lower electrodes 310 and 320 , It may be larger than the width of the case where a plurality of through holes are formed in the mold layer. Accordingly, the photolithography process and the etching process for forming the plurality of first holes 350H can be made easier.

Referring to FIG. 18, a plurality of first spacers 361, each positioned within the plurality of first holes 350H and having a size of the eleventh width W11, are formed, and the etch stop layer 304 And exposes the conductive region 302 to define a plurality of first lower electrode regions 310H.

The plurality of first spacers 361 may have a circular planar shape corresponding to the circular contour of the plurality of first holes 350H and the plurality of first lower electrode regions 310H may have a circular planar shape corresponding to the 11th width The circular shape having the diameter of the wedge W11 may have a horizontal cross-sectional shape.

Referring to FIG. 19, a plurality of first lower electrodes 310 are formed by filling a plurality of first lower electrode regions 310H with a conductive material, and the mold layer 340 is lifted off to form a plurality of first spacers 361 And the etch stop layer 304 are exposed.

Referring to FIG. 20, a plurality of second spacers 362 are formed on the outer wall of the plurality of first spacers 361 so as to be in contact with one another, and are disposed between two neighboring first lower electrodes 310 A plurality of second lower electrode regions 320H are defined by defining an isolated island shape and exposing the conductive region 302 by removing the etch stop layer 304 corresponding to the island shape.

In detail, the second spacers 362 formed on the outer wall of one of the first spacers 361 are spaced apart from each other by a third width W13), the isolated island-shaped horizontal cross-sectional shape can be defined by forming the plurality of second spacers 362 having a size of W13. Accordingly, the plurality of second lower electrode regions 320H have three vertexes, and may have a horizontal cross-sectional shape having concave sidewalls when viewed from the inside.

Referring to FIG. 21, a plurality of second lower electrodes 320 are formed by filling a plurality of second lower electrode regions 320H with a conductive material, and a plurality of first and second spacers 361 and 362 are lifted off To expose the plurality of first lower electrodes 310, the outer walls of the plurality of second lower electrodes 310, and the upper surface of the etch stop layer 304. Accordingly, as shown in FIG. 16, the first and second lower electrodes 310 and 320 having a columnar shape having different horizontal cross-sectional shapes can be formed.

According to the above embodiments, the density of the lower electrode can be doubled by the self-alignment method. Therefore, even if the design rule is reduced, the photolithography process and the etching process are easy, The problem of degradation can be solved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100, 200, 300: semiconductor memory device

Claims (10)

A plurality of first and second lower electrodes,
Wherein the plurality of first and second lower electrodes have different horizontal cross-sectional shapes from each other. The method according to claim 1,
Wherein the plurality of first and second lower electrodes are alternately arranged one by one in the row direction and the column direction on the first plane to form a matrix shape. The method according to claim 1,
Wherein the horizontal cross-sectional shape of the plurality of first lower electrodes has a convex curved surface on the outside,
Wherein the horizontal cross-sectional shape of the plurality of second lower electrodes has at least four vertexes and a curved surface concaved from the outside. The method according to claim 1,
And a plurality of third lower electrodes positioned on the same plane as the plurality of first and second lower electrodes,
Wherein the plurality of third lower electrodes have a different horizontal cross-sectional shape from the plurality of first and second lower electrodes. 5. The method of claim 4,
The plurality of first to third lower electrodes are arranged in a row direction and a column direction on a first plane to form a matrix,
In the first row and the first column, the plurality of first and second lower electrodes are arranged alternately one by one, and in the second row adjacent to the first row and the second row adjacent to the first row, And a plurality of second and third lower electrodes are alternately arranged one by one. 5. The method of claim 4,
Wherein the horizontal cross-sectional shape of the plurality of first lower electrodes has a convex curved surface on the outside,
Wherein a horizontal cross-sectional shape of the second and third lower electrodes has at least four vertexes, respectively, and a concave curved surface at an outer side thereof, and directions of lines connecting opposite vertices are different from each other. The method according to claim 1,
Wherein the first lower electrode and the second lower electrode are alternately arranged in the row direction and the column direction, respectively. 8. The method of claim 7,
Wherein the horizontal cross-sectional shape of the plurality of first lower electrodes has a convex curved surface on the outside,
Wherein a horizontal cross-sectional shape of the plurality of second lower electrodes has at least three vertices and an outer concave curved surface. Forming a plurality of first holes in a mold layer on a substrate having a plurality of conductive regions, penetrating the mold layer and forming rows and columns on a first plane;
Defining a plurality of first lower electrode regions having a first horizontal cross-sectional shape by forming a plurality of first spacers on inner walls of each of the plurality of first holes and exposing the conductive regions;
Filling the plurality of first lower electrode regions with a conductive material to form a plurality of first lower electrodes;
Exposing an outer wall of the plurality of first spacers by removing the mold layer;
A plurality of second spacers formed on an outer wall of the plurality of first spacers, wherein adjacent second spacers are in contact with each other, and exposing the conductive regions to form a plurality of second lower electrodes Defining regions; And
Filling the plurality of second lower electrode regions with a conductive material to form a plurality of second lower electrodes;
And forming a gate insulating film on the semiconductor substrate. 10. The method of claim 9,
Exposing an outer wall of the plurality of first and second lower electrodes by removing the plurality of first and second spacers;
Forming a plurality of third spacers on an outer wall of the plurality of first and second lower electrodes such that adjacent ones of the plurality of third spacers are in contact with each other, exposing the conductive regions to form a plurality of Forming third lower electrode regions; And
Filling the plurality of third lower electrode regions with a conductive material to form a plurality of third lower electrodes;
Further comprising a step of forming a gate electrode on the semiconductor substrate.

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