KR20140086588A - Phase detector circuit - Google Patents

Abstract

The present invention relates to a phase detection circuit which is used to detect the phase of a clock signal. The phase detection circuit includes first and second edge latching units which detect and latch the comparison subject edge of a first clock signal and the comparison subject edge of a second clock signal respectively; and a phase information generating unit which generates the phase information of the comparison subject edges in response to the output signals from the first and second edge latching units.

Description

[0001] PHASE DETECTOR CIRCUIT [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly to a phase detection circuit for detecting the phase of a clock signal.

Generally, a semiconductor device including a DDR SDRAM (Double Data Rate Synchronous DRAM) receives an external clock signal, generates an internal clock signal, and uses the internal clock signal as a reference for adjusting the operation timing of the internal circuit. Thus, an internal clock signal generating circuit for generating an internal clock signal is provided in the semiconductor device. The internal clock signal generation circuit typically includes a phase locked loop (PLL) and a delay locked loop (DLL).

Since the configuration and operation of the phase locked loop and the delay locked loop are well known, a detailed description thereof will be omitted. Hereinafter, an internal clock signal generating circuit such as a phase locked loop and a delay locked loop generates a basic clock signal Will be briefly described.

The internal clock signal generating circuit receives a clock signal as a reference (hereinafter, referred to as a reference clock signal) and generates an internal clock signal having a phase corresponding to the reference clock signal. In the case of the internal clock signal which is initially generated, since most of the internal clock signals do not have a phase corresponding to the reference clock signal, a locking operation is performed. Here, the locking operation means an operation of adjusting the phase of the internal clock signal to a phase corresponding to the reference clock signal. In order to perform the locking operation, the internal clock signal generation circuit includes a detection operation for comparing the phases of the internal clock signal and the reference clock signal and detecting the result, and a control operation for adjusting the phase of the internal clock signal according to the detection result . The internal clock signal generation circuit must have a detection circuit and an adjustment circuit for this operation. For convenience of explanation, the internal clock signal input to the detection circuit is hereinafter referred to as a feedback clock signal.

1 and 2 are operation waveforms for explaining a general locking operation, and FIG. 1 is an operation waveform diagram for performing a normal locking operation.

In FIG. 1, the phase detection signal DET is detected by comparing the phase difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED, and the phase difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED.

As shown in the figure, the phase detection signal DET maintains logic 'high' when the phase of the reference clock signal CLK_REF is ahead of the phase of the feedback clock signal CLK_FED and the reference clock signal CLK_REF, Quot; low " when the phase of the feedback clock signal CLK_FED is behind the phase of the feedback clock signal CLK_FED.

As described above, the locking operation of the internal clock signal compares and detects the phase of the reference clock signal CLK_REF and the feedback clock signal CLK_FED, and adjusts the phase of the internal clock signal according to the result. Here, the internal clock signal corresponds to the feedback clock signal CLK_FED, and thus the phase of the feedback clock signal CLK_FED is adjusted through the locking operation. The phase of the reference clock signal CLK_REF and the phase of the feedback clock signal CLK_FED become substantially the same when the phase detection signal DET transits from the logic low to the logic high. It is time to complete.

2 is an operation waveform diagram when an abnormal locking operation is performed.

2, the reference clock signal CLK_REF, the feedback clock signal CLK_FED and the phase detection signal DET are started, and the reference clock signal CLK_REF and the feedback clock signal CLK_FED are jittered, Or the duty is changed.

As shown in the figure, when the phase of the reference clock signal CLK_REF and the phase of the feedback clock signal CLK_FED are undesirably changed, the phase detection signal DET is detected at the falling edge of the reference clock signal CLK_REF Transition from logic 'low' to logic 'high'. The transition point of the phase detection signal DET means the locking point, and such a wrong locking point of the phase detection signal DET causes a malfunction in all the circuits using the phase detection signal DET.

And to provide a phase detection circuit capable of detecting a phase by latching a predetermined comparison target edge of each of a clock signal serving as a comparison reference and a clock signal to be compared.

A phase detection circuit according to an embodiment of the present invention includes first and second edge latching units for detecting and latching a comparison target edge of a first clock signal and a comparison target edge of a second clock signal, respectively; And a phase information generator for generating phase information of the edge to be compared in response to an output signal of the first and second edge latching units.

The apparatus may further include a reset control unit for controlling a reset operation of the first and second edge latching units after a predetermined time at the time when the phase information is activated.

The internal clock signal generating circuit according to another embodiment of the present invention includes a phase detector for detecting phase information of a comparison target edge among the first and second edges of the reference clock signal and the feedback clock signal, ; And a clock adjusting unit for adjusting the reference clock signal to generate the feedback clock signal corresponding to the output signal of the phase detecting unit.

Preferably, the phase detector may generate an output signal corresponding to at least three states: a case where the phase of the reference clock signal precedes the phase of the feedback clock signal, .

According to another aspect of the present invention, there is provided a semiconductor device including: a phase detector for detecting phase information of an edge to be compared by detecting an edge to be compared among first and second edges of each of first and second clock signals; A locking detector for detecting locking information in response to an output signal of the phase detector; And a locking operation unit for performing a predetermined operation in response to the locking information.

Preferably, the locking information is activated when the second detection signal is activated after the first detection signal is activated.

The phase detection circuit according to the embodiment of the present invention is capable of detecting phase by latching a predetermined comparison target edge of each of a clock signal as a reference for comparison and a clock signal to be compared. Furthermore, it is possible to stably detect the completion time of the locking operation based on the phase detection result. In addition, it is possible to efficiently control the operation of the internal clock signal generation circuit based on the result of the phase detection.

It is possible to obtain an effect of securing phase information corresponding to a predetermined comparison target edge even if a jitter or a duty change occurs in the clock signal.

In addition, it is possible to generate accurate locking information and to ensure the stable operation of other circuits provided with the same.

In addition, unnecessary power consumption can be reduced and an erroneous operation can be prevented in generating an internal clock signal.

1 and 2 are operation waveform diagrams for explaining a general locking operation.
3 is a circuit diagram for explaining a phase detection circuit according to an embodiment of the present invention.
4 is a circuit diagram for illustrating a reset control section for generating the enable signal EN of FIG.
Figs. 5 to 7 are operation waveform diagrams for explaining the circuit operation of Figs. 3 and 4. Fig.
8 is a block diagram for explaining a semiconductor device and an internal clock signal generation circuit including the phase detector of FIG.
9 is a circuit diagram for explaining the locking detection unit 830 of FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

3 is a circuit diagram for explaining a phase detection circuit according to an embodiment of the present invention.

Referring to FIG. 3, the phase detection circuit includes a first edge latching unit 310, a second edge latching unit 320, and a phase information generating unit 330.

The first edge latching unit 310 detects and latches the rising edge of the reference clock signal CLK_REF and the edge to be compared of the polling edge and the second edge latching unit 320 latches the rising edge of the feedback clock signal CLK_FED The comparing target edge is also detected and latched during the polling edge. Hereinafter, for convenience of explanation, it is assumed that each of the first and second edge latching units 310 and 320 detects and latches the rising edge of the reference clock signal CLK_REF and the rising edge of the feedback clock signal CLK_FED Each of the first and second edge latching units 310 and 320 is implemented as a D-Flip Flop that outputs a signal input to the input terminal D in response to a corresponding clock signal as an output terminal Q. . Here, the reset operation is controlled in response to the enable signal EN in the de-flip flop. The reset control unit for generating the enable signal EN will be described with reference to FIG.

In response to the output signals of the first and second edge latching units 310 and 320, the phase information generating unit 330 generates the phase of the rising edge of the reference clock signal CLK_REF and the rising edge of the feedback clock signal CLK_FED And outputs information to the first and second phase detection signals DET1 and DET2. Here, the first phase detection signal DET1 is activated when the rising edge of the reference clock signal CLK_REF precedes the rising edge of the feedback clock signal CLK_FED, and the second phase detection signal DET2 is activated when the reference clock signal CLK_REF Is behind the rising edge of the feedback clock signal CLK_FED. The rising edge of the reference clock signal CLK_REF and the rising edge of the feedback clock signal CLK_FED have the same phase as that of the reference clock signal CLK_REF, The first and second phase detection signals DET1 and DET2 maintain a logic 'low' state.

4 is a circuit diagram for illustrating a reset control section for generating the enable signal EN of FIG.

Referring to FIG. 4, the reset control unit includes first and second shifting units 410 and 420, an initial activation control unit 430, and an enable signal output unit 440.

The first shifting unit 410 is for deactivating the enable signal EN after a predetermined period of time after the first phase detection signal DET1 which is the phase information of the reference clock signal CLK_REF is activated, A flip-flop 411 which is reset in response to the signal DET1 and receives the feedback clock signal CLK_FED at the clock terminal CK, and a reset clock signal CLK_FED which is reset in response to the reset signal RSTB And a de-flip flop 412 receiving the output signal G1 of the previous stage of the de-flip-flop 411 and receiving the output signal G1 of the de-flip flop 411 as a clock signal CK.

The second shifting unit 420 is for deactivating the enable signal EN after a predetermined time since the second phase detection signal DET2, which is phase information of the feedback clock signal CLK_FED, Flip flop 421 which is reset in response to the signal DET2 and receives the reference clock signal CLK_REF at the clock terminal CK and a reset signal RSTB which is reset in response to the reset signal RSTB and outputs the reference clock signal CLK_REF And a de-flip flop 422 receiving the output signal D1 from the previous stage of the de-flip flop 421 and receiving the output signal D1 from the clock stage CK.

The initial activation control unit 430 is for a stable comparison operation of the rising edge of the reference clock signal CLK_REF and the rising edge of the feedback clock signal CLK_FED and is reset in response to the reset signal RSTB and is supplied with the feedback clock signal CLK_FED, And a de-flip flop 431 receiving a signal obtained by inverting the clock signal CK.

The enable signal output unit 440 outputs the output signal G2 of the first shifting unit 410, the output signal D2 of the second shifting unit 420, and the output of the initial activation control unit 430 And generates the enable signal EN in response to the signal.

FIGS. 5 to 7 are operation waveforms for explaining the circuit operation of FIGS. 3 and 4. FIG. 5 shows a case where the rising edge of the reference clock signal CLK_REF precedes the rising edge of the feedback clock signal CLK_FED.

Referring to FIGS. 2, 3 and 5, first, the D-flip flops 412, 422 and 431 receiving the reset signal RSTB in the interval in which the reset signal RSTB is logic 'low' are reset. Then, when the reset signal RSTB becomes logic 'high', the enable signal EN transits from logic 'low' to logic 'high' in response to the polling edge of the feedback clock signal CLK_FED. The first and second edge latching units 310 and 320 detect and latch the phase of the reference clock signal CLK_REF and the feedback clock signal CLK_FED in response to the enable signal EN, Generates the first and second phase detection signals DET1 and DET2 in response to the output signals of the first and second edge latching units 310 and 320. [ Here, since the rising edge of the reference clock signal CLK_REF precedes the rising edge of the feedback clock signal CLK_FED, the first phase detection signal DET1 transitions from logic 'low' to logic 'high' Lt; RTI ID = 0.0 > DET2 < / RTI >

On the other hand, when the first phase detection signal DET1 transits to logic 'high', the de-flip flop 411 receiving the first phase detection signal DET1 outputs a logic 'high' in response to the feedback clock signal CLK_FED And the output signal G1 is output (G2) in response to the feedback clock signal CLK_FED at the subsequent stage of the de-flip flop 412. [ The enable signal EN then transitions from logic 'high' to logic 'low' in response to this output signal G2, and in response to this enable signal EN, the first edge latching section 310 So that the first phase detection signal DET1 transits from logic 'high' to logic 'low'.

6 shows a case where the rising edge of the reference clock signal CLK_REF is behind the rising edge of the feedback clock signal CLK_FED. Since the circuit operation of FIG. 6 is similar to the circuit operation of FIG. 5, a detailed description will be omitted.

In FIG. 6, since the rising edge of the reference clock signal CLK_REF is behind the rising edge of the feedback clock signal CLK_FED, the second phase detection signal DET2 replaces the first phase detection signal DET1, Section.

7 shows a case where the rising edge of the reference clock signal CLK_REF is behind the rising edge of the feedback clock signal CLK_FED and then precedes the rising edge of the reference clock signal CLK_REF. Since the circuit operation of Fig. 7 is a combination of the circuit operations of Figs. 5 and 6, a detailed description thereof will be omitted. For reference, there may be a case where the relationship between the reference clock signal CLK_REF and the feedback clock signal CLK_FED is opposite to that of FIG. 7. Since the circuit operation is also a combination of the circuit operations of FIGS. 5 and 6, A detailed description will be omitted.

The phase detection circuit according to the embodiment of the present invention detects and latches the rising edge of the reference clock signal CLK_REF and the rising edge of the feedback clock signal CLK_FED and outputs the first and second phase detection signals DET1 and DET2 ). In other words, the phase detection circuit according to the embodiment of the present invention ignores the phase relationship between the reference clock signal CLK_REF and the polling edge of the feedback clock signal CLK_FED. Therefore, even if jitter occurs in the reference clock signal CLK_REF and the feedback clock signal CLK_FED or the duty changes, the phase relationship of the polling edge of the reference clock signal CLK_REF can be detected by the first and second phase detection It does not affect the signals DET1 and DET2.

8 is a block diagram for explaining a semiconductor device and an internal clock signal generation circuit including the phase detector of FIG.

8 includes internal clock signal generation circuits 810 and 820 including a phase detector 810 and a clock controller 820, a phase detector 810, a locking detector 830, and a locking controller 840 Semiconductor devices 810, 830 and 840 are shown. Here, the phase detector 810 has the configuration shown in FIG. 3 and has the operation waveforms shown in FIGS. 5 to 7. FIG.

First, the internal clock signal generating circuits 810 and 820 include a phase detecting unit 810 and a clock adjusting unit 820. The clock regulator 820 generates the feedback clock signal CLK_FED corresponding to the internal clock signal in response to the first and second phase detection signals DET1 and DET2 output from the phase detector 810 , A circuit such as a delay locked loop and a phase locked loop. For example, in the case of a delay locked loop, the delay amount of the reference clock signal CLK_REF is adjusted in response to the first and second phase detection signals DET1 and DET2 to be output as the feedback clock signal CLK_FED, And adjusts the frequency of the reference clock signal CLK_REF in response to the first and second phase detection signals DET1 and DET2 to output the feedback clock signal CLK_FED.

The phase detector 810 according to the embodiment of the present invention generates the first and second detection signals DET1 and DET2 of three states according to the phases of the reference clock signal CLK_REF and the feedback clock signal CLK_FED . Therefore, the clock adjusting unit 820 also controls the reference clock signal CLK_REF to be higher than the phase of the feedback clock signal CLK_FED according to the first and second detection signals DET1 and DET2, It is possible to additionally control to maintain the same state as the previous state. In particular, when the same state is maintained, it means that unnecessary power consumption can be reduced because the recently generated feedback clock signal CLK_FED is used as it is. For reference, a malfunction such as a bang-bang jitter may occur in an existing configuration, but it is possible to prevent such malfunction in the embodiment of the present invention.

Next, the semiconductor devices 810, 830, and 840 include a phase detector 810, a locking detector 830, and a locking unit 840. The locking detector 830 is for detecting the locking information INF_LOC in response to the first and second phase detection signals DET1 and DET2 output from the phase detector 810, . The locking operation unit 840 is for performing a predetermined circuit operation in response to the locking information INF_LOC, and corresponds to various internal circuits provided with the locking information INF_LOC.

9 is a circuit diagram for explaining the locking detection unit 830 of FIG.

9, the locking detecting unit 830 includes a first latching unit 910 for latching whether the second phase detecting signal DET2 is activated, and a second latching unit 910 for latching the activation And a second latching unit 920 latching the activation of the first phase detection signal DET1 and outputting the locking information INF_LOC.

Hereinafter, a simple circuit operation of the locking detection unit 830 will be described.

The first phase detection signal DET1 is activated when the phase of the reference clock signal CLK_REF is higher than the phase of the feedback clock signal CLK_FED and the second phase detection signal DET2 is activated when the phase of the reference clock signal CLK_FED is higher than the phase of the feedback clock signal CLK_FED. It is activated when the phase is ahead of the phase of the reference clock signal CLK_REF. Accordingly, the first latching unit 910 performs a latching operation when the phase of the feedback clock signal CLK_FED is ahead of the phase of the reference clock signal CLK_REF, and the second latching unit 920 latches the first latching unit 910 In the case where the phase of the reference clock signal CLK_REF is ahead of the phase of the feedback clock signal CLK_FED. In the case of the second latching unit 920, the latched signal is output to the locking information INF_LOC.

The semiconductor device according to the embodiment of the present invention can generate the locking information INF_LOC using the first and second phase detection signals DET1 and DET2. In the case of the thus generated locking information INF_LOC, Duty changes are also guaranteed to ensure stable locking.

9, when the second phase detection signal DET2 is activated and then the first phase detection signal DET1 is activated, the locking information INF_LOC is activated. However, according to the design, the first phase detection signal DET1 It may be possible to activate first.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, the logic gates and transistors exemplified in the above-described embodiments must be implemented in different positions and types according to the polarity of input signals.

310: first edge latching portion
320: Second edge latching part
330: phase information generating unit

Claims (15)

First and second edge latching sections for respectively detecting and latching a comparison target edge of a first clock signal and a comparison target edge of a second clock signal; And
A phase information generating unit for generating phase information of the edge to be compared in response to an output signal of the first and second edge latching units,
And a phase detection circuit.
The method according to claim 1,
And a reset control unit for controlling a reset operation of the first and second edge latching units after a predetermined time at the time when the phase information is activated.
The method according to claim 1,
Wherein the phase information generating section generates an output signal corresponding to at least three states in accordance with output signals of the first and second edge latching sections.
A phase detector for detecting phase information of the comparison target by detecting a comparison target edge among the first and second edges of the reference clock signal and the feedback clock signal, respectively; And
A clock adjusting unit for adjusting the reference clock signal by an amount corresponding to the output signal of the phase detecting unit to generate the feedback clock signal,
And an internal clock signal generating circuit.
5. The method of claim 4,
Wherein the clock adjusting unit adjusts a frequency or a delay amount of the reference clock signal to generate the feedback clock signal.
5. The method of claim 4,
Wherein the phase detector generates an output signal corresponding to at least three states of when the phase of the reference clock signal precedes, is behind, and is equal to that of the feedback clock signal. . 5. The method of claim 4,
Wherein the clock adjusting unit controls the phase of the reference clock signal to be higher than the phase of the feedback clock signal in accordance with the output signal of the phase detector, Clock signal generation circuit.
5. The method of claim 4,
Wherein the phase detector comprises:
A first edge latching unit for detecting and latching an edge corresponding to the compared edge among the first and second edges of the reference clock signal;
A second edge latching unit for detecting and latching an edge corresponding to the compared edge among the first and second edges of the feedback clock signal; And
And a phase information generating unit for generating phase information of the edge to be compared in response to an output signal of the first and second edge latching units.
9. The method of claim 8,
And a reset control unit for controlling a reset operation of the first and second edge latching units after a predetermined time at a time point when the phase information is activated.
9. The method of claim 8,
Wherein the phase information generation unit generates an output signal corresponding to at least three states in accordance with output signals of the first and second edge latching units.
A phase detector for detecting phase information of the edge to be compared by detecting an edge to be compared among the first and second edges of the first and second clock signals, respectively;
A locking detector for detecting locking information in response to an output signal of the phase detector; And
A locking operation unit for performing a predetermined operation in response to the locking information,
.
12. The method of claim 11,
Wherein the locking information is activated when the second detection signal is activated after the first detection signal is activated.
12. The method of claim 11,
Wherein the locking detection unit comprises:
A first latching unit for latching whether the first detection signal is activated or not; And
And a second latching unit activated in response to an output signal of the first latching unit, latching whether the second detection signal is activated, and outputting the latched information as the locking information.
12. The method of claim 11,
A first edge latching unit for detecting and latching an edge corresponding to the compared edge among the first and second edges of the first clock signal;
A second edge latching unit for detecting and latching an edge corresponding to the compared edge among the first and second edges of the second clock signal; And
And a phase information generation unit for generating phase information of the edge to be compared in response to an output signal of the first and second edge latching units. 15. The method of claim 14,
And a reset control section for controlling a reset operation of the first and second edge latching sections after a predetermined time at the time when the phase information is activated.

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