KR100859834B1 - Delay locked loop and operation method thereof - Google Patents

Abstract

A delay locked loop and an operation method thereof are provided to perform stable operation by setting an initial delay time corresponding to PVT(Process, Voltage, Temperature) characteristics. A phase detection unit(610) detects the phase difference between an external clock and a feedback clock. A control voltage generation unit(630) generates a control voltage corresponding to an output signal of the phase detection unit. A voltage control delay line(650) generates a number of output signals reflected with different delay time for the external clock in response to the control voltage. An internal clock multiplexing unit(670) outputs one of the output signals as an internal clock in response to a skew information signal. A delay copy model unit(690) outputs the feedback clock by reflecting delay of an actual clock/data path to the internal clock.

Description

DELAY LOCKED LOOP AND OPERATION METHOD THEREOF}

1 is a block diagram illustrating a general delay locked loop.

FIG. 2 is a circuit diagram illustrating the voltage control delay line of FIG. 1. FIG.

FIG. 3 is a circuit diagram for describing a first delay cell of FIG. 2. FIG.

FIG. 4 is a graph for explaining operation characteristics of the phase detection unit of FIG. 1. FIG.

5A and 5B are timing diagrams for explaining an initial delay time.

6 is a block diagram illustrating a delay locked loop according to the present invention.

7 is a view for explaining a part of the configuration of the delay lock loop of FIG.

8 is a block diagram for explaining a skew information signal generation unit.

FIG. 9 is a circuit diagram illustrating the pulse signal generator of FIG. 8. FIG.

10 is a circuit diagram illustrating the clock sampling unit of FIG. 3.

11 is a timing diagram for explaining a part of the operation of the skew information signal generator;

* Explanation of symbols for the main parts of the drawings

610: phase detection unit 630: control voltage generation unit

650: voltage control delay line 652: first delay unit

654: second delay unit 670: internal clock multiplexer

690: delayed replication model unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a delay locked loop (DLL).

In general, semiconductor memory devices including DDR SDRAM (Double Data Rate Synchronous DRAM) receive an external clock (CLK_EXT) to generate an internal clock (CLK_INN) and use it as a reference for matching various operation timings. Therefore, a clock synchronizing circuit is required to match the timing of the external clock CLK_EXT and the internal clock CLK_INN. The clock synchronization circuit includes a phase locked loop (PLL) and a delay locked loop (DLL).

Here, when the frequency of the external clock CLK_EXT and the frequency of the internal clock CLK_INN are different from each other, a phase locked loop having a frequency multiplication function is mainly used, and the frequency of the external clock CLK_EXT and the internal clock CLK_INN are the same. In this case, the delay lock loop is mainly used. Basically, the phase locked loop and the delay locked loop have similar configurations, but in the case of the phase locked loop, a voltage controlled oscillator (VCO) is used to generate the internal clock (CLK_INN). It can be distinguished in that it uses a Voltage Controlled Delay Line (VCDL).

In the semiconductor memory device, a myriad of resistors, capacitors, and transistors are provided, and the semiconductor memory device performs various operations through various combinations of such resistors, capacitors, and transistors.

The resistors, capacitors, and transistors may vary in PVT characteristics according to process, voltage, and temperature. In particular, capacitors and transistors may vary in operation speed according to PVT characteristics. Therefore, a PVT skew according to the PVT characteristic may also occur in the semiconductor memory device composed of such devices.

1 is a block diagram illustrating a general delay locked loop.

Referring to FIG. 1, the delay lock loop may include a phase detector 110, a control voltage generator 130, a voltage control delay line 150, and a delay replication model unit 170.

The phase detector 110 detects a phase difference between the external clock CLK_EXT and the feedback clock CLK_FDB and outputs an up detection signal DET_UP or a down detection signal DET_DN. The up detection signal DET_UP and the down detection signal DET_DN are pulse signals having a pulse width corresponding to the phase difference between the external clock CLK_EXT and the feedback clock CLK_FDB.

The control voltage generator 130 outputs a voltage control signal V_CTR having a voltage level corresponding to the up detection signal DET_UP and the down detection signal DET_DN. The voltage level of the voltage control signal V_CTR is increased in response to the up detection signal DET_UP and lowered in response to the down detection signal DET_DN.

The voltage control delay line 150 reflects the delay time corresponding to the voltage control signal V_CTR to the external clock CLK_EXT and generates the internal clock CLK_INN. When the voltage level of the voltage control signal V_CTR is high, the delay time reflected in the external clock CLK_EXT is shortened. When the voltage level of the voltage control signal V_CTR is low, the delay time reflected in the external clock CLK_EXT is long. You lose.

The delay replication model unit 170 outputs the feedback clock CLK_FDB to the internal clock CLK_INN by reflecting the delay time of the actual clock / data path.

In a simple operation, the delay lock loop detects a phase difference between the external clock CLK_EXT and the feedback clock CLK_FED, generates a voltage control signal V_CTR corresponding thereto, and corresponds to the voltage control signal V_CTR. The delay time is reflected to the external clock CLK_EXT and output as the internal clock CLK_INN. The delay locked loop performs this operation repeatedly so that the external clock CLK_EXT and the feedback clock CLK_FED are in the same phase to generate the desired internal clock CLK_INN.

2 is a circuit diagram illustrating the voltage control delay line 150 of FIG. 1.

2 illustrates a plurality of delay cells 210, 230, 250, and 270 for reflecting a delay time corresponding to the voltage control signal V_CTR to the external clock CLK_EXT.

Hereinafter, for convenience of description, a positive external clock having the same phase as the external clock CLK_EXT uses 'CLK_EXT', which is the same reference numeral as the external clock CLK_EXT. Here, the negative external clock (/ CLK_EXT) is a clock signal out of phase with the positive external clock (CLK_EXT). For reference, the delay locked loop may receive a positive external clock (CLK_EXT) and a negative external clock (/ CLK_EXT) at the same time, thereby comparing the phase difference of 0 to π in the phase detector 110 instead of 0 to 2π. It becomes possible.

Each of the first to fourth delay cells 210, 230, 250, and 270 reflects a delay time corresponding to the voltage level of the voltage control signal V_CTR to the input signal. When the voltage level of the voltage control signal V_CTR increases, the delay time decreases. When the voltage level of the voltage control signal V_CTR decreases, the delay time increases. As a result, the positive external clock CLK_EXT is output to the rising internal clock RCLK_INN after the delay time reflected by the first to fourth delay cells 210, 230, 250, and 270, and the negative external clock / CLK_EXT is also output. After the delay time reflected by the first to fourth delay cells 210, 230, 250, and 270, the output is output to the polling internal clock FCLK_INN.

In other words, the voltage control delay line 150 of the delay locked loop receives the positive external clock CLK_EXT and the negative external clock / CLK_EXT and outputs the corresponding rising internal clock RCLK_INN and the falling internal clock FCLK_INN. do. Therefore, since the phase detector 110 compares the feedback clock CLK_FED and the positive external clock CLK_EXT reflecting the delay time of the delay replication model unit 170 to the polling internal clock FCLK_INN, it is not 0 to 2π. It is possible to compare the phase difference of π at.

3 is a circuit diagram illustrating the first delay cell 210 of FIG. 2. Since the first to fourth delay cells 210, 230, 250, and 270 have similar structures, the first delay cells 210 will be described as representative.

Referring to FIG. 3, the first delay cell 210 is source-drain connected between the first output terminal / OUT and the first node N1 and receives a positive external clock CLK_EXT. A second NMOS transistor NM2 having a source-drain connected between the NM1, the second output terminal OUT, and the first node N1, and receiving a negative external clock / CLK_EXT, and an external voltage terminal VDD; And a first symmetric node 310 connected between and a first output terminal / OUT, a second symmetric node 330 connected between an external voltage terminal VDD and a second output terminal OUT, and a first node N1. ) And a third NMOS transistor NM3 connected to a source-drain between the ground voltage terminal VSS and a gate input of the bias voltage V_BIAS.

Each of the first and second symmetric nodes 310 and 330 includes two PMOS transistors, and one of the two PMOS transistors has a gate connected to the voltage control signal V_CTR so that the first and second output terminals (/ Control the current flowing to OUT, OUT). The delay time is determined in the first delay cell 210 according to the current flowing through the first and second output terminals / OUT and OUT.

Therefore, the positive external clock CLK_EXT and the negative external clock / CLK_EXT are the rising internal clock RCLK_INN and the falling internal clock after the delay time reflected by the first to fourth delay cells 210, 230, 250, and 270. Outputs to (FCLK_INN).

On the other hand, the design of the voltage control delay line 150 is to be noted that the initial delay time should be secured. Here, the initial delay time refers to the delay time that the voltage control delay line 150 should have at the beginning of the operation of the delay locked loop, and a description of why the voltage control delay line 150 should have the initial delay time is illustrated in FIG. 4. Through.

4 is a graph for describing an operating characteristic of the phase detection unit 110 of FIG. 1.

4 represents the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED, and the vertical axis represents the pulse widths of the up detection signal DET_UP and the down detection signal DET_DN. For example, as the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED increases, the pulse width of the up detection signal DET_UP is increased to reduce the delay time of the voltage control delay line 150. Therefore, the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED is reduced.

The area indicated by the dotted line is a dead zone where the phase detection unit 110 cannot operate. In the dead zone, the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED occurs near -π, 0, π. If the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED is in the dead zone during the initial operation of the delay locked loop, the phase detector 110 does not operate. Therefore, the designer should set the initial delay time of the voltage control delay line 150 appropriately so that the phase difference between the positive external clock CLK_EXT and the feedback clock CLK_FED does not fall into the dead zone.

5A and 5B are timing diagrams for explaining an initial delay time.

5A illustrates a case in which the voltage control delay line 150 normally secures a desired initial delay time INT_N.

In this case, since the initial delay time INT_N is sufficiently secured, the phase difference between the rising edge of the feedback clock CLK_FED and the rising edge of the positive external clock CLK_EXT does not fall into the dead zone. Thereafter, through the normal operation, the delay lock loop causes the rising edge of the feedback clock CLK_FED and the rising edge of the positive external clock CLK_EXT to be the same.

5B illustrates a case in which the voltage control delay line 150 secures the initial delay time INT_A abnormally.

In this case, since the initial delay time INT_A is not sufficiently secured, the phase difference between the rising edge of the feedback clock CLK_FED and the rising edge of the positive external clock CLK_EXT is about π. This phase difference may fall into the dead zone, and the phase detection unit 110 malfunctions or does not operate at all. This is called the initial lock fail of the delay lock loop.

Meanwhile, the first to fourth delay cells 210, 230, 250, and 270 of the voltage control delay line 150 are formed of a plurality of transistors as shown in FIG. 3. Therefore, PVT skew may occur depending on the process, voltage, and temperature. This means that the initial delay time of the voltage control delay line 150 may be longer or shorter than the time intended by the designer.

Hereinafter, for convenience of description, PVT characteristics will be divided into TYPICAL, FAST, and SLOW.

TYPICAL means that the operating speed of NMOS transistor and PMOS transistor is typical, FAST means that the operating speed of NMOS transistor and PMOS transistor is faster than standard due to PVT characteristics, and SLOW means NMOS This means that the operation speed of the transistor and the PMOS transistor is slower than the standard due to the PVT characteristic.

If the voltage control delay line 150 provides the initial delay time intended by the designer when the PVT characteristic is TYPICAL, the initial delay time is shorter than the intended time when the PVT characteristic is FAST, and the PVT characteristic is SLOW. If the initial delay time is longer than the intended time.

In other words, when the PVT characteristic is FAST, the initial delay time may not be sufficiently secured as shown in FIG. 5B, and the phase difference between the feedback clock CLK_FED and the positive external clock CLK_EXT falls into the dead zone. An initial fix error may occur. On the contrary, when the PVT characteristic is SLOW, the initial delay time is too long, and the dead zone is also lost, and an initial fixing error of the delay locked loop may occur.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a delay locked loop capable of securing an initial delay time regardless of the influence of process, voltage, and temperature.

In addition, another object of the present invention is to provide a method for driving a delay locked loop that can stably operate by setting an initial delay time corresponding to a PVT characteristic.

According to an aspect of the present invention for achieving the above object, phase detection means for detecting a phase difference between the external clock and the feedback clock; Control voltage generation means for generating a control voltage having a voltage level corresponding to the output signal of the phase detection means; A voltage control delay line for generating a plurality of output signals reflecting different delay times with respect to the external clock in response to the control voltage; Internal clock multiplexing means for outputting any one of said plurality of output signals as an internal clock in response to a skew information signal; And a delay replication model means for outputting the feedback clock as the feedback clock reflecting the delay of the actual clock / data path.

According to another aspect of the present invention for achieving the above object, the step of detecting the phase difference between the external clock and the feedback clock; Generating a control voltage having a voltage level corresponding to the detection result; Generating a plurality of output signals reflecting different delay times with respect to the external clock in response to the control voltage; An internal clock multiplexing step for outputting any one of the plurality of output signals as an internal clock in response to a skew information signal; And outputting the feedback clock as the feedback clock by reflecting a delay of an actual clock / data path to the internal clock.

The present invention detects the PVT characteristic and sets the initial delay time differently according to the characteristic, thereby preventing the initial fixing error of the delay locked loop which may be caused when the initial delay time is different from the intended delay time.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

6 is a block diagram illustrating a delay locked loop according to the present invention.

Referring to FIG. 6, the delay locked loop includes a phase detector 610, a control voltage generator 630, a voltage control delay line 650, an internal clock multiplexer 670, and a delay replication model unit 690. ) May be provided.

The phase detector 610 detects a phase difference between the external clock CLK_EXT and the feedback clock CLK_FDB and outputs an up detection signal DET_UP or a down detection signal DET_DN. The up detection signal DET_UP and the down detection signal DET_DN are pulse signals having a pulse width corresponding to the phase difference between the external clock CLK_EXT and the feedback clock CLK_FDB.

The control voltage generator 630 outputs a voltage control signal V_CTR having a voltage level corresponding to the up detection signal DET_UP and the down detection signal DET_DN. The voltage level of the voltage control signal V_CTR is increased in response to the up detection signal DET_UP and lowered in response to the down detection signal DET_DN.

The voltage control delay line 650 generates first and second output signals OUT1 and OUT2 reflecting different delay times with respect to the external clock CLK_EXT in response to the voltage control signal V_CTR. The voltage control delay line 650 may include a first delay unit 652 for generating the first output signal OUT1 by reflecting a delay time corresponding to the voltage level of the voltage control signal V_CTR to the external clock CLK_EXT. The second delay unit 654 may be provided to generate the second output signal OUT2 by reflecting the delay time corresponding to the voltage level of the voltage control signal V_CTR to the first output signal OUT1.

Here, when the voltage levels of the voltage control signal V_CTR are high, the first and second delay units 652 and 654 shorten the delay time reflected in the input signal, and the voltage level of the voltage control signal V_CTR is increased. If it is low, the delay time reflected in the input signal becomes long.

The internal clock multiplexer 670 may output one of the first and second output signals OUT1 and OUT2 as the internal clock CLK_INN in response to the skew information signal INF_SQ. Here, the skew information signal INF_SQ is a signal having PVT characteristic information. Therefore, the internal clock multiplexer 670 outputs the first output signal OUT1 delaying the external clock CLK_EXT or the second output delays the first output signal OUT1 according to the skew information signal INF_SQ. The signal OUT2 can be output.

The delay replication model unit 690 outputs a feedback clock CLK_FDB to the internal clock CLK_INN by reflecting the delay time of the actual clock / data path.

For convenience of explanation, PVT characteristics are divided into TYPICAL, FAST, and SLOW.

In other words, TYPICAL means that the operating speeds of the NMOS transistors and the PMOS transistors are typical, and FAST means that the operating speeds of the NMOS transistors and the PMOS transistors are faster than the standard due to PVT characteristics. SLOW means that the operating speed of the NMOS transistor and the PMOS transistor is slower than the standard due to the PVT characteristics.

The problem of the prior art is that the initial delay time of the voltage control delay line is different from the designer's intention according to the PVT characteristic, so that the phase difference between the external clock CLK_EXT and the feedback clock CLK_FED falls into the dead zone. In order to solve this problem, the present invention divides the voltage control delay line 650 into a first delay unit 652 and a second delay unit 654 and according to the skew information signal INF_SQ, the first output signal OUT1. Alternatively, the second output signal OUT2 may be output as the internal clock CLK_INN to solve a problem in which the phase difference between the external clock CLK_EXT and the feedback clock CLK_FED falls into the dead zone.

First, when the PVT characteristic is FAST, the phase difference between the external clock CLK_EXT and the feedback clock CLK_FED is too small due to the low initial delay time.

It is assumed that the first delay unit 652 provides the initial delay time intended by the designer in the case where the PVT characteristic is TYPICAL. In this case, when the PVT characteristic is FAST, the internal clock CLK_INN receives the second output signal OUT2 through the first delay unit 652 and the second delay unit 654 by the skew information signal INF_SQ having the FAST information. Will be used. Therefore, the phase detector 610 compares the external clock CLK_EXT and the feedback clock CLK_FED in which the delay time is further reflected by the second delay unit 654. That is, the phase difference between the external clock CLK_EXT and the more delayed feedback clock CLK_FED may satisfy the initial delay intended by the designer, which means that the dead zone does not fall into the dead zone.

Second, when the PVT characteristic is SLOW, the phase difference between the external clock CLK_EXT and the feedback clock CLK_FED due to too much initial delay time is too large.

If the total delay time between the first delay unit 652 and the second delay unit 654 is TYPICAL, the first output signal of the first delay unit 652 is caused by the skew information signal INF_SQ having SLOW information. (OUT1) is used as the internal clock (CLK_INN). Therefore, the phase detector 610 compares the external clock CLK_EXT with the feedback clock CLK_FED which does not reflect the delay time by the second delay unit 654. That is, the phase difference between the external clock CLK_EXT and the less delayed feedback clock CLK_FED can satisfy the initial delay time intended by the designer, which means that the dead zone does not fall into the dead zone.

7 is a view for explaining a part of the configuration of the delay lock loop of FIG.

7 illustrates a first delay unit 652, a second delay unit 654, and an internal clock multiplexer 670 of the voltage control delay line 650. Similarly, for convenience of description, a positive external clock having the same phase as the external clock CLK_EXT uses 'CLK_EXT', which is the same reference numeral as the external clock CLK_EXT. Here, the negative external clock / CLK_EXT is a clock signal that is out of phase with the positive external clock CLK_EXT. Also, in response to the positive / negative external clocks CLK_EXT and / CLK_EXT, the first output signal OUT1 is set to use 'OUT1, / OUT1' and the second output signal OUT2 is also set to 'OUT2, / OUT2'. The internal clock CLK_INN is also used as the rising internal clock RCLK_INN and the polling internal clock FCLK_INN.

Referring to FIG. 7, the first delay unit 652 may include first to third delay cells 652A, 652B, and 652C. Each of the first to third delay cells 652A, 652B, and 652C reflects a delay time corresponding to the voltage level of the voltage control signal V_CTR to the input signal. When the voltage level of the voltage control signal V_CTR increases, the delay time decreases. When the voltage level of the voltage control signal V_CTR decreases, the delay time increases. Thus, the positive / negative external clocks CLK_EXT and / CLK_EXT are output as the first output signals OUT1 and / OUT1 after the delay time reflected by the first to third delay cells 652A, 652B, and 652C.

The second delay unit 654 may include a fourth delay cell 654A. The fourth delay cell 654A reflects the delay time corresponding to the voltage level of the voltage control signal V_CTR to the first output signals OUT1 and / OUT1. When the voltage level of the voltage control signal V_CTR increases, the first output signal OUT1 and / OUT1 are further delayed. When the voltage level of the voltage control signal V_CTR decreases, the first output signal OUT1 and / OUT1 is applied. Delay less. Therefore, the first output signals OUT1 and / OUT1 are output as the second output signals OUT2 and / OUT2 after the delay time reflected by the fourth delay cell 654A. Here, although the second delay unit 654 has one delay cell, according to the present invention, the second delay unit 654 compensates for the case where the initial delay time intended by the designer is too small. It is also possible to have the above delay cells.

Technical implementations of the first to fourth delay cells 652A, 652B, 652C, and 654A are the same as those of the related art, and will be apparent to those skilled in the art, and thus, detailed descriptions thereof will be omitted.

The internal clock multiplexer 670 transmits the first output signal OUT1 and / OUT1 or the second output signal OUT2 and / OUT2 as the internal clocks RCLK_INN and FCLK_INN in response to the skew information signal INF_SQ. In this case, the first transmission unit 672 and the second transmission unit 674 may be provided.

The first transfer unit 672 transfers the first output signals OUT1 and / OUT1 as internal clocks RCLK_INN and FCLK_INN in response to the skew information signal INF_SQ, and the second transfer unit 674 sends the skew information signal. In response to INF_SQ, the second output signals OUT2 and / OUT2 are transferred as internal clocks RCLK_INN and FCLK_INN.

In this case, the first and second transfer units 672 and 674 may perform an operation of transferring the input signal to the corresponding internal clocks RCLK_INN and FCLK_INN or not in response to the skew information signal INF_SQ. It may be composed of a general transfer gate or a combination of several logic gates.

Meanwhile, according to the present invention, a skew information signal generator (not shown) for generating the skew information signal INF_SQ may be further provided, which will be described with reference to FIG. 8.

8 is a block diagram illustrating a skew information signal generator.

Referring to FIG. 8, the skew information signal generator includes a delay unit 810, a pulse signal generator 830, a clock sampling unit 850, a clock counting unit 870, and a scan information signal output unit 890. ) May be provided.

The delay unit 810 is for outputting the second input signal IN2 by delaying the first input signal IN1 and may include at least one delay element (not shown). For example, an inverter or a capacitor may be used as the delay element, or a combination of the inverter and the capacitor may be used. The delay time of the delay device included in the delay unit 810 varies according to the PVT characteristic. When the PVT characteristic is FAST, the delay time provided by the delay unit 810 is reduced than when the TYPICAL is, and when the PVT characteristic is SLOW, the delay time provided by the delay unit 810 is increased than when the TYPICAL is. That is, the delay time of the second input signal IN2 changes with respect to the first input signal IN1 according to the PVT characteristic.

The pulse signal generator 830 generates a pulse signal PLS that is enabled during a period defined by the first input signal IN1 and the second input signal IN2. The pulse signal generator 830 is shown.

Referring to FIG. 9, the pulse signal generator 830 may include an exclusive logic sum gate XOR that receives a first input signal IN1 and a second input signal IN2 and outputs a pulse signal PLS. Can be. Thus, the pulse signal PLS has a pulse width in a section defined by the first input signal IN1 and the second input signal IN2. That is, the pulse signal PLS is set in response to the first input signal IN1 and reset in response to the second input signal IN2.

Referring back to FIG. 8, the clock sampling unit 850 is configured to generate the sampling clock CLK_SAM by sampling the reference clock CLK_REF in response to the pulse signal PLS. Sampling unit 850 is shown.

Referring to FIG. 10, the clock sampling unit 850 may include a logic product gate AND that receives a pulse signal PLS and a reference clock CLK_REF and outputs a sampling clock CLK_SAM. Thus, the sampling clock CLK_SAM output from the clock sampling unit 850 is a signal that toggles only a defined section of the pulse signal PLS.

Here, a reference clock generation circuit (not shown) for generating the reference clock CLK_REF may be further provided. The reference clock generation circuit generates a clock signal having a stable frequency, and may be implemented as a crystal oscillator.

In brief, the skew information signal generator generates a pulse signal PLS that is activated during a period defined by the first input signal IN1 and the second input signal IN2 delaying the input signal. The reference clock CLK_REF is sampled during the activation period of the pulse signal PLS.

11 is a timing diagram for describing a part of an operation of a skew information signal generator.

11 illustrates a first input signal IN1 and a second input signal IN2, a pulse signal PLS, a reference clock CLK_REF, and a sampling clock CLK_SAM.

Referring back to FIGS. 8 and 11, the delay unit 810 delays the first input signal IN1 by 'B' and outputs the second input signal IN2. The pulse signal PLS is activated during the period defined by the first input signal IN1 and the second input signal IN2. That is, the pulse signal PLS is set to logic 'high' in response to the time when the first input signal IN1 transitions from logic 'low' to logic 'high', and the second input signal IN2 is logic '. In response to the transition from low to logic high, the logic resets to logic low. The clock sampling unit 850 generates a sampling clock CLK_SAM that samples the reference clock CLK_REF during the activation period of the pulse signal PLS.

Here, the number of clocks of the sampling clock CLK_SAM varies depending on the PVT characteristic. For convenience of explanation, it is assumed that the 'B' section is TYPICAL.

The 'B' section determines the pulse width of the pulse signal PLS, and the reference clock CLK_REF included in the pulse width is the number of clocks of the sampling clock CLK_SAM. If the PVT characteristic is SLOW, because the operation speed is slower than that of TYPICAL, the delay time is longer and the 'B' section is increased. As a result, the pulse width of the pulse signal PLS increases, and the number of clocks of the sampling clock CLK_SAM increases. If the PVT characteristic is FAST, because the operation speed is faster than that of the TYPICAL, the delay time is shortened and the 'B' section is reduced. Accordingly, the pulse width of the pulse signal PLS is also reduced, and the number of clocks of the sampling clock CLK_SAM is reduced. According to the present invention, the PVT characteristic can be detected through the number of clocks of the sampling clock CLK_SAM.

Referring back to FIG. 8, the clock counting unit 870 is for counting the sampling clock CLK_SAM and may include a general bit counter. Here, since the circuit configuration and operation of the bit counter is obvious to those skilled in the art, detailed description thereof will be omitted. However, this bit counter only needs to output the N-bit count signal CONT corresponding to the number of clocks of the sampling clock CLK_SAM. That is, assuming that the number of clocks of the sampling clock CLK_SAM is eight, it is preferable to use a bit counter that can count eight.

The skew information signal output unit 890 generates a skew information signal INF_SQ corresponding to the count signal CONT. The maximum number that can be represented by the skew information signal INF_SQ may be as many as the maximum case that can be represented by the count signal CONT. For example, the 3-bit count signal CONT may be detected as up to eight skew information signals.

If the PVT characteristic is TYPICAL, it is assumed that the number of clocks of the sampling clock CLK_SAM is six.

When the PVT characteristic is FAST, the number of clocks of the sampling clock CLK_SAM becomes smaller than six, and in response to the corresponding count signal CONT, a skew information signal INF_SQ having information indicating that the PVT characteristic is FAST is obtained. Can be.

When the PVT characteristic is SLOW, the number of clocks of the sampling clock CLK_SAM is greater than six, and the skew information signal INF_SQ having information that the PVT characteristic is SLOW in response to the count signal CONT corresponding thereto. Can be obtained.

As described above, since the delay delay loop can adjust the initial delay time of the voltage control delay line 650 according to the PVT characteristics by using the skew information signal INF_SQ, the delay delay loop is stably secured. Early fixing errors can be prevented.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the case in which the second output signal OUT2 reflects the delay times of the first delay unit 652 and the second delay unit 654 has been described as an example, but the first and second delay units are described. Also applicable to the case where the 652 and 654 can receive the external clock CLK_EXT and output the first and second output signals OUT1 and OUT2 reflecting different delay times, respectively.

According to the present invention described above, by securing the initial delay time regardless of the influence of the process, voltage, temperature, it is possible to obtain the effect of preventing the initial fixing error.

In addition, by securing the initial delay time it is possible to ensure a stable locking operation of the delay lock loop to obtain an effect that can generate a reliable internal clock.

Claims (31)

Phase detection means for detecting a phase difference between the external clock and the feedback clock; Control voltage generation means for generating a control voltage having a voltage level corresponding to the output signal of the phase detection means; A voltage control delay line for generating a plurality of output signals reflecting different delay times with respect to the external clock in response to the control voltage; Internal clock multiplexing means for outputting any one of said plurality of output signals as an internal clock in response to a skew information signal; And Delay replication model means for outputting the feedback clock by reflecting a delay of an actual clock / data path to the internal clock; A delay locked loop comprising: The method of claim 1, The plurality of output signals includes a first output signal delaying the external clock and a second output signal delaying the first output signal. The method of claim 2, The voltage control delay line, A first delay unit for generating the first output signal by reflecting a delay time corresponding to the voltage level of the control voltage to the external clock; And a second delay unit for generating the second output signal by reflecting a delay time corresponding to the voltage level of the control voltage to the first output signal. The method of claim 3, And the first delay unit comprises at least one delay cell. The method of claim 3, And the second delay unit comprises at least one delay cell. The method according to claim 4 or 5, The external clock has a delay lock loop, characterized in that it comprises a positive external clock and a secondary external clock. The method of claim 6, The delay cell, A first symmetric node connected between the external power supply voltage terminal and the first output node; A second symmetric node connected between the external power supply voltage terminal and a second output node; A first input unit connected between the first output node and a first node and receiving the positive external clock; A second input unit connected between the second output node and the first node and receiving the secondary external clock; And And a sinking part connected between the first node and a ground voltage terminal and configured to sink a current corresponding to a bias voltage. The method of claim 3, The internal clock multiplexing means, A first transfer unit for transferring the first output signal as the internal clock in response to the skew information signal; And a second transfer unit configured to transfer the second output signal as the internal clock in response to the skew information signal. The method of claim 1, And a skew information signal generating means for generating the skew information signal. The method of claim 9, The skew information signal generating means, A delay unit for outputting a second input signal by delaying the first input signal; A pulse signal generator for generating a pulse signal that is activated during a period defined by the first and second input signals; A clock sampling unit for sampling a reference clock in response to the pulse signal; A clock counting unit for counting the sampling clock generated by the clock sampling unit; And And a skew information signal output unit configured to output the skew information signal in response to an output signal of the clock counting unit. The method of claim 10, And the pulse signal is set in response to the first input signal and reset in response to the second input signal. The method of claim 10, And the pulse signal generator includes an exclusive logic sum gate configured to receive the first and second input signals and output the pulse signal. The method of claim 10, And the sampling clock toggles during the defined interval. The method of claim 10, The clock sampling unit includes a logic product gate configured to receive the pulse signal and the reference clock and output the sampling clock. The method of claim 10, And the clock counting unit outputs an N-bit code signal corresponding to the number of clocks of the sampling clock. The method of claim 15, And the skew information signal output unit outputs the number of skew information signals corresponding to the N-bit code signal. The method of claim 10, And the skew information signal corresponds to a PVT characteristic according to a process, a voltage, and a temperature. The method of claim 10, The delay unit, And a delay lock loop comprising at least one delay element. The method of claim 10, And a reference clock generator for generating the reference clock. The method of claim 19, And the reference clock generator comprises a crystal oscillator. Detecting a phase difference between the external clock and the feedback clock; Generating a control voltage having a voltage level corresponding to the detection result; Generating a plurality of output signals reflecting different delay times with respect to the external clock in response to the control voltage; An internal clock multiplexing step for outputting any one of the plurality of output signals as an internal clock in response to a skew information signal; And Outputting the feedback clock by reflecting a delay of an actual clock / data path to the internal clock; Method of driving a delay locked loop comprising a. The method of claim 21, The plurality of output signals includes a first output signal delaying the external clock and a second output signal delaying the first output signal. The method of claim 22, The internal clock multiplexing step, Transmitting the first output signal to the internal clock in response to the skew information signal; And transmitting the second output signal to the internal clock in response to the skew information signal. The method of claim 21, And generating a skew information signal for generating the skew information signal. The method of claim 24, The skew information signal generation step, Delaying the first input signal and outputting a second input signal; Generating a pulse signal that is activated during a period defined by the first and second input signals; A sampling step of sampling a reference clock in response to the pulse signal; Counting the sampled reference clock; And And generating a skew information signal in response to a counting value. The method of claim 25, The pulse signal is set in response to the first input signal and reset in response to the second input signal. The method of claim 25, And the sampling clock generated in the sampling step is toggled during the defined period. The method of claim 27, In the counting step, And outputting a code signal of N (N is a natural number) bits corresponding to the number of clocks of the sampling clock. The method of claim 28, In generating the skew information signal, And generating a number of the skew information signals corresponding to the N-bit code signals. The method of claim 25, The skew information signal corresponds to a PVT characteristic according to a process, a voltage, or a temperature. The method of claim 25, And generating the reference clock.

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