KR20120048746A - Driving circuit for image display device and method for driving the same - Google Patents

Abstract

The present invention provides a driving apparatus and a driving method of an image display apparatus capable of adjusting the charging timing of image signals for each image display region of an image display panel, thereby improving the quality of the display image and increasing the application range of the data driver. A display device comprising: an image display panel including a plurality of pixels to display an image; A data driver for supplying image signals to data lines of the image display panel; And delay control signals for aligning the image data from the outside with the driving of the image display panel and supplying the data data to the data driver and for adjusting the supply timing of the image signals supplied to the data lines. And a timing controller for supplying to the data driver.

Description

DRIVING CIRCUIT FOR IMAGE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device. In particular, an image display is made to improve the quality of a display image and to increase the application range of a data driver by allowing the charging timing of image signals to be adjusted for each image display region of the image display panel. A driving device of the device and a driving method thereof.

Recently, flat panel display devices that are emerging include liquid crystal displays, field emission displays, plasma display panels, and light emitting displays.

The flat panel display devices are actively applied to laptops, desktop monitors, and mobile terminals due to their excellent resolution, color display, and image quality.

Recently, flat panel displays have been developed to implement a screen with high frequency, high resolution, and a large screen in order to realize a more satisfactory screen. Such flat panel displays generally include an image display panel on which an image is displayed, a driving driver for driving the image display panel, and a driving controller for controlling the driving driver.

The driving driver includes at least one driving integrated circuit. Each of the driving integrated circuits is configured to be adjacent to the periphery of the image display panel to drive each pixel of the image display panel. The drive controller is mounted on a separate printed circuit board to control each of the driving integrated circuits.

However, the conventional flat panel display device has a problem such that the amount of charge of an image signal supplied to the image display panel varies depending on the area depending on the position of the driving integrated circuits adjacent to the image display panel. In other words, the display area of the image display area that is far from the driving integrated circuit than the display areas adjacent to each of the driving integrated circuits has a problem in that the image display quality is different for each area due to the smaller amount of charge of the image signal.

In the related art, a method of increasing output characteristics of each driving integrated circuit or inversely compensating the output resistance of the driving integrated circuit has been applied. However, in this case, it is necessary to reduce development problems such as designing output characteristics of each driving integrated circuit differently according to the size, structure, and resolution characteristics of the image display panel.

The present invention is to solve the above problems, by adjusting the charging timing of the image signal for each image display area of the image display panel to improve the quality of the display image and to increase the application range of the data driver A driving device of a video display device and a driving method thereof.

According to an aspect of the present invention, there is provided a driving apparatus of an image display apparatus including an image display panel including a plurality of pixels to display an image; A data driver for supplying image signals to data lines of the image display panel; A delay control signal for aligning the image data from the outside with the driving of the image display panel to be supplied to the data driver and for supplying the image signal supplied to the data lines can be adjusted for each data line. And a timing controller for supplying the data driver.

The delay control signal may be a signal that is set in advance such that the image signals supplied to each data line are supplied at the same or different timings for each data line.

The timing controller includes an LVDS transmitter including a TTL-TO-LVDS converter, a first phase locked loop, and a plurality of buffers, and transmits a delay control signal for each data line through one of the buffers. The red, green, and blue aligned image data is transmitted using the remaining plurality of buffers.

The data driver includes an LVDS receiver including an LVDS-TO-TTL converter, a second phase locked loop, and a plurality of receive buffers, and transmits a delay control signal for each data line through any one of the plurality of receive buffers. And receiving the red, green, and blue aligned image data through the remaining receiving buffers.

The delay control signal may be set to have a larger delay timing in the corresponding data lines in a region closest to the data driver in the image display panel, and set a smaller delay timing in a data line in an area farther away from the data driver. According to the size, configuration, and driving characteristics of the image display panel, the delay level of supply of the video signal is differently set for each region.

In addition, a driving method of an image display apparatus according to an embodiment of the present invention for achieving the above object comprises the steps of supplying the image signals to the data lines of the image display panel using a data driver; Supplying the image data from the outside to the data driver in alignment with the driving of the image display panel; And supplying a delay control signal to the data driver so that the timing of supplying the image signals supplied to the data lines can be adjusted for each data line.

The delay control signal may be a signal that is set in advance such that the image signals supplied to each data line are supplied at the same or different timings for each data line.

The step of supplying the delay control signal to the data driver may include a TTL-TO-LVDS converter, a first phase synchronization loop, and an LVDS transmitter including a plurality of buffers. The delay control signal for each data line is transmitted, and red, green, and blue aligned image data are transmitted using the remaining plurality of buffers.

The image signals may be supplied to the data lines by using an LVDS receiver including an LVDS-TO-TTL converter, a second phase locked loop, and a plurality of receive buffers. Receiving a delay control signal for each data line, and receiving the red, green and blue aligned image data through the remaining receiving buffers.

The delay control signal may be set to have a larger delay timing in the corresponding data lines in a region closest to the data driver in the image display panel, and set a smaller delay timing in a data line in an area farther away from the data driver. According to the size, configuration, and driving characteristics of the image display panel, the delay level of supply of the video signal is differently set for each region.

The driving device and the driving method of the image display apparatus of the present invention having the above-described characteristics allow the charging timing of the image signals to be adjusted for each image display region of the image display panel, thereby minimizing the difference in the charge amount of the image signals for each image display region. Can improve the quality.

In addition, an application range of the data driver may be increased by adjusting the charging timing of the image signals for each image display area according to the size, structure, resolution characteristics, etc. of the image display panel. In this case, there is no need to develop drivers separately according to the characteristics of the image display panel, thereby reducing development cost and time between products.

1 is a configuration diagram showing a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram illustrating an LVDS transmitter included in the timing controller of FIG. 1. FIG.
3 is a configuration diagram illustrating an LVDS receiver provided in the data driver of FIG. 1.
4 is a diagram illustrating LVDS data format information for each pixel of an LVDS transmitter;
5A and 5B are graphs illustrating delay output times of video signal output channels of a data driver.

Hereinafter, a driving apparatus and a driving method of an image display apparatus according to an exemplary embodiment of the present invention having the above-described features and effects will be described in detail with reference to the accompanying drawings. Here, although the image display device of the present invention may be a liquid crystal display device, a field emission display device, a plasma display panel, a light emitting display device, etc., only the case where it is applied to the liquid crystal display device will be described as an example.

1 is a configuration diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

1 includes a liquid crystal panel 2 including a plurality of pixels to display an image; A data driver 4 for driving data lines DL1 to LDm of the liquid crystal panel 2; A gate driver 6 driving gate lines GL1 to GLn of the liquid crystal panel; The image data RGB from the outside is aligned with the driving of the liquid crystal panel 2 to be supplied to the data driver 4, and the timing of supplying the image signals supplied to the data lines DL1 to LDm is determined. A timing controller 8 is provided to supply the delay control signal G_SOE to the data driver 6 to be adjusted for each data line DL1 to LDm.

In addition to the delay control signal G_SOE, the timing controller 8 includes gate and data control signals GCS and DCS for controlling the gate driver 6 and the data driver 4, and the data lines DL1 to DLm. Also, a polarity control signal for converting the polarity of the video signals supplied to the N / W may be generated and supplied to the gate and the data drivers 6 and 4.

The liquid crystal panel 2 includes a thin film transistor (TFT) and a liquid crystal capacitor connected to a TFT formed in each pixel area defined by the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. (Clc). The liquid crystal capacitor Clc is constituted of a pixel electrode connected to a TFT, and a common electrode facing each other with the pixel electrode and the liquid crystal interposed therebetween. The TFT supplies the image signals from the respective data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the respective gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating layer interposed therebetween. In contrast, the storage capacitor Cst is formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween.

The data driver 4 includes a data control signal DCS from the timing controller 8, for example, a source start pulse (SSP), a source shift clock (SSC), and a source output enable (SCS). A data output arranged from the timing controller 8 is converted into an analog voltage, that is, an image signal, using a source output enable (SOE) signal or the like. Specifically, the data driver 4 latches the data Data gamma-converted and aligned through the timing controller 8 according to the SSC, and then scan pulses are applied to the gate lines GL1 to GLn in response to the SOE signal. Each horizontal line is supplied with one horizontal line of video signals to each of the data lines DL1 through DLm.

At this time, the data driver 4 delays and supplies the corresponding video signal for each of the data lines DL1 to LDm according to the delay control signal G_SOE signal from the timing controller 8. The delay control signal G_SOE is a signal preset in an external memory or the like such that an image signal supplied to each data line DL1 to LDm is supplied at the same or different timing to each data line DL1 to LDm. . Accordingly, the data driver 4 delays and supplies the video signal for each data line DL1 to LDm in response to the delay control signal G_SOE.

Meanwhile, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gray level values of the sorted data, and converts the selected gamma voltage to each data line DL1 to DLm as an image signal. It is also supplied.

The gate driver 6 includes a gate control signal GCS from the timing controller 8, for example, a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GSC). Scan pulses are sequentially generated in response to a GOE (Gate Output Enable) signal, and are sequentially supplied to the gate lines GL1 to GLn. In other words, the gate driver 6 shifts the GSP from the timing controller 8 in accordance with GSC to sequentially supply scan pulses, for example, gate-on voltages, to the gate lines GL1 to GLn. The gate-off voltage is supplied to the gate lines GL1 to GLn during the period when the gate-on voltage is not supplied. Here, the gate driver 6 controls the pulse width of the scan pulse in accordance with the GOE signal.

The timing controller 8 arranges the image data RGB input from an external system or the like and supplies the image data RGB to the data driver 4 according to the size and resolution of the liquid crystal panel 2. At this time, the timing controller 8 sequentially reads the delay control signal G_SOE signal stored in the external memory 10 such as EEPROM and supplies it to the data driver 4 together with the sorted image data Data. In addition, the timing controller 8 uses a gate and data control signal using at least one of an external synchronization signal, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync. The gate and data drivers 6 and 4 are controlled by generating (GCS and DCS) and supplying them to the gate and data drivers 6 and 4, respectively.

At this time, the timing controller 8 transmits the aligned image data (Data), data control signal (DCS) and delay control signal (G_SOE) signals to the data driver 4 by using a low voltage differential signaling (LVDS) interface technology. do. Here, the LVDS interface technology is a technology for converting and transmitting the image data (Data) and control signals, etc. into LVDS signals. Specifically, the LVDS interface method converts and supplies a TTL (Transistor-Transistor Logic) signal into an LVDS signal, and then converts the LVDS signal into a TTL signal to perform timing formatting. The formatted data or control signals are separate data. Drivers may be supplied to a plurality of drive integrated circuits (D-ICs), for example.

The image data Data supplied to the data driver 4 may be data of 8 bits for each of three colors, that is, red (R), green (G), and blue (B). In this case, three-color image data of 8 bits are transmitted through a data control signal DCS and a delay control signal G_SOE signal, and at least four corresponding TTL signal transmission lines and respective buffers. This interface method will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating an LVDS transmitter included in the timing controller of FIG. 1. 3 is a configuration diagram illustrating an LVDS receiver included in the data driver of FIG. 1.

First, referring to FIG. 2, the timing controller 8 of the present invention includes a TTL-TO-LVDS converter 110, a first phase locked loop 120, and a plurality of first phase locked loops. And a LVDS transmission unit including buffers 130a to 130g, wherein the timing controller 8 performs one of the plurality of buffers 130a to 130g for each of the data lines DL1 to LDm through one of the buffers 130g. The delay control signal G_SOE is transmitted, and the aligned image data Data of red (R), green (G), and blue (B) is transmitted using the remaining buffers 130a to 130g.

More specifically, referring to FIG. 2, a process in which a TTL signal is changed into an LVDS signal is provided. The image data supplied to the liquid crystal panel 2 to display an image includes three colors, that is, red (R) and green (G). ) And 8 bits of data for blue (B). In this case, three-color image data of 8 bits each have a TTL-TO-LVDS converter that configures an LVDS transmitter through a TTL (Transistor-Transistor Logic) signal transmission line of 24 or 48 lines (when odd and even frames are divided). 110).

The delay control signal G_SOE for each data line DL1 to LDm is connected to the TTL-TO- through three, six, eight, or more TTL signal transmission lines according to the number of bits of the delay control signal G_SOE. Is applied to the LVDS converter 110. In the case of SSC, it is applied to the first PLL 120.

The first PLL 120 is configured to provide a reference clock for operation with the TTL-TO-LVDS converter 110, and the reference clock may be synchronized with an input dot clock DCLK or SSC. The TTL-TO-LVDS converter 110 converts the TTL signal into an LVDS signal using this reference clock, and the TTL-TO-LVDS converter 110 stores the remaining buffers except the delay control signal (G_SOE) transmission buffer 130g. The LVDS signals IN0 to IN5 to be transmitted for each transmission line are output through 130a to 130f. The first PLL 120 also converts the SSC into an LVDS signal and transmits the clock signal CKIN through the PLL buffer 130h.

Next, referring to FIG. 3, the data driver 4 of the present invention includes an LVDS receiver including an LVDS-TO-TTL converter, a second phase locked loop 230, and a plurality of receive buffers 210a to 210g. At this time, the data driver 4 receives the delay control signal G_SOE for each of the data lines DL1 to LDm through one of the plurality of receive buffers 210a to 210g and the remaining receive buffers. The received image data Data of red (R), green (G), and blue (B) are received through the fields 210a to 210f.

The LVDS receiving unit converts the LVDS data of each pixel that is converted into the LVDS signal and transmitted, that is, the image data RGB of each pixel that has been converted into the LVDS signal and the delay control signal G_SOE for each data line DL1 to LDm. The signal is converted into a TTL signal and supplied to the timing controller 8.

Looking at the process of changing the LVDS signal into a TTL signal, the LVDS signal including the image data (Data) transmitted through IN0 to IN5 is the LVDS-TO-TTL converter through the first to sixth reception buffers 210a to 210f. The clock signal CKIN, which has been input to 220 and has been LVDS converted, is also input to the second PLL 230 through the PLL receiving buffer 210h. Then, the reference signal is provided to the LVDS-TO-TTL converter 220 as a TTL signal at the second PLL 230, and the LVDS-TO-TTL converter 220 TTL the input LVDS signal and the delay control signal G_SOE. It converts the signal and outputs it to the corresponding transmission line. Then, 24 or 48 bits of data and delay control signal (G_SOE) corresponding to the image data as TTL signals are transmitted to the TTL transmission line.

4 is a diagram illustrating LVDS data format information for each pixel of the LVDS transmitter.

As shown in FIG. 4, one port LVDS data LV of each pixel includes red, green, and blue image data LV0 + to LV2 + and even frame 8 of 8 bits of odd frame. The format is set to include the red, green, and blue image data LV3 + to LV5 + bit by bit and the delay control signal G_SOE for each data line DL1 to LDm. Accordingly, the LVDS transmitter of the present invention converts the 48-bit image data Data of odd and even frames and the delay control signal G_SOE for each data line DL1 to LDm of any one predetermined bit into the LVDS signal format. To LVDS data.

Accordingly, the data driver 4 receiving the image data Data and the delay control signal G_SOE for each data line DL1 to LDm through the LVDS receiver converts the aligned data Data into an image signal. The video signal is delayed and supplied for each data line DL1 to LDm according to the delay control signal G_SOE for each data line DL1 to LDm.

5A and 5B are graphs illustrating delay output times of video signal output channels of a data driver.

In the case of FIG. 5A, when the delay control signal G_SOE is set, the delay time is increased for the corresponding data lines in the region closest to the data driver 4, and the delay start is set smaller in the data lines in the region farther away from the integrated circuit. An example is shown. In this case, the image signal output timing of the short data lines positioned adjacent to the data driver 4 and the long data lines positioned far from the data driver 4 may be different to prevent signal distortion due to electromagnetic interference. At the same time, the charging period of the video signal can be minimized by making the period during which the video signal is charged to be the same. Therefore, the display quality can be improved by maintaining the display quality of the image uniformly regardless of the position of the data driver 4 configured adjacent to the liquid crystal panel 2.

Meanwhile, in the case of FIG. 5B, when the delay control signal G_SOE is set, the delay time is set in the corresponding data lines as the area closest to the data driver 4 is set, and the delay start is as in the data line in the area farther away from the integrated circuit. Is set to a small value, but the delay degree is set differently according to the characteristics of the liquid crystal panel 2. In this case, the image signal output timings of the short data lines positioned adjacent to the data driver 4 and the long data lines positioned far from the data driver 4 are different while the size and configuration of the liquid crystal panel 2 are different. And signal transmission characteristics and the like in consideration of the maximum. Therefore, the signal distortion due to electromagnetic interference can be more effectively prevented, and the charging period of the video signal can be minimized by making the period during which the video signal is charged to be the same. That is, regardless of the position of the data driver 4 configured adjacent to the liquid crystal panel 2, the display quality of the image can be maintained uniformly, thereby improving the display quality.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

2: liquid crystal panel 4: gate driver
6: data driver 8: timing controller
110: TTL-TO-LVDS Converter 220: LVDS-TO-TTL Converter

Claims (10)

An image display panel including a plurality of pixels to display an image;
A data driver for supplying image signals to data lines of the image display panel;
A delay control signal for aligning the image data from the outside with the driving of the image display panel to be supplied to the data driver and for supplying the image signal supplied to the data lines can be adjusted for each data line. And a timing controller for supplying the data driver. The method of claim 1,
The delay control signal is
And a predetermined signal such that the image signals supplied to the data lines are supplied at the same or different timings for each of the data lines. The method of claim 2,
The timing controller is
A LVDS transmitter comprising a TTL-TO-LVDS converter and a first phase locked loop and a plurality of buffers,
A delay control signal for each data line is transmitted through one of the plurality of buffers and red, green, and blue aligned image data are transmitted using the remaining plurality of buffers. Drive system. The method of claim 3, wherein
The data driver
An LVDS receiver comprising an LVDS-TO-TTL converter and a second phase locked loop and a plurality of receive buffers,
Receive a delay control signal for each data line through any one of the plurality of receive buffers, and through the remaining receive buffers the red, green and blue aligned image data is received. Drive of the device. The method of claim 2,
The delay control signal is
In the image display panel, the delay timing is set to the corresponding data lines in the region closest to the data driver, and the delay timing is set to be smaller in the data lines in the region located farther from the data driver.
And a supply delay level of the image signal is differently set for each region according to the size, configuration, and driving characteristics of the image display panel. Supplying image signals to data lines of an image display panel using a data driver;
Supplying the image data from the outside to the data driver in alignment with the driving of the image display panel; And
And supplying a delay control signal to the data driver so that the timing of supplying the image signals supplied to the data lines can be adjusted for each of the data lines. The method according to claim 6,
The delay control signal is
And a predetermined signal such that the image signals supplied to the data lines are supplied at the same or different timings for each of the data lines. The method of claim 7, wherein
The step of supplying the delay control signal to the data driver
By using an LVDS transmitter comprising a TTL-TO-LVDS converter, a first phase locked loop and a plurality of buffers,
A delay control signal for each data line is transmitted through one of the plurality of buffers and red, green, and blue aligned image data is transmitted using the remaining plurality of buffers. Driving method. The method of claim 8,
Supplying image signals to the data lines
Using an LVDS receiver comprising an LVDS-TO-TTL converter, a second phase locked loop and a plurality of receive buffers,
Receiving a delay control signal for each data line through one of the plurality of receiving buffers, and receiving the red, green, and blue aligned image data through the remaining receiving buffers. A method of driving a video display device. The method according to claim 6,
The delay control signal is
In the image display panel, the delay timing is set to the corresponding data lines in the region closest to the data driver, and the delay timing is set to be smaller in the data lines in the region located farther from the data driver.
And a supply delay degree of the video signal is set differently for each region according to the size, configuration, and driving characteristics of the video display panel.

Images