KR101726628B1 - Driving circuit for image display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for an image display apparatus and a driving method thereof that can improve the quality of a display image and increase the application range of a data driver by adjusting the charging timing of image signals for each image display region of the image display panel An image display panel for displaying an image with a plurality of pixels defined by a plurality of gate lines and a plurality of data lines arranged in a direction perpendicular to each other; A data driver for supplying image signals to the plurality of data lines of the image display panel; And a data driver for supplying image data from outside to the data driver in a manner suitable for driving the image display panel and for adjusting a supply timing of a video signal supplied to the plurality of data lines, And a timing controller for supplying delay control signals for the respective data lines to the data driver.

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a video display device and a driving method thereof. BACKGROUND OF THE INVENTION [0002]

The present invention relates to an image display apparatus, and more particularly, to an image display apparatus capable of adjusting a charging timing of image signals for each image display region of an image display panel, thereby improving the quality of a display image, The present invention relates to a driving apparatus of a device and a driving method thereof.

2. Description of the Related Art Recently, flat panel display devices that have emerged include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

The flat panel display devices have excellent resolution, color display, and image quality, and are actively applied to notebook computers, desktop monitors, and mobile terminals.

In recent years, flat panel display devices have been developed to realize a screen with a high frequency, a high resolution and a large screen in order to realize a more satisfactory screen. Such flat panel display devices generally include an image display panel on which an image is displayed, a driving driver for driving the image display panel, and a driving controller for controlling the driving driver.

In the case of the driving driver, at least one driving integrated circuit is disposed adjacent to a peripheral portion of the image display panel to drive each pixel of the image display panel. The drive controller is mounted on a separate printed circuit board and controls each drive integrated circuit.

However, in the conventional flat panel display device, there is a problem that the charged amount of the video signal supplied to the image display panel varies depending on the area depending on the position of the driving integrated circuits formed adjacent to the image display panel. In other words, in the case of a display area which is farther from the driving integrated circuit than the display areas adjacent to the respective driving integrated circuits in the image display area, there is a problem that the image display quality is different depending on the area because the charging amount of the video signal is smaller.

Conventionally, methods such as increasing the output characteristics of the driving integrated circuits or inversely compensating the output resistance of the driving integrated circuit have been applied. However, in this case, development problems such as designing the output characteristics of the respective driving integrated circuits must be reduced according to the size of the image display panel, the structure thereof, resolution characteristics, and the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to improve the quality of a display image and increase the application range of a data driver by adjusting the charging timing of image signals for each image display region of the image display panel To a driving apparatus of a video display apparatus and a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving an image display apparatus including a plurality of pixels defined by a plurality of gate lines and a plurality of data lines arranged in a direction perpendicular to each other, An image display panel for displaying an image; A data driver for supplying image signals to the plurality of data lines of the image display panel; A data driver for supplying image data supplied from the outside to the data driver in accordance with driving of the image display panel and for supplying timing of the video signal supplied to the plurality of data lines to each data line, And a timing controller for supplying line-by-line delay control signals to the data driver.

And the delay control signals for the respective data lines are predetermined signals so that the video signals supplied to the respective data lines are supplied at the same or different timing for each of the data lines.

The timing controller includes a TTL-TO-LVDS converter, a first phase-locked loop, and an LVDS transmitter including a plurality of buffers, and transmits a delay control signal for each of the data lines through one of the plurality of buffers And red, green, and blue aligned image data are transmitted using the remaining plurality of buffers.

Wherein the data driver includes an LVDS receiver including an LVDS-TO-TTL converter, a second phase-locked loop, and a plurality of receive buffers, wherein the delay driver controls a delay control signal for each data line through one of the plurality of receive buffers And receives the red, green, and blue aligned image data through the remaining reception buffers.

The delay control signals for the respective data lines are set to have a larger delay timing in the data lines closest to the data driver in the image display panel and the delay timings in the data lines in the far area in the data driver are set to be smaller And the supply delay of the video signal is set differently according to the size, configuration, and driving characteristics of the video display panel.

According to another aspect of the present invention, there is provided a method of driving an image display device including a plurality of gate lines and a plurality of data lines arranged in a direction perpendicular to each other, A method of driving a panel, the method comprising: arranging image data from outside in accordance with driving of the image display panel; Supplying the delay control signals and the aligned image data for each data line for adjusting the supply timing of the video signal supplied to the plurality of data lines for each data line; Receiving delay control signals for each data line and the aligned image data; And supplying the aligned image data to the plurality of data lines according to the delay control signals for the respective data lines.

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The driving device and the driving method of the video display device having the above characteristics can adjust the charging timing of the video signals for each video display area of the video display panel, Can be improved.

Further, the application range of the data driver can be increased by adjusting the charging timing of the video signals for each image display region according to the size, structure, resolution characteristics, etc. of the image display panel. In this case, it is not necessary to separately develop drivers in accordance with the characteristics of the image display panel, so that the development cost and time of the product can be reduced.

1 is a configuration diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention;
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LVDS transmitter.
FIG. 3 is a block diagram showing an LVDS receiver included in the data driver of FIG. 1. FIG.
4 is a diagram showing LVDS data format information for each pixel in an LVDS transmission unit;
5A and 5B are graphs showing a delay output time of each video signal output channel of the data driver.

Hereinafter, a driving apparatus and a driving method thereof according to an embodiment of the present invention having the above-described features and effects will be described in detail with reference to the accompanying drawings. Here, the video display device of the present invention may be a liquid crystal display device, a field emission display device, a plasma display panel, a light emitting display device, and the like. Hereinafter, only a case where the present invention is applied to a liquid crystal display device will be described.

1 is a block diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention.

The liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 2 having a plurality of pixels to display an image; A data driver 4 for driving the data lines DL1 to LDm of the liquid crystal panel 2; A gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel; And supplies the image data RGB from the outside to the data driver 4 in accordance with the driving of the liquid crystal panel 2 and supplies the video signals to the data lines DL1 to LDm, And a timing controller 8 for supplying to the data driver 6 a delay control signal G_SOE that can be adjusted for each of the data lines DL1 to LDm.

The timing controller 8 includes gate and data control signals GCS and DCS for controlling the gate driver 6 and the data driver 4 in addition to the delay control signal G_SOE and data lines DL1 to DLm And a polarity control signal for converting the polarity of the video signals supplied to the data driver 6 and the data driver 4, respectively.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, and a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating film interposed therebetween. Alternatively, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

The data driver 4 receives a data control signal DCS from the timing controller 8, for example, a source start pulse SSP, a source shift clock SSC, a source output enable SOE (Source Output Enable) signal from the timing controller 8 to an analog voltage, that is, a video signal. Specifically, the data driver 4 latches the data (Data) subjected to the gamma conversion through the timing controller 8 in accordance with the SSC, and supplies a scan pulse to each of the gate lines GL1 to GLn in response to the SOE signal And supplies a video signal for one horizontal line to each of the data lines DL1 to DLm for every one horizontal period to be supplied.

At this time, the data driver 4 delays the corresponding video signal for each of the data lines DL1 to LDm according to a delay control signal (G_SOE) signal from the timing controller 8. The delay control signal G_SOE is a signal preset in the external memory or the like so that the video signals supplied to the data lines DL1 to LDm are supplied to the data lines DL1 to LDm at the same timing or at different timings . Accordingly, the data driver 4 delays the corresponding video signal for each data line DL1 to LDm in response to the delay control signal (G_SOE) signal.

On the other hand, the data driver 4 selects a positive or negative gamma voltage having a predetermined level according to the gray level of the aligned data Data, and supplies the selected gamma voltage to each of the data lines DL1 to DLm Supply.

The gate driver 6 outputs a gate control signal GCS from the timing controller 8, for example, a gate start pulse GSP, a gate shift clock GSC, a gate output enable Sequentially generates a scan pulse in response to a Gate Output Enable (GOE) signal, and sequentially supplies the scan pulse to the gate lines GL1 to GLn. In other words, the gate driver 6 shifts the GSP from the timing controller 8 according to the GSC to sequentially supply a scan pulse, for example, a gate-on voltage to the gate lines GL1 to GLn. Then, the gate-off voltage is supplied during the period when the gate-on voltage is not supplied to the gate lines GL1 to GLn. Here, the gate driver 6 controls the pulse width of the scan pulse in accordance with the GOE signal.

The timing controller 8 arranges image data RGB inputted from an external system or the like in accordance with the size and resolution of the liquid crystal panel 2 and supplies the image data to the data driver 4. [ At this time, the timing controller 8 sequentially reads a delay control signal (G_SOE) signal stored in advance in the external memory 10 such as an EEPROM and supplies the same to the data driver 4 together with the aligned image data Data. The timing controller 8 uses at least one of an external synchronizing signal, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync, (GCS, DCS) and supplies them to the gate and data drivers 6, 4, respectively, thereby controlling the gate and data drivers 6, 4.

At this time, the timing controller 8 transmits the aligned image data Data, data control signal DCS and delay control signal (G_SOE) signals to the data driver 4 by using a low voltage differential signaling (LVDS) do. Here, the LVDS interface technology is a technology for converting and transferring the image data (Data), control signals, and the like into LVDS signals. Specifically, the LVDS interface method converts a TTL (Transistor-Transistor Logic) signal into an LVDS signal, and then converts the LVDS signal into a TTL signal to form a timing format. For example, a plurality of drive ICs (D-ICs), respectively.

The image data Data supplied to the data driver 4 may be data of 8 bits for three colors, i.e., red (R), green (G) and blue (B) In this case, the 3-bit color image data of 8 bits are transmitted through the data control signal DCS, the delay control signal (G_SOE) signal, and the corresponding TTL signal transmission lines and buffers of at least four lines. Such an interface method will be described in more detail with reference to the accompanying drawings hereinafter.

FIG. 2 is a block diagram illustrating an LVDS transmitter included in the timing controller of FIG. 1. Referring to FIG. 3 is a block diagram illustrating an LVDS receiver included in the data driver of FIG.

Referring to FIG. 2, the timing controller 8 includes a TTL-TO-LVDS converter 110, a first PLL 120 and a plurality of And a timing controller 8 is connected to the data lines DL1 to LDm through the buffer 130g of the plurality of buffers 130a to 130g, And transmits the delayed control signal G_SOE and the aligned image data Data of red (R), green (G) and blue (B) using the remaining plurality of buffers 130a to 130g.

2, the image data supplied to the liquid crystal panel 2 to display an image is divided into three colors: red (R), green (G), and green ) And blue (B), respectively. In this case, the 8-bit tri-color image data is converted into a TTL-TO-LVDS converter (LTL) constituting an LVDS transmission unit through a TTL (Transistor-Transistor Logic) signal transmission line of 24 lines or 48 lines (at odd and even frame division) 110).

The delay control signal G_SOE for each of the data lines DL1 to LDm is supplied to the TTL-TO-DA converter through the corresponding TTL signal transmission line of 3 lines, 6 lines, 8 lines or more according to the number of bits of the delay control signal G_SOE. LVDS converter < RTI ID = 0.0 > 110 < / RTI > In the case of the SSC, the first PLL 120 is applied.

The first PLL 120 is configured to provide a reference clock for operation to the TTL-TO-LVDS converter 110, and the reference clock may be synchronized with the input dot clock DCLK or SSC. The TTL-TO-LVDS converter 110 converts the TTL signal to the LVDS signal using the reference clock, and the TTL-TO-LVDS converter 110 converts the TTL- And outputs LVDS signals IN0 to IN5 to be transmitted for each transmission line through the transmission lines 130a to 130f. The first PLL 120 also converts the SSC into an LVDS signal and transmits the clock signal CKIN through the PLL buffer 130h.

3, the data driver 4 of the present invention includes an LVDS receiver including an LVDS-TO-TTL converter, a second phase-locked loop 230, and a plurality of reception buffers 210a to 210g. At this time, the data driver 4 receives a delay control signal G_SOE for each of the data lines DL1 to LDm through one of the reception buffers 210a to 210g, (R), green (G), and blue (B) image data (Data) through the first and second color filters 210a to 210f.

The LVDS receiving unit receives the LVDS data of each pixel converted into the LVDS signal, that is, the image data RGB of each pixel converted and supplied to the LVDS signal and the delay control signal G_SOE for each of the data lines DL1 to LDm TTL signal and supplies it to the timing controller 8.

The LVDS signal including the image data Data transmitted through IN0 to IN5 is input to the LVDS-TO-TTL converter 210 through the first to sixth receiving buffers 210a to 210f. And the LVDS converted clock signal CKIN is also input to the second PLL 230 through the PLL receiving buffer 210h. The second PLL 230 provides a reference signal to the LVDS-TO-TTL converter 220 as a TTL signal and the LVDS-TO-TTL converter 220 converts the input LVDS signal and the delay control signal G_SOE into TTL Signal and outputs it to the corresponding transmission line. Then, the 24 or 48 bit data corresponding to the image data and the delay control signal (G_SOE) are transmitted as the TTL signal to the TTL transmission line.

4 is a diagram illustrating LVDS data format information for each pixel in the LVDS transmission unit.

4, the 1-port LVDS data LV of each pixel includes red, green, and blue image data LV0 + to LV2 + of 8 bits of an odd frame and an even frame 8 The format is set to include the red, green, and blue image data LV3 + to LV5 + bit by bit and the delay control signal G_SOE for each data line DL1 to LDm. Accordingly, the LVDS transmitter of the present invention converts the 48-bit image data of odd and even frames and the delay control signal G_SOE for each data line DL1 to LDm of a predetermined bit into the LVDS signal format And transmits it as LVDS data.

The data driver 4 supplied with the image data Data and the delay control signals G_SOE for the data lines DL1 to LDm through the LVDS receiver converts the aligned data into image signals, And supplies the delayed video signal for each data line DL1 to LDm in accordance with the delay control signal G_SOE for each data line DL1 to LDm.

5A and 5B are graphs showing a delay output time for each video signal output channel of the data driver.

5A, when the delay control signal G_SOE is set, the delay time is increased for the data line closest to the data driver 4, and the delay start is set smaller for the data line located far away from the integrated circuit An example is shown. In this case, the video signal output timing of the short data lines positioned adjacent to the data driver 4 and the long data lines positioned far away from the data driver 4 are different, thereby preventing signal distortion due to electromagnetic interference In addition, the charging period of the video signal can be minimized by maximizing the period during which the video signal is charged. Accordingly, the display quality of the image can be uniformly maintained regardless of the position of the data driver 4 adjacent to the liquid crystal panel 2, thereby improving the display quality.

In the case of FIG. 5B, when delay control signal G_SOE is set, the delay time is set large for the data lines closest to the data driver 4, and the data lines for the data lines far from the integrated circuit are delayed The delay amount is set differently for each region according to the characteristics of the liquid crystal panel 2. In this case, the video signal output timings of the short data lines adjacent to the data driver 4 and the long data lines positioned far away from the data driver 4 are different from each other, and the size and configuration of the liquid crystal panel 2 And the signal transmission characteristics, etc., can be coped with as much as possible. Therefore, it is possible to more effectively prevent the signal distortion due to the electromagnetic interference, and the charging period of the video signal can be minimized by maximizing the period of time during which the video signal is charged. That is, the display quality of the image can be uniformly maintained regardless of the position of the data driver 4 adjacent to the liquid crystal panel 2, thereby improving the display quality.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

2: liquid crystal panel 4: gate driver
6: Data driver 8: Timing controller
110: TTL-TO-LVDS converter 220: LVDS-TO-TTL converter

Claims (10)

An image display panel for displaying an image with a plurality of pixels defined by a plurality of gate lines and a plurality of data lines arranged in a direction perpendicular to each other;
A data driver for supplying image signals to the plurality of data lines of the image display panel; And
A data driver for supplying image data supplied from the outside to the data driver in accordance with the driving of the image display panel and for controlling supply timings of the video signals supplied to the plurality of data lines for each data line, And a timing controller for supplying the delay control signals to the data driver. The method according to claim 1,
The delay control signals for each data line
Wherein the video signal supplied to each of the data lines is a signal preset to be supplied at the same or different timing for each of the data lines. 3. The method of claim 2,
The timing controller
A TTL-TO-LVDS converter, a first phase-locked loop, and an LVDS transmitter comprising a plurality of buffers,
And transmits the delay control signal for each data line through any one of the plurality of buffers and transmits the red, green, and blue aligned video data using the remaining plurality of buffers. Driving device. The method of claim 3,
The data driver
A LVDS-TO-TTL converter, a second phase-locked loop and an LVDS receiver comprising a plurality of receive buffers,
And receiving the delay control signal for each of the data lines through one of the plurality of reception buffers and receiving the red, green, and blue aligned image data through the remaining reception buffers. Device for driving a device. 3. The method of claim 2,
The delay control signals for each data line
Wherein a delay timing is set to a corresponding data line in an area closest to the data driver in the image display panel and a delay timing is set to be smaller in a data line in an area located far away from the data driver,
Wherein the supply delay of the video signal is set differently according to the size, configuration, and driving characteristics of the video display panel. A method of driving an image display panel including a plurality of gate lines and a plurality of data lines arranged in a direction perpendicular to each other to display an image,
The method comprising: aligning image data from outside in accordance with driving of the image display panel;
Supplying the delay control signals and the aligned image data for each data line, the supply timing of the video signals supplied to the plurality of data lines being adjusted for each data line;
Receiving delay control signals for each data line and the aligned image data; And
And supplying the aligned image data to the plurality of data lines according to the delay control signals for the respective data lines. The method according to claim 6,
The delay control signals for each data line
Wherein the video signal supplied to each of the data lines is a signal set to be supplied at the same or different timing for each of the data lines. 8. The method of claim 7,
The step of supplying the delay control signals and the aligned image data for each data line
Using a TTL-TO-LVDS converter, a first phase-locked loop and an LVDS transmitter comprising a plurality of buffers,
And transmits the delay control signal for each data line through any one of the plurality of buffers and transmits the red, green, and blue aligned video data using the remaining plurality of buffers. Driving method. 9. The method of claim 8,
The step of receiving the control signals for each data line and the aligned image data
Using an LVDS receiver comprising an LVDS-TO-TTL converter, a second phase-locked loop and a plurality of receive buffers,
Receiving the delay control signal for each data line through one of the plurality of reception buffers and receiving the red, green, and blue aligned image data through the remaining reception buffers, And a driving method of the video display device. The method according to claim 6,
The delay control signals for each data line
The delay timing is set to a larger value in the data line closest to the data driver in the image display panel and the delay timing is set to be smaller in the data line in the area located far away from the data driver,
Wherein the supply delay of the video signal is set differently according to the size, configuration, and driving characteristics of the image display panel.

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