KR20120036434A - Level shifter - Google Patents

Abstract

PURPOSE: A level shifter is provided to reduce a leakage current in a deep power down mode by preventing a current path between a high voltage and a ground voltage when the level of an input signal is transited from the level of the ground voltage to the level of a power voltage. CONSTITUTION: A current mirror(21) is connected between a high voltage and first and second nodes. A switch unit(22) switches between a first node and an input node in response to an enabled mode signal in the entry of a deep power down mode. A pull down unit(23) pulls down a second node in response to an input signal. A buffer unit outputs an output signal by buffering a signal of a second node.

Description

Level shifter {LEVEL SHIFTER}

The present invention relates to a level shifter.

In general, level shifters serve as an interface between circuits using different supply voltages. For example, a word line driver of a semiconductor memory device uses a high voltage VPP at a level higher than an externally supplied external voltage VDD. The signal for driving the word line driver is an external voltage. The word line driver needs to swing between high voltage (VPP) and ground voltage (VSS) while swinging between (VDD) and ground voltage (VSS). Therefore, if the circuit is directly connected without level shifting between the two circuits, the leakage current may flow in the circuit using the high voltage (VPP) as the power supply voltage, so the level shifter is used to connect the two circuits.

1 is a circuit diagram of a level shifter according to the prior art.

As shown, a conventional level shifter circuit is a PMOS transistor P11 connected between a high voltage VPP and a node nd11 and acting as a pullup element that pulls up the node nd11 in response to a signal from the node nd12. And a PMOS transistor P12 connected between the high voltage VPP and the node nd12 to operate as a pull-up device that pulls up and drives the node nd12 in response to the signal of the node nd11, and the node nd11 and the node nd11. An NMOS transistor N11 that is connected between the input signal IN and operates as a switch element that receives the power supply voltage VDD and is turned on, and is connected between the node nd12 and the ground voltage VSS, and is input signal IN. In response, the NMOS transistor N12 operates as a pull-down device for driving the node nd12, and the inverter IV11 operates as a buffer for inverting and buffering the signal of the node nd12 and outputting an output signal.

In the level shifter circuit having such a configuration, since the NMOS transistor N11 receives the power supply voltage VDD as the gate, when the input signal IN is the ground voltage VSS, the NMOS transistor N11 is turned on to turn on the PMOS transistor P12. In this state, when the input signal IN transitions from the ground voltage VSS to the power supply voltage VDD, the NMOS transistor N12 is turned on while the PMOS transistor P12 is turned on, thereby causing the high voltage VPP and the ground voltage. A current path is generated between (VSS) to generate a leakage current.

The present invention discloses a level shifter capable of reducing leakage current in deep power down mode.

To this end, the present invention includes a current mirror connected between the high voltage and the first and second nodes; A switch unit configured to switch between the first node and an input node to which an input signal is input in response to a mode signal enabled when entering a deep power down mode; And a pull-down unit configured to pull-down the second node in response to the input signal.

In the present invention, the current mirror unit is connected between the high voltage and the first node, the first pull-up element for driving up the first node in response to the signal of the second node; And a second pull-up element connected between the high voltage and the second node and configured to pull up the second node in response to a signal from the first node.

In the present invention, the switch unit buffers the mode signal; And a switch device connected between the first node and the input node and turned on in response to an output signal of the buffer.

In the present invention, the pull-down unit is connected between the second node and the ground voltage, and preferably includes a pull-down element for driving down the second node in response to the input signal.

Preferably, the level shifter further includes a buffer unit for outputting an output signal by buffering the signal of the second node.

1 is a circuit diagram of a level shifter according to the prior art.
2 is a circuit diagram of a level shifter according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

2 is a circuit diagram of a level shifter according to an embodiment of the present invention.

As shown in Fig. 2, the level shifter of the present embodiment includes a current mirror portion 21, a switch portion 22, a pull-down portion 23 and a buffer portion 24.

The current mirror unit 21 is connected between the high voltage VPP and the node nd21 to operate as a pull-up element that pulls up the node nd21 in response to the signal of the node nd22, and a high voltage. A PMOS transistor P22 connected between the VPP and the node nd22 and acting as a pull-up device that pulls up the node nd22 in response to a signal of the node nd21.

The switch unit 22 is an inverter IV21 operating as a buffer for inverting and buffering the mode signal DPD enabled at the logic high level when entering the deep power down mode, and the node nd21 and the input signal IN are inputted. And an NMOS transistor N21 connected between the input nodes nd23 and turned on in response to an output signal of the inverter IV21. Inverter IV21 may be configured to output an output signal driven at a power supply voltage VDD level at a logic low level input.

The pull-down unit 23 includes an NMOS transistor N22 connected between the node nd22 and the ground voltage VSS to operate as a pull-down device that pulls down the node nd22 in response to the input signal IN.

The buffer unit 24 includes an inverter IV21 that operates as a buffer for inverting and buffering the signal of the node nd22 and outputting an output signal.

The operation of the level shifter circuit having the above configuration will be described, but divided into before and after entering the deep power down mode are as follows.

First, the mode signal DPD before entering the deep power down mode is a logic low level. Accordingly, the inverter IV21 outputs an output signal driven by the power supply voltage VDD, and the NMOS transistor N21 receives a signal driven by the power supply voltage VDD as a gate. In this state, the NMOS transistor N21 and the PMOS PMOS transistor P22 to which the input signal IN of the ground voltage VSS level is input are turned on, and the node nd22 is pulled up. Thereafter, when the input signal IN transitions from the ground voltage VSS level to the power supply voltage VDD level, the NMOS transistor N21 is turned off, the NMOS transistor N22 is turned on, and the node nd22 is pulled down. .

On the other hand, when entering the deep power down mode, the mode signal DPD is enabled to a logic high level. Thus, inverter IV21 outputs an output signal driven at a logic low level to turn off NMOS transistor N21. The NMOS transistor N21 remains turned off regardless of the level of the input signal IN. Therefore, even if the level of the input signal IN is the ground voltage VSS level, the signal of the node nd21 is not driven to the ground voltage VSS and thus does not turn on the PMOS transistor P22, so that the level of the input signal IN is turned on. Even when the NMOS transistor N22 is turned on from the ground voltage VSS level to the power supply voltage VDD level, no current path is generated between the high voltage VPP and the ground voltage VSS.

As described above, the level shifter includes a switch unit which is turned off when entering the deep power-down mode so that the high voltage VPP when the level of the input signal IN transitions from the ground voltage VSS level to the power supply voltage VDD level. ) And the leakage current is blocked by preventing the current path between the ground voltage and ground voltage (VSS).

21: current mirror 22: switch
23: pull-down section 24: buffer section

Claims (5)

A current mirror unit connected between the high voltage and the first and second nodes;
A switch unit configured to switch between the first node and an input node to which an input signal is input in response to a mode signal enabled when entering a deep power down mode; And
And a pull-down unit configured to pull-down the second node in response to the input signal.
The method of claim 1, wherein the current mirror unit
A first pull-up element connected between the high voltage and a first node and configured to pull up the first node in response to a signal of the second node; And
And a second pull-up element connected between the high voltage and a second node and configured to pull up the second node in response to a signal from the first node.
The method of claim 1, wherein the switch unit
A buffer for buffering the mode signal; And
And a switch element connected between the first node and the input node and turned on in response to an output signal of the buffer.
The level shifter of claim 1, wherein the pull-down part includes a pull-down element connected between the second node and a ground voltage and pull-down driving the second node in response to the input signal.
The level shifter of claim 1, further comprising a buffer unit configured to buffer the signal of the second node and output an output signal.

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