KR20120004825A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to secure margin of a global input and output line by optimally setting an activation section of a pipe input signal. CONSTITUTION: A column selection signal generating unit(110) receives a read command signal(RD_CMD). The column selection signal generating unit generates a column selection signal with a pulse width of a read command signal or a column selection signal which is extended than the pulse width of the read command signal in response to a bank grouping mode signal. A pipe input signal generating unit(120) receives a column selection signal outputted from the column selection signal generating unit. The pipe input signal generating unit generates a pipe input signal(RD_PIN) with a pulse width of a column selection signal or a pipe input signal which is reduced than the pulse width of the column selection signal.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device.

Recently, a bank grouping mode is used for a semiconductor memory device that operates at a high speed. The bank grouping mode is a mode that logically groups a plurality of banks and increases a minimum 'tCCD (CAS to CAS Command Delay)' between commands when successive column accesses are made in the same bank group. The purpose of the present invention is to reduce the burden on a semiconductor memory device that operates at a high speed.

In other words, in the bank grouping mode, when sequential column access is made to different bank groups, the minimum 'tCCD' is 2 cycles (2tCK) of the external clock signal between commands, but continuous column access is performed in the same bank group. In this case, the minimum 'tCCD' between commands extends to four cycles (4tCK) of the external clock signal. This is illustrated in Figures 1A and 1B.

FIG. 1A is a timing diagram illustrating a case where successive column accesses are made in the same bank group, and FIG. 1B is a timing diagram illustrating a case where sequential column accesses are made to different bank groups.

In this case, the semiconductor memory device has an eight bank structure as an example. Here, the first to fourth banks are referred to as a first bank group BG0, and the fifth to eighth banks are referred to as a second bank group BG1. Let's assume.

First, referring to FIG. 1A, when continuous column access is performed in the same bank group in the bank grouping mode, for example, column access is performed in the first bank group BG0 and column access is again performed in the first bank group BG0. In this case, the minimum 'tCCD' between commands is guaranteed to be 4 cycles (4tCK) of the external clock signal CLK. In other words, the column selection signal (YI) is activated, the section (1.5tCK) for loading data to the local I / O line (LIO) and the section (2.5tck) for precharging the local I / O line (LIO) Four cycles (4tCK) of the external clock signal CLK are set.

Next, referring to FIG. 1B, when sequential column access is made to different bank groups in the bank grouping mode, for example, column access is made in the first bank group BG0 and column access is made in the second bank group BG1. Is performed, the minimum 'tCCD' is guaranteed between two commands (2tCK) of the external clock signal CLK. That is, the external clock signal CLK includes a section 1.5tCK for activating the column selection signal YI to load data on the local input / output line LIO and a section 0.5tck for precharging the local input / output line LIO. It is set to two cycles (2tCK).

In this case, the column select signal YI in the bank grouping mode is a signal derived from a column command signal such as a read command signal and a write command signal. In other words, the column select signal YI is a signal generated by extending the activation width of the column command signal (eg, 1 tCK), and as shown in FIGS. 1A and 1B, the activation width of the column select signal YI is increased. It can be seen that 1.5 cycles (1.5 tCK) of the external clock signal. This is to ensure sufficient time when loading the amplified data from the bit-line sense amplifier (BLSA) to the local input / output line (LIO).

However, when continuous column access is made within the same bank group (see FIG. 1A), the precharge period is secured as 2.5 cycles (2.5 tCK) of the external clock signal, so that the local input / output line (LIO) can be normally precharged. When sequential column access is made to different bank groups (refer to FIG. 1B), the precharge period may not be properly performed because only 0.5 cycles (0.5 tCK) of the external clock signal are secured.

On the other hand, in the semiconductor memory device, a pipe input signal (not shown) in which an activation width is determined corresponding to the column selection signal YI is used. The pipe input signal is a control signal for latching data carried on the global I / O line (GIO) to the pipe latch circuit. Since the activation width of this pipe input signal expands together as the activation width of the column select signal YI expands, it is unnecessarily extended even though the activation width of the pipe input signal is already sufficient. In this case, there is a problem in that the margin of the global input / output line GIO is degraded.

An object of the present invention is to provide a semiconductor memory device in which a margin of a global input / output line (GIO) is secured while the local input / output line (LIO) is stably precharged.

Another object of the present invention is to generate a column selection signal and a pipe input signal irrespective of an external clock signal to secure a precharge period of a local input / output line (LIO) and a margin of a global input / output line (GIO).

According to an aspect of the present invention, the present invention provides a selection transfer unit for selectively transferring a column command signal in response to a bank grouping mode signal, a delay unit for delaying an output signal of the selection transfer unit by a predetermined delay amount, and a column; And a column select signal output unit for outputting a column select signal in response to an output signal of the command signal and the delay unit.

According to another aspect of the invention, the present invention receives a column command signal having a first pulse width, and the second pulse width having a first pulse width or greater than the first pulse width in response to the bank grouping mode signal A column selection signal generator for selectively generating a column selection signal, and a column selection signal, and receiving a third pulse width having a second pulse width or smaller than the second pulse width in response to the bank grouping mode signal. The branch includes a pipe input signal generator for selectively generating a pipe input signal.

According to the present invention, the activation period of the column selection signal and the precharge period of the local input / output line (LIO) are optimally set so that the data amplified by the bit line detection amplifier BLSA is normally loaded on the local input / output line (LIO). At the same time, the local input / output line (LIO) is stably precharged. At this time, since the activation period of the column selection signal and the precharge period of the local input / output line LIO are set regardless of the external clock signal, there is an effect that can be applied to a high frequency environment.

In addition, the present invention has the effect of ensuring the margin of the global I / O line (GIO) by setting the activation interval of the pipe input signal to the optimum.

1A is a timing diagram showing a case where continuous column access is made in the same bank group during operation of a conventional semiconductor memory device.
1B is a timing diagram illustrating a case where sequential column access is made to different bank groups during operation of a conventional semiconductor memory device.
Fig. 2 is a block diagram for explaining the essential parts of a semiconductor memory device according to the embodiment of the present invention.
FIG. 3A is an internal configuration diagram illustrating an example of the column select signal generator of FIG. 2. FIG.
3B is an internal configuration diagram illustrating an example of the pipe input signal generator of FIG. 2.
FIG. 4A is a timing diagram for describing an operation of the column select signal generator of FIG. 3A. FIG.
4B is a timing diagram for describing an operation of the pipe input signal generator of FIG. 3B.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

In the embodiment of the present invention, a read operation is performed as an example.

2 is a block diagram illustrating a main part of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor memory device 100 receives a read command signal RD_CMD, and has a column width selection signal YI having a pulse width of the read command signal RD_CMD in response to the bank grouping mode signal BG. Or a column select signal generator 110 for generating a column select signal YI extended to a pulse width of the read command signal RD_CMD, and a column select signal output from the column select signal generator 110. Receives the YI and generates a pipe input signal RD_PIN having a pulse width of the column selection signal YI in response to the bank grouping mode signal BG, or reduced to a pulse width of the column selection signal YI. And a pipe input signal generator 120 for generating the pipe input signal RD_PIN. Here, although the column select signal YI is not shown in the figure, the data amplified by the corresponding bit line sense amplifier (BLSA) is transferred to the local I / O line (LIO). The pipe input signal RD_PIN is a signal for controlling the data loaded on the global I / O line (GIO) to be latched in the pipe latch circuit.

3A is a diagram illustrating an internal configuration of an example of the column select signal generator 110 of FIG. 2.

Referring to FIG. 3A, the column select signal generator 110 may include an inverter 112 for inverting the read command signal RD_CMD and an output signal of the inverter 112 in response to the bank grouping mode signal BG. The first selection transfer unit 114 for selectively transmitting the signal, the first delay unit 116 for delaying the output signal of the selection transfer unit 114 by a predetermined delay amount, and the output signal of the inverting unit 112. And a column select signal output unit 118 for outputting a column select signal YI in response to the output signal of the delay unit 116.

The inversion part 112 is comprised with the 1st inverter INV1.

The first selection transfer unit 114 inputs the second inverter INV2 for inverting and outputting the bank grouping mode signal BG, the output signal of the second inverter INV2, and the output signal of the first inverter INV1. The first NOR gate NOR1 receives the negative OR operation and the third inverter INV3 inverts and outputs the output signal of the first NOR gate NOR1.

The first delay unit 116 may be composed of a plurality of inverters. In this case, the delay amount of the plurality of inverters determines the activation width of the column selection signal YI. For example, when column access is sequentially performed to different bank groups in the bank grouping mode, at least 'tCCD (CAS to CAS Command Delay)' corresponds to '2 cycles (2tCK)' of the external clock signal between commands. In the case of continuous column access within the same bank group, the read command signal in the bank grouping mode in a state in which a minimum 'tCCD' between commands is assumed to correspond to '4 cycles (4 tCK)' of the external clock signal. If the activation width of RD_CMD corresponds to one cycle 1tCK of the external clock signal, the activation width of the column select signal YI is greater than the one cycle 1tCK of the external clock signal and is greater than 1.5 cycles (1.5tCK). smaller than tCK). If the activation width of the column select signal YI is determined as '1.3 cycles (1.3tCK)' of the external clock signal, the minimum 'tCCD' is the external clock signal between commands when the column access is sequentially performed in different bank groups. Since it corresponds to the '2 cycle (2tCK)' of, the precharge period can be secured to correspond to the '0.7 cycle (0.7tCK)' of the external clock signal.

The column select signal output unit 118 receives the output signal of the inverter 112 and the output signal of the first delay unit 116 to perform a negative AND operation to output a column select signal YI. It consists of a gate NAND1. The column select signal output unit 118 configured as described above has a column select signal having a pulse width of the read command signal RD_CMD in response to the output signal of the inverter 112 and the output signal of the first delay unit 116. YI) or the column select signal YI that is wider than the pulse width of the read command signal RD_CMD is selectively output.

3B is an internal configuration diagram illustrating an example of the pipe input signal generator 120 of FIG. 2.

Referring to FIG. 3B, the pipe input signal generator 120 may include a second selection transfer unit 122 for selectively transmitting the column selection signal YI in response to the bank grouping mode signal BG, and a second selection transfer unit 122. The second delay unit 124 for delaying and outputting the output signal of the transfer unit 122 by a predetermined delay amount, and the pipe input signal in response to the output signal and the column select signal YI of the second delay unit 124. And a pipe input signal output unit 126 for outputting RD_PIN.

The second select transfer unit 122 receives the fourth inverter INV4 for inverting and outputting the bank grouping mode signal BG, the output signal of the fourth inverter INV4 and the column select signal YI, and performs a negative logic sum. The second NOR gate NOR2 performing the operation and the fifth inverter INV5 which inverts and outputs the output signal of the second NOR gate NOR2.

The second delay unit 124 may be composed of a plurality of inverters, and the delay amount by the plurality of inverters determines the activation width of the pipe input signal RD_PIN.

The pipe input signal output unit 126 receives the column select signal YI and the output signal of the second delay unit 124 and performs a negative AND operation and performs a second NAND gate NAND2 and a second NAND gate ( And a sixth inverter for inverting the output signal of NAND2 and outputting the pipe input signal RD_PIN. The pipe input signal output unit 126 configured as described above has a pipe input signal RD_PIN having a pulse width of the column selection signal YI in response to the output signal of the column selection signal YI and the second delay unit 124. Alternatively, the pipe input signal RD_PIN, which is smaller than the pulse width of the column select signal YI, is selectively output.

Hereinafter, the operation of the semiconductor memory device according to the embodiment of the present invention having the above configuration will be described with reference to FIGS. 4A and 4B.

In the embodiment of the present invention, only the bank grouping mode will be described for convenience of description. In this case, the bank grouping mode is a mode in which a plurality of banks are logically grouped to increase the minimum 'tCCD' between commands when successive column accesses are made in the same bank group. If the minimum 'tCCD' is set to two cycles (2tCK) of the external clock signal between commands, and if the column access is performed continuously in the same bank group, the minimum 'tCCD' is set to four cycles (4tCK) of the external clock signal between commands. An extension will be described as an example.

4A is a timing diagram illustrating the operation of the column select signal generator 110 of FIG. 3A, and FIG. 4B is a timing diagram illustrating the operation of the pipe input signal generator 120 of FIG. 3B. Is shown.

First, referring to FIG. 4A, when the read command signal RD_CMD having the first activation width corresponding to one cycle 1tCK of the external clock signal (not shown) is applied to the inversion unit 112, All 112 output the inverted read command signal A. FIG.

Then, the first selection transfer unit 114 transmits the inverted read command signal A to the first delay unit 116. In more detail, since the bank grouping mode signal BG is a current bank grouping mode, it has a logic high level. That is, the bank grouping mode signal BG is a high active signal. Accordingly, the second inverter INV2 inverts and outputs the logic group-level bank group signal BG, and the first NOR gate NOR1 outputs a logic low level signal to one input terminal-the second inverter INV2. Since the output signal of-is applied, the signal applied to the other input terminal-the inverted read command signal A-is inverted and output. Since the third inverter INV3 inverts and outputs the output signal of the first NOR gate NOR1, the output signal of the second inverter INV3 becomes the same as the inverted read command signal A. FIG.

Accordingly, the first delay unit 116 receives the inverted read command signal A and delays the delayed read command signal B by a predetermined delay amount a. Here, the predetermined delay amount a has a value smaller than 0.5 cycles (0.5 tCK) of the external clock signal.

As a result, the column select signal output unit 118 performs a negative AND operation on the inverted read command signal A and the delayed read command signal B so as to be larger than 1.5 times one cycle (1tCK) of the second activation width-external clock signal. Outputs a column select signal YI having a period-less than 1.5 tCK. Since the column selection signal YI has the second activation width 1tCK <1tCK + a <1.5tCK, the data amplified by the corresponding bit line sense amplifier BLSA is normally applied to the local input / output line LIO. Time is available for loading. In addition, even when sequential column access is made to different bank groups, since the minimum 'tCCD' is 2 cycles (2tCK) of the external clock signal between commands, the pre-except the second activation width (1tCK <1tCK + a <1.5tCK) The charge period is secured larger than 0.5 cycles (0.5tCK) of the external clock signal, so that the precharge operation on the local input / output line (LIO) can be normally performed.

Next, referring to FIG. 4B, the second selection transfer unit 122 receives the applied column selection signal YI as the second column selection signal YI having the second activation width 1tCK + a is applied to the second selection transfer unit 122. Transfer to the delay unit 124. In more detail, the inverter INV4 inverts and outputs the bank grouping mode signal BG having a logic high level. Since the second NOR gate NOR2 receives the logic low level signal-the output signal of the fourth inverter INV4-to one input terminal, the second NOR gate NOR2 inverts the column selection signal YI applied to the other input terminal. To the fifth inverter INV5. Then, the fifth inverter INV5 inverts the output signal of the second NOR gate NOR2 and transmits the inverted signal to the second delay unit 124.

Then, the second delay unit 124 receives the column selection signal YI and delays the predetermined delay amount by outputting the delayed column selection signal C to the pipe input signal output unit 126. In this case, the predetermined delay amount may be the same as or different from the predetermined delay amount a of the first delay unit 124. In the embodiment of the present invention will be described taking the same as an example.

Accordingly, the pipe input signal output unit 126 receives the column selection signal YI and the delayed column selection signal C and outputs the pipe input signal RD_PIN having the third activation width 1tCK. That is, the second NAND gate NAND2 performs a negative AND operation on the column select signal YI and the delayed column select signal C, and the sixth inverter INV6 inverts the output signal of the second NAND gate NAND2. To output the pipe input signal RD_PIN. As such, the pipe input signal RD_PIN set to the optimum activation width is used as a control signal for latching data carried on the global input / output line GIO to the pipe latch circuit, thereby securing a margin of the global input / output line GIO. It becomes possible.

According to the exemplary embodiment of the present invention, the column access operation and the precharge operation may be normally performed in the bank grouping mode, and the margin of the global input / output line GIO d may be secured.

Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

100: semiconductor memory device 110: column select signal generator
112: inversion unit 114: second selection transfer unit
116: first delay unit 118: column select signal output unit
120: pipe input signal generation unit 122: second selection transfer unit
124: second delay unit 126: pipe input signal output unit

Claims (12)

A selection transfer unit for selectively transferring a column command signal in response to the bank grouping mode signal;
A delay unit for delaying the output signal of the selection transfer unit by a predetermined delay amount; And
A column select signal output unit for outputting a column select signal in response to the column command signal and the output signal of the delay unit;
And a semiconductor memory device.
The method of claim 1,
When sequential column access is made to different bank groups in the bank grouping mode, at least 'tCCD (CAS to CAS Command Delay)' corresponds to '2 cycles (2tCK)' of the external clock signal between commands, and within the same bank group. In the case of successive column accesses in the semiconductor memory device, at least 'tCCD' between commands corresponds to '4 cycles (4tCK)' of the external clock signal.
The method of claim 2,
The pulse width of the column command signal in the bank grouping mode corresponds to one cycle (1tCK) of the external clock signal.
The method of claim 2,
The pulse width of the column selection signal in the bank grouping mode is set greater than one cycle (1tCK) and less than 1.5 cycles (1.5tCK) of the external clock signal.
Receiving a column command signal having a first pulse width and selectively generating a column selection signal having the first pulse width or a second pulse width greater than the first pulse width in response to a bank grouping mode signal; A column selection signal generation unit for; And
A pipe input signal for receiving the column selection signal and selectively generating a pipe input signal having a second pulse width or a third pulse width smaller than the second pulse width in response to the bank grouping mode signal; Generator
And a semiconductor memory device.
The method of claim 5,
The column select signal generator,
A first selection transfer unit for selectively transferring the column command signal in response to the bank grouping mode signal;
A first delay unit for delaying the output signal of the first select transfer unit by a predetermined first delay amount; And
And a column select signal output unit configured to output the column select signal in response to an output signal of the column command signal and the first delay unit.
The method of claim 5,
The pipe input signal generator,
A second selection transfer unit for selectively transferring the column selection signal in response to the bank grouping mode signal;
A second delay unit for delaying the output signal of the second select transfer unit by a predetermined second delay amount;
And a pipe input signal output unit configured to output the pipe input signal in response to an output signal of the second delay unit and the column selection signal. The method according to claim 6 or 7,
And the first delay amount and the second delay amount are the same.
The method according to claim 6 or 7,
And the first delay amount and the second delay amount are different from each other.
8. The method according to any one of claims 5 to 7,
When sequential column access is made to different bank groups in the bank grouping mode, at least 'tCCD (CAS to CAS Command Delay)' corresponds to '2 cycles (2tCK)' of the external clock signal between commands, and within the same bank group. In the case of successive column accesses in the semiconductor memory device, at least 'tCCD' between commands corresponds to '4 cycles (4tCK)' of the external clock signal.
The method of claim 10,
The first pulse width corresponds to one cycle (1tCK) of the external clock signal.
The method of claim 10,
The second pulse width is defined as being greater than one cycle (1tCK) and less than 1.5 cycles (1.5tCK) of the external clock signal.

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