KR100924017B1 - Auto precharge circuit and method for auto precharge - Google Patents

Abstract

PURPOSE: A circuit and a method for auto precharge are provided to prevent malfunction of an auto precharge circuit by preventing enabling of the auto precharge circuit corresponding to a CAS command about a different bank. CONSTITUTION: A circuit for auto precharge includes a reserve precharge signal generating part(601), a read precharge control signal generating part(605), a write precharge control signal generating part(602), and a precharge signal generating part(603). The reserve precharge signal generating part is enabled in response to a CAS command about a fixed bank including auto precharge. The reserve precharge signal generating part generates a reserve precharge signal disabled by a read precharge control signal. If a burst operation end signal is enabled in an enable section of the reserve precharge signal, the read precharge control signal generating part generates a read precharge control signal. The write precharge control signal generating part delays the read precharge control signal as a fixed delay value, and enables a write precharge control signal. The precharge signal generating part enables an auto precharge signal in response to the read and write precharge control signal.

Description

AUTO PRECHARGE CIRCUIT AND METHOD FOR AUTO PRECHARGE}

The present invention relates to an auto precharge circuit, and more particularly, to an auto precharge circuit and an auto precharge method capable of preventing malfunction and reducing the layout area.

An operation of accessing data by the semiconductor memory device is an active operation and a read and write operation. The active, read, and write operations may be performed by the semiconductor memory device using an external signal such as a chip select signal (CS), a row address strobe signal (RAS), a column address strobe signal (CAS), and The decoding is performed by receiving a write enable signal WE.

For example, activation is performed when the external signal is / CS low, / RAS low, / CAS high and / WE high. Read operation is performed when the external signal is / CS low, / RAS high, / CAS low and / WE high. The write operation is performed when the external signal is / CS low, / RAS high, / CAS low and / WE low.

The active operation receives a row address from an external source, selects a bank and a word line, and detects and stores data stored in a plurality of memory cells corresponding to the selected word line using a corresponding bit line sense amplifier. The process of amplification.

The read and write operations are operations of outputting data corresponding to a column address to the outside or replacing data input from the outside among a plurality of data signals sensed and amplified by the activation operation. After a read or write operation is performed on the corresponding data, the data latched in the plurality of bit line sense amplifiers are respectively stored in the original memory cells. Since the potential of the bit line may vary when read and write operations are performed, it is necessary to precharge the bit line to a predetermined voltage level after the read and write operations. Therefore, when the restoring of data is completed, a precharge operation for preparing the next activation operation is performed.

The precharge operation may be performed by a precharge command, or may also be performed by auto precharge without a precharge command. Auto precharge is performed based on a read or write command accompanied by auto precharge from an external (e.g., memory controller).

The semiconductor memory device generates an auto precharge signal internally in response to read and write commands. After the read or write operation, the auto precharge operation is performed by the auto precharge signal. Normally, a high level signal is applied to address 10 (address <10>), and auto precharge is involved in read and write commands.

1 is a configuration diagram of an auto precharge circuit according to the prior art.

As shown in the drawing, a conventional auto precharge circuit includes a precharge control unit 101, a clock shift unit 103, a delay unit 105, and a precharge signal generation unit 107.

The precharge control unit 101 receives a casing command CASP8 <0: n> with auto precharge. The CAS command CASP8 <0: n> is a column selection command having information about a bank address for selecting one bank among banks included in the semiconductor memory device and a column address for selecting one of a plurality of columns of the bank. <0: n> means that the semiconductor memory device includes n banks. For example, CASP8 <0: n> is a cas instruction for n banks. CASP8 <m> (0 = <m = <n) has information on the columns of the m th bank. One column is selected in the m-th bank by the column information. In the present specification, a case where n = 3, that is, four banks will be described.

The internal precharge signal A10TBAP is a signal generated inside the semiconductor memory device based on the high level signal at address 10.

The precharge control unit 101 enables the activation signal APCGDETB based on the cas instruction CASP8 <0: 3> and the internal precharge signal A10TBAP. The precharge control unit 101 generates a read precharge control signal NSFTAPCGPB in response to the burst operation end signal YBSTENDBP9. The precharge operation is performed after the read operation by the read precharge control signal NSFTAPCGPB.

The reason why the read precharge control signal NSFTAPCGPB is generated in response to the burst operation end signal YBSTENDBP9 is that a read or write operation is performed together with the burst operation. That is, the precharge control unit 101 generates the read precharge control signal NSFTAPCGPB in response to the burst operation end signal YBSTENDBP9 generated at the end of the burst operation to perform auto precharge after the read operation performed with the burst operation. Be sure to

 Here, the burst operation is an operation for overcoming the constraint of increasing the operating speed of the core region of the semiconductor memory device, and serially processing data processed in parallel in the core region where the operating speed is difficult to increase. It is a fast input / output method. In this regard, the burst length BL refers to the number of data input / output serially at one time.

For example, if the burst length BL is 4, the semiconductor memory device reads 4 bits of data from the memory cell in parallel by a read command, and reads the same 4 bits of data for 2 clock cycles. Output serially through pin (DQ pin).

In addition, the precharge control unit 101 disables the activation signal APCGDETB based on the preliminary signal PREAPCGB enabled by the precharge signal generation unit 107 described later.

The clock shift unit 103 and the delay unit 105 output a write precharge control signal SFTAPCGTB_2 for auto precharge performed after the write operation.

The clock shift unit 103 outputs the delayed read precharge control signal SFTAPCGTB_1 in response to the activation signal APCGDETB and the read precharge control signal NSFTAPCGPB. The delay unit 105 further delays the delayed read precharge control signal SFTAPCGTB_1 according to the CAS latency (CL) mode and outputs the write precharge control signal SFTAPCGTB_2. The reason for delaying the write precharge control signal SFTAPCGTB_2 from the read precharge control signal NSFTAPCGPB is to ensure the write recovery time tWR so that the auto precharge operation is performed.

The write recovery time tWR refers to a time that must be guaranteed from the time of a write command to the time of writing data to a memory cell. Therefore, the write recovery time tWR must be guaranteed after the write operation is completed in the semiconductor memory device and before the auto precharge operation is performed.

The write recovery time tWR varies depending on the cascade latency CL mode. The cascade latency CL is the number of operation clocks until data corresponding to a command input to the semiconductor memory device is output. The larger the CAS latency CL, the longer the write recovery time tWR.

The delay time of the signal by the clock shift unit 103 is a write recovery time tWR which is commonly delayed regardless of various cascade latency CL modes. For example, if the write recovery time tWR is 12 ns when the cascade latency CL is minimum, and the write recovery time tWR is increased by 15 ns each time the cascade latency CL is increased by 1, the clock shift unit 103 The delayed read precharge control signal SFTAPCGTB_1 has a minimum write recovery time tWR in common regardless of the CAS latency mode, that is, a delay amount of 12 ns. The delay unit 105 further delays the read precharge control signal SFTAPCGTB_1 delayed by the remaining amount of delay according to the cascade latency CL mode, and outputs the write precharge control signal SFTAPCGTB_2.

The precharge signal generation unit 107 enables the auto precharge signal APCG. The read / write select signal WT6RD5B is maintained at a high level during a write operation and is maintained at a low level during a read operation. The auto precharge signal APCG responds to the read precharge control signal NSFTAPCGPB during a read operation. It is enabled and enabled in response to the write precharge control signal SFTAPCGTB_2 during the write operation. Meanwhile, the precharge signal generator 107 generates a preliminary signal PREAPCGB and transmits the precharge signal PREAPCGB to the precharge controller 101.

Hereinafter, the auto precharge circuit of the 0th bank (m = 0) will be described as an example.

2 is a detailed block diagram of the precharge control unit 101 of FIG. 1.

The precharge control unit 101 activates 201 for outputting an activation signal APCGDETB <0> for determining the enable time of the preliminary precharge signal EN_PULSE, and within the enable period of the preliminary precharge signal EN_PULSE. The preliminary signal PREAPCGPB generated by the read precharge control signal generator 203 and the precharge signal generator 107 that generate the read precharge control signal NSFTAPCGPB <0> in response to the burst operation end signal YBSTENDBP9. And reset means 205 for disabling the precharge control unit 101 based on < 0 >.

The enable section of the preliminary precharge signal EN_PULSE is a section in which the precharge control unit 101 can generate the read precharge control signal NSFTAPCGPB. That is, it means a predetermined logical level section of the node A to enable the read precharge control signal NSFTAPCGPB in response to the node B logical level.

The high level casing command CASP8 <0> and the internal precharge signal A10TBAP turn on the NMOS transistors T1 and T2 of the activating means 201 to bring the activation signal APCGDETB <0> low. Able. The enable state of the activation signal APCGDETB <0> is maintained by the latch 207 even when the NMOS transistors T1 and T2 are turned off by the low level casing command CASP8 <0>. The activation signal APCGDETB <0> is disabled to the high level by the reset means 205. The NOR gate 211 maintains the logic level of the node A high based on the activation signal APCGDETB <0> through the delay line 209 and the activation signal APCGDETB <0> without passing through the delay line 209. Let's do it. As a result, the preliminary precharge signal EN_PULSE is enabled. As will be described later, if the delay amount of the delay line 209 is one clock cycle of the internal clock CLKP4 of the semiconductor memory device, the preliminary precharge signal EN_PULSE is enabled and the internal signal (PCCDETB <0>) is enabled. Enabled after one clock cycle of CLKP4).

Except in the parallel test mode described below, the cas instruction (CASP8 <1: 3>) for the remaining banks is not enabled while the cas instruction (CASP8 <0>) for the 0th bank is enabled at a high level. Do not. Therefore, the output of the NOR gate 213 is high level. Therefore, the inverter 217 outputs a high level signal. Thereafter, the NAND gate 219 outputs a high level pulse signal to the node B by the burst operation end signal YBSTENDBP9 enabled at the low level at the end of the burst operation. The read precharge control signal NSFTAPCGPB <0> is performed by the NAND gate 221 while the node A remains high, that is, when the level of the node B becomes high while the preliminary precharge signal EN_PULSE is enabled. Is enabled at low level.

On the other hand, the parallel test signal TPARA is a signal enabled to a high level in the parallel test mode. In the parallel test mode, the read precharge generating unit 203 may enable the read precharge control signal NSFTAPCGPB <0> after the burst operation is terminated by the parallel test signal TPARA. In parallel test mode, the cas instruction (CASP8 <1: 3>) for the remaining banks is also enabled to test all banks. Therefore, in the parallel test mode, the output of the NOR gate 213 is at a low level. At this time, if the parallel test signal TPARA is enabled at a high level, the node B becomes low level by the NAND gate 219 before the burst operation ends, and then, in response to the burst operation end signal YBSTENDBP9, the node B becomes high level. The read precharge control signal NSFTAPCGPB <0> is enabled to the low level.

On the other hand, when not in the parallel test mode, that is, when the parallel test signal TPARA is at the low level, the casing command CASP8 <1: 3> for the other bank is read precharge control signal NSFTAPCGPB even if the low level is not enabled at the low level. <0>) can be enabled at a low level.

In some cases, the casing command CASP8 <0> for the first bank and the casp command CASP8 <1> for the first bank are continuously enabled. In this case, before the burst operation end signal YBSTENDBP9 for the 0th bank is enabled, that is, before the burst operation is terminated, the casing command CASP8 <1> for the first bank is enabled. At this time, in response to the casing command CASP8 <1> for the first bank, the output of the NOR gate 213 becomes low level and the node B becomes low level, so even if the burst operation end signal YBSTENDBP9 is not enabled, read-free The charge control signal NSFTAPCGPB <0> may be enabled at a low level.

The pulse generator 223 generates a pulse signal having a low level for a predetermined period based on the preliminary signal PREAPCGB <0> enabled by the precharge signal generation unit 107 described later. The low level pulse signal generated by the pulse generator 223 is input to the PMOS transistor T3 of the reset means 205 to turn on the PMOS transistor T3.

When either the casing command CASP <0> and the internal precharge signal A10TBAP are disabled, the activation signal APCGDETB <0> is disabled to the high level by the supply voltage VPERI and is preliminary pre-free at node A. The charge signal EN_PULSE is disabled to a low level.

3 is a detailed block diagram of the clock shift unit 103 of FIG. 1.

The PMOS transistor T4 is turned on by the read precharge control signal NSFTAPCGPB <0> enabled to low level and outputs a high level pulse signal. The latch 301 stores the output level of the PMOS transistor T4 and inverts the output level of the PMOS transistor T4 and outputs the inverted output level. The pass gate 307 is turned on by the semiconductor memory device internal clock CLKP4 and is turned on later than the enable timing of the read precharge control signal NSFTAPCGPB <0>, and transmits the output of the latch 301. The latch 309 stores the output signal of the pass gate 307 until the NMOS transistor T7 is turned on by the internal clock CLKP4, and inverts the output level of the pass gate 307.

The NMOS transistor T7 is turned on by the internal clock CLKP4 delayed from the turn-on timing of the pass gate 307. At this time, the NMOS transistor T6 connected in series with the NMOS transistor T7 is also turned on so that the NMOS transistors T6 and T7 output a low level.

The output signals of the NMOS transistors T6 and T7 are output as pulse signals by the latch 311 and the pulse generator 313, and thus the clock shift unit 103 is delayed than the read precharge control signal NSFTAPCGPB <0>. Output the read precharge control signal SFTAPCGPB_1 <0>. The delayed read precharge control signal SFTAPCGPB_1 <0> is a low level enable signal similarly to the read precharge control signal NSFTAPCGPB <0>.

The delay unit 105 further delays the read precharge control signal SFTAPCGPB_1 <0> delayed by the delay amount according to the cascade latency CL mode and outputs the write precharge control signal SFTAPCGPB_2 <0>.

On the other hand, the delay line 303 determines the timing at which the pass gate 307 and the NMOS transistor T7 are turned on so that the read precharge control signal NSFTAPCGPB <0> is delayed.

4 is a detailed configuration diagram of the precharge signal generation unit 107 of FIG. 1.

The precharge signal generation unit 107 includes read / write selection means 401, preliminary signal generation means 402, and precharge signal generation means 403.

The read / write select signal WT6RD5B is maintained at a high level during a write operation and is maintained at a low level during a read operation. The passgate 409 is controlled on / off by the cas instruction CASP8 <0> and the internal precharge signal A10TBAP so that the auto precharge circuit is operated, i.e., the cas instruction CASP8 <0> and The passgate 409 remains turned on while the internal precharge signal A10TBAP is enabled at a high level. The read / write select signal WT6RD5B is transmitted to the preliminary signal generating means 402 by the pass gate 409 in the turned-on state. The latch 411 stores the read / write select signal WT6RD5B, and inverts the read / write select signal WT6RD5B and outputs the inverted read / write select signal WT6RD5B.

First, when the read / write select signal WT6RD5B is at a low level, that is, when the semiconductor memory device performs a read operation, the operation of the preliminary signal generator 402 will be described.

The NAND gate 415 outputs a high level signal regardless of the logic level of the write precharge control signal SFTAPCGPB_2 <0> by the read / write select signal WT6RD5B input at a low level. The NAND gate 413 inverts and outputs the level of the read precharge control signal NSFTAPCGPB <0> to the read / write select signal WT6RD5B input at a high level.

The NAND gate 419 outputs the read precharge control signal NSFTAPCGPB <0> as a preliminary signal PREAPCGB <0> by the output signal of the NAND gate 415 input at the high level. The preliminary signal PREAPCGB <0> is a signal enabled at a low level like the read precharge control signal NSFTAPCGPB <0>.

The operation of the preliminary signal generating means 402 when the read / write selection signal WT6RD5B is at a high level, that is, when the semiconductor memory device performs a write operation, will be described.

 The NAND gate 413 outputs a high level signal regardless of the logic level of the read precharge control signal NSFTAPCGPB <0> by the read / write select signal WT6RD5B input at a low level. The NAND gate 415 inverts and outputs the level of the write precharge control signal SFTAPCGPB_2 <0> by the read / write select signal WT6RD5B input at a high level.

The NAND gate 419 outputs the write precharge control signal SFTAPCGPB_2 <0> as a preliminary signal PREAPCGB <0> by the output signal of the NAND gate 413 input at the high level. The preliminary signal PREAPCGB <0> is a signal enabled at a low level like the write precharge control signal SFTAPCGPB_2 <0>.

In summary, when the semiconductor memory device performs a read / write operation, the preliminary signal generating means 402 responds to the read precharge control signal NSFTAPCGPB <0> or the write precharge control signal SFTAPCGPB_2 <0>. The preliminary signal PREAPCGB <0> is enabled at a low level.

The precharge signal PREAPCGB <0> and the power up signal PWRUP are input to the SR latch 421 by the precharge signal generating means 403. The power-up signal PWRUP is a signal that is maintained at a high level during the operation of the semiconductor memory device. Since the preliminary signal PREAPCGB <0> is a low level enable pulse signal, the SR latch 421 maintains a high level after the low level of the preliminary signal PREAPCGB <0> and outputs the result to the NAND gate 425. .

The TRASMINB signal is a signal for guaranteeing a low active time tRAS and is enabled at a low level after a minimum low active time tRAS has elapsed. When the TRASMINB signal inverted by the inverter 423 and input to the NAND gate 425 is enabled at low level, the NAND gate 425 outputs the SR latch 421 output signal by the TRASMINB signal enabled at the low level. The output is inverted and thus the preliminary signal PREAPCGB <0> is transmitted to the pulse generator 429. The pulse generator 429 and the inverter 431 output an auto precharge signal APCG <0> enabled to a high level based on the preliminary signal PREAPCGB <0>.

In a semiconductor memory device, for example, when a low active command for activating a memory cell for a read operation is applied, a read operation is performed on data stored in the memory cell, and the same data as the read data is stored again in the memory cell. After the restoring process is performed, the transition to the precharge state. However, when the precharge operation is performed too quickly, a problem arises in that data in the memory cell may not be stored sufficiently in the capacitor during the restoring process, resulting in a loss of data. (tRAS). The TRASMINB signal is a signal for guaranteeing a minimum low active time (tRAS) enough to detect and amplify and restore data of a memory cell in order to perform an auto precharge operation properly.

In summary, the auto precharge signal APCG <0> is enabled in response to the read precharge control signal NSFTAPCGPB <0> during the read operation of the semiconductor memory device, and the read precharge control signal during the write operation of the semiconductor memory device. The auto precharge signal APCG <0> is enabled by the write precharge control signal SFTAPCGPB_2 <0> which is delayed from the NSFTAPCGPB <0>.

5 is a timing diagram illustrating an operation of an auto precharge circuit according to the prior art.

FIG. 5 illustrates a case in which an auto precharge signal APCG is enabled during a write operation, in which a write command accompanying auto precharge is input to the 0th, 1st, and 2nd banks, and a casing command (CASP8 <) for the 1st, 2nd banks. 1: 2>) are continuously enabled. In addition, the burst length BL is 4 so that the burst operation is performed for two clock cycles of the internal clock CLKP4 of the semiconductor memory device.

The internal precharge signal A10T8AP is enabled and input to the precharge control unit 101 of the auto precharge circuit of the 0th bank together with the casing command CASP8 <0> for the 0th bank. In response, the activation signal APCGDETB <0> is enabled at a low level. If the delay amount of the delay line 209 is one clock cycle of the internal clock CLKP4, the preliminary precharge signal EN_PULSE is enabled after the activation signal APCGDETB <0> and one clock cycle of the internal clock CLKP4. do.

When the burst operation is performed for two clock cycles of the semiconductor memory device CLKP4 and the burst operation end signal YBSTENDBP9 is enabled at the low level after the burst operation is completed, the read precharge control signal NSFTAPCGPB <0> is low level. Is enabled.

The write precharge control signal SFTAPCGTB_2 <0> is delayed by the clock shift unit 103 and the delay unit 105 in order to ensure the write recovery time tWR, and is greater than the read precharge control signal NSFTAPCGPB <0>. Is enabled late. Since the write command is input, the precharge signal generation unit 107 enables the preliminary signal PREAPCGPB <0> to a low level in response to the write precharge control signal SFTAPCGTB_2 <0>, and the auto precharge signal APCG < 0>) to the high level. The preliminary signal PREAPCGB <0> is fed back to the precharge control unit 101 to disable the activation signal APCGDETB <0> to a high level.

The first bank auto precharge circuit also operates through a process similar to the above process. However, the casing instructions CASP8 <1: 2> for the first and second banks are continuously enabled so that the burst operation end signal YBSTENDBP9 is not enabled. In this case, when the burst operation end signal YBSTENDBP9 is enabled, the precharge operation is performed before the burst operation is completed in the second bank. Therefore, the first bank auto precharge circuit enables the read precharge control signal NSFTAPCGPB <1> in response to the cas instruction CASP8 <2> for the second bank.

On the other hand, the casing command CASP8 <2> for two banks is also input to the precharge control unit 101 of the 0th bank auto precharge circuit. In the precharge control unit 101 that receives the casing command CASP8 <2> for the second bank, the output of the knock gate 213 becomes a low level. Therefore, the node B goes high by the NAND gate 219 and the read precharge control signal NSFTAPCGPB <0> is enabled since the preliminary precharge signal EN_PULSE is not yet disabled. As a result, even though the auto precharge is performed after the write operation in the 0th bank, an error in which the auto precharge operation is performed again occurs.

As described above, in the case of the auto precharge circuit according to the related art, before the activation signal is disabled, that is, before the precharge control unit is disabled, the auto precharge operation is performed again in the bank in which the auto precharge operation has already been performed by the cas command for another bank. There is a problem that a malfunction occurs in which the precharge operation is performed.

The present invention has been proposed to solve the above problems, and provides an auto precharge circuit and an auto precharge method which can prevent malfunction of the auto precharge circuit and reduce the layout area by reducing the use of delay means in the auto precharge circuit. Its purpose is to.

The present invention for achieving the above object is a preliminary precharge that is enabled in response to a cas command for a given bank with auto precharge and generates a preliminary precharge signal that is disabled by a feedback read precharge control signal. A signal generator; A read precharge control signal generation unit configured to generate the read precharge control signal enabled when the burst operation end signal is enabled within the enable period of the preliminary precharge signal; A write precharge control signal generation unit configured to enable the write precharge control signal by delaying the read precharge control signal by a predetermined delay value; And a precharge signal generator for enabling an auto precharge signal in response to the read and write precharge control signals.

In addition, the present invention for achieving the above object is a preliminary precharge that is enabled in response to a cas command for a given bank with auto precharge, and generates a preliminary precharge signal that is disabled by a feedback read precharge control signal. Generating a charge signal; A read precharge control signal generation step of generating the read precharge control signal enabled when the burst operation end signal is enabled within the enable period of the preliminary precharge signal; A write precharge control signal generation step of enabling the write precharge control signal by delaying the read precharge control signal by a predetermined delay value; And a precharge signal generation step of enabling an auto precharge signal in response to the read and write precharge control signals.

According to the present invention, the auto precharge circuit can be prevented from being enabled in response to a casing command to another bank, thereby preventing the auto precharge circuit from malfunctioning, and reducing the use of delay means in the auto precharge circuit. The layout area and power consumption of the charge circuit can be reduced.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

6 is a configuration diagram of an auto precharge circuit according to an embodiment of the present invention.

As shown in the figure, the auto precharge circuit according to the present invention is enabled in response to a cas command (CASP) for a predetermined bank with auto precharge, and is discharged by the feedback read precharge control signal NSFTAPCGPB. A preliminary precharge signal generator 601 for generating a preliminary precharge signal EN_PULSE enabled; A read precharge control signal generation unit 605 for generating a read precharge control signal NSFTAPCGPB enabled when the burst operation end signal YBSTENDBP9 is enabled within the enable period of the preliminary precharge signal EN_PULSE; A write precharge control signal generation unit 602 for delaying the read precharge control signal NSFTAPCGPB by a predetermined delay value to enable the write precharge control signal SFTAPCGPB_2; And a precharge signal generation unit 603 that enables the auto precharge signal (APCG) in response to the read and write precharge control signals NSFTAPCGPB and SFTAPCGPB_2.

The preliminary precharge signal generation unit 601 includes: activating means 604 for outputting an activation signal APCGDETB for determining an enable time of the preliminary precharge signal EN_PULSE; Preliminary precharge signal delay means 613 for delaying the activation signal APCGDETB and outputting a preliminary precharge signal EN_PULSE; And reset means 609 receiving the read precharge control signal NSFTAPCGPB and disabling the activation signal APCGDETB.

In the prior art, the precharge controller 101 receives the preliminary signal PREAPCGBP generated by the precharge signal generator 107 and feeds back the feedback signal to disable the activation signal APCGDETB. When the enable signal APCGDETB is disabled by feeding back the read precharge control signal NSFTAPCGPB, the enable signal APCGDETB is disabled and the preliminary precharge signal EN_PULSE is disabled to read the precharge control signal. This is because the width of the enable period of the NSFTAPCGPB), that is, the pulse width could not be sufficiently secured. In addition, when disabling the activation signal APCGDETB by feeding back the write precharge SFTAPCGPB_2, the activation signal APCGDETB cannot be disabled immediately after the auto precharge operation is performed after the read operation.

Therefore, in the prior art, the activation signal APCGDETB is disabled by feeding back the preliminary signal PREAPCGB. However, the timing at which the preliminary signal PREAPCGB is enabled according to a read or write operation of the semiconductor memory device is different. In addition, the write recovery time tWR is changed according to the cascade latency CL mode during the write operation of the semiconductor memory device, and thus the enable timing of the write precharge control signal SFTAPCGPB_2 is changed, and the enable timing of the preliminary signal PREAPCGB is also changed. Is changed.

As a result, the enable section of the preliminary precharge signal EN_PULSE is wide and fluctuates. As a result, the auto precharge signal APCG is enabled when inputting a cas instruction to another bank. .

However, the auto precharge circuit according to the present invention prevents the preliminary precharge signal EN_PULSE from being immediately disabled even when the activation signal APCGDETB is disabled by receiving the read precharge control signal NSFTAPCGPB. (NSFTAPCGPB) to receive feedback. To this end, the auto precharge circuit according to the present invention delays the activation signal APCGDETB and also delays the preliminary precharge signal EN_PULSE so that the preliminary precharge signal EN_PULSE is immediately disabled by the read precharge control signal NSFTAPCGPB. To prevent it.

That is, even if the activation signal APCGDETB is directly disabled by the read precharge control signal NSFTAPCGPB, the preliminary precharge signal EN_PULSE is immediately generated because the activation signal APCGDETB is delayed to generate the preliminary precharge signal EN_PULSE. Since it is not disabled, the width of the enable period of the read precharge control signal NSFTAPCGPB, that is, the pulse width, can be sufficiently ensured. In other words, the width of the enable period of the read precharge control signal NSFTAPCGPB is determined by the delay value of the preliminary precharge signal generator 601.

Accordingly, the auto precharge circuit according to the present invention can determine the disable timing of the preliminary precharge signal EN_PULSE by the read precharge control signal NSFTAPCGPB regardless of the read or write operation of the semiconductor memory device. It is possible to reduce the width of the enable interval of (EN_PULSE) and keep it constant. In addition, the auto precharge circuit according to the present invention can solve the problem of the related art, which has a wide width of the enable period of the preliminary precharge signal EN_PULSE and malfunctions due to a cas instruction to another bank.

Hereinafter, a specific operation process of the present invention will be described as an example of the auto precharge circuit for the 0th bank. The difference with the prior art will be described.

The activation means 604 and the reset means 609 of the preliminary precharge signal generation unit 601 have the same operation process as the activation means 201 and the reset means 205 of the prior art. The preliminary precharge signal delay means 613 includes a plurality of latches 611, 617, 621; And a plurality of passgates 615 and 619 that are alternately connected in series with the plurality of latches 611, 617, and 621 and turned on in response to the semiconductor device internal clock CLKP4. The preliminary precharge signal delay means 613 delays the activation signal APCGDETB <0> in synchronization with the internal clock CLKP4 of the semiconductor memory device.

Each of the plurality of passgates 615 and 619 is turned on in response to a different logic level of the internal clock CLKP4 of the semiconductor device. That is, when the passgate 615 is turned on, the passgate 619 is turned off, and when the passgate 619 is turned on, the passgate 615 is turned off so that the activation signal APCGDETB <0> is internally clocked CLKP4. Delay in synchronization with At this time, the latches 611, 617, and 621 are connected to the input / output terminals of the plurality of passgates 615 and 619 to store the activation signal APCGDETB <0> until each of the plurality of passgates 615 and 619 is turned on. It is.

In the synchronous semiconductor memory device, since the input / output of data is performed in synchronization with the internal clock CLKP4 of the semiconductor memory device, the delay of the activation signal APCGDETB <0> in synchronization with the semiconductor device memory CLKP4 is delayed. Improve the reliability of the device.

The activation signal APCGDETB <0> is delayed by the preliminary precharge signal delaying means 613 and is delayed from the enable time of the activation signal APCGDETB <0> at the node NET130, thereby preliminary precharge signal EN_PULSE <0>. Is enabled. In the enable period of the preliminary precharge signal EN_PULSE <0>, the read precharge control signal NSFTAPCGPB <0> is enabled at a low level, and the read precharge control signal NSFTAPCGPB <0> is reset means 609. ) To disable the activation signal APCGDETB <0>. Since the activation signal APCGDETB <0> is delayed by the preliminary precharge signal delaying means 613, the preliminary precharge signal EN_PULSE <0> is delayed later than the disable time of the activation signal APCGDETB <0> at the node NET130. ) Is disabled.

Therefore, even when the read precharge control signal NSFTAPCGPB <0> is enabled, the preliminary precharge signal EN_PULSE <0> is not immediately disabled, and the preliminary precharge signal EN_PULSE <0> remains enabled. The pulse width of the read precharge control signal NSFTAPCGPB <0> is also guaranteed. In addition, the enable period of the preliminary precharge signal EN_PULSE <0> is reduced as compared with the related art, thereby reducing malfunction caused by the cas instruction CASP8 <1: 3> for other banks.

On the other hand, in the enable period of the preliminary precharge signal EN_PULSE <0> of the node NET130, the node NET66 when the cas instruction CASP8 <1: 3> or the burst operation termination signal YBSTENDBP9 for another bank is enabled. Is enabled at a high level and thus the read precharge control signal NSFTAPCGPB <0> is enabled. A detailed description of enabling node NET66 is described in the Background section and will be omitted.

The clock shift means 607 of the write precharge control signal generator 602 corresponds to the conventional clock shift unit 103. The delay line 625 has the same operation principle as the preliminary precharge signal delay unit 613. Do. The write precharge control signal generation unit 602 delays the read precharge control signal NSFTAPCGPB <0> to ensure the time required for the write operation, that is, to guarantee the write recovery time tWR. Generate the signal SFTAPCGPB_2 <0>.

The clock shift means 607 applies the read precharge control signal NSFTAPCGPB <0>.

Delay and transfer to the delay means 631. The read precharge control signal NSFTAPCGPB <0> delayed by the delay line 625 and the internal memory clock CLKP4 of the semiconductor memory device are combined at the OR gates 627 and 629 and the OR gates 627 and 629 are read precharges. A signal having the same waveform as the control signal NSFTAPCGPB <0> is output to the delay means 631. The delay means 631 corresponds to the delay unit 105 described in the background section, and performs a delay operation according to the cascade latency CL mode.

Subsequently, the process of enabling the auto precharge signal APCG <0> is the same as that described in the background art.

As shown in the figure, the preliminary precharge signal generation unit 601 and the clock shift means 607 according to the present invention do not use a plurality of delay lines unlike the prior art. Therefore, the present invention has an advantage of reducing the layout area.

7 is a timing diagram showing the overall operation of the present invention.

FIG. 7 illustrates a case in which an auto precharge signal APCG is enabled during a write operation, in which a write command accompanying an internal precharge signal A10T8AP is input to the first, second, and second banks, and a casing for the first and second banks. The instructions CASP8 <1: 2> are subsequently enabled. In addition, the burst length BL is 4 to perform a burst operation for two clock cycles of the internal clock CLKP4 of the semiconductor memory device.

The internal precharge signal A10T8AP is enabled and input to the read precharge control unit 601 of the 0th bank auto precharge circuit along with the casing command CASP8 <0> for the 0th bank to a high level. In response, the activation signal APCGDETB <0> is enabled at a low level. The activation signal APCGDETB <0> is delayed by the preliminary precharge signal delaying means 613 and is delayed from the enable time of the activation signal APCGDETB <0> at the node NET130, thereby preliminary precharge signal EN_PULSE <0>. Is enabled. For example, if the activation signal APCGDETB <0> is delayed by one clock of the internal clock CLKP4 by the preliminary precharge signal delaying means 613, the preliminary precharge signal EN_PULSE <0> is activated by the activation signal APCGDETB <0. After>) is enabled, it is delayed by one clock of the internal clock CLKP4 and enabled.

When the burst operation is performed during two clock cycles of the internal clock CLKP4 and the burst operation end signal YBSTENDBP9 is enabled at the low level after the burst operation is completed, the read precharge control signal NSFTAPCGPB <0> is enabled at the low level. do.

The read precharge control signal NSFTAPCGPB <0> is fed back to the reset means 609 to disable the activation signal APCGDETB <0>. Since the activation signal APCGDETB <0> is delayed by the preliminary precharge signal delaying means 613, the preliminary precharge signal EN_PULSE <0> is delayed by the node NET130 later than the disable time of the activation signal APCGDETB <0>. Is disabled. For example, if the activation signal APCGDETB <0> is delayed by one clock of the internal clock CLKP4 by the preliminary precharge signal delaying means 613, the preliminary precharge signal EN_PULSE <0> is activated by the activation signal APCGDETB <0. >) Is disabled and delayed by one clock of the internal clock CLKP4 is disabled. Therefore, while the read precharge control signal NSFTAPCGPB <0> is enabled, the preliminary precharge signal EN_PULSE <0> remains enabled, so the pulse width of the read precharge control signal NSFTAPCGPB <0> is Guaranteed.

Thereafter, the process of generating the write precharge control signal SFTAPCGPB_2 <0> and the enabling of the auto precharge signal APCG are the same as in the operation of the prior art.

On the other hand, the cas instruction for the first bank (CASP8 <1>) and the cas instruction for the second bank (CASP8 <2>) are enabled in succession, and the cas instruction for the second bank (CASP8 <2>) is read. When input to the precharge control signal generation unit 601, the node NET66 becomes high level. However, since the preliminary precharge signal EN_PULSE <0> is disabled when the cas command CASP8 <2> is input to the second bank, the read precharge control signal NSFTAPCGPB <0> is not enabled. That is, in the auto precharge circuit according to the present invention, unlike the prior art, the enable period of the preliminary precharge signal EN_PULSE <0> is reduced so that the auto precharge circuit does not malfunction due to the cas instruction CASP8 <2> for the second bank. .

Although the above has been described by the apparatus point of view of the present invention, the operation of each component constituting the auto precharge circuit according to the present invention can be easily understood from the process point of view. Therefore, the operation of each component constituting the auto precharge circuit of the present invention can be understood as each step of configuring the auto precharge method according to the principles of the present invention. Explain how to charge.

The auto precharge method according to the present invention includes a preliminary precharge signal generation step, a read precharge control signal generation step, a write precharge control signal generation step and a precharge signal generation step. The preliminary precharge signal generation step is enabled in response to a cas command (CASP) for a predetermined bank with auto precharge, and is preliminary precharge signal EN_PULSE disabled by the feedback read precharge control signal NSFTAPCGPB. ) The read precharge control signal generation step generates a read precharge control signal NSFTAPCGPB which is enabled when the burst operation end signal YBSTENDBP9 is enabled within the enable period of the preliminary precharge signal EN_PULSE. The write precharge control signal generation step enables the write precharge control signal SFTAPCGPB_2 by delaying the read precharge control signal NSFTAPCGPB by a predetermined delay value. The precharge signal generation step enables the auto precharge signal APCG in response to the read and write precharge control signals NSFTAPCGPB and SFTAPCGPB_2.

The preliminary precharge signal generation step may include: an activation signal generation step of outputting an activation signal APCGDETB for determining an enable time of the preliminary precharge signal EN_PULSE; A preliminary precharge signal delay step of delaying the activation signal APCGDETB to generate a preliminary precharge signal EN_PULSE; And a reset step of receiving the read precharge control signal NSFTAPCGPB and disabling the activation signal APCGDETB.

The auto precharge method according to the present invention prevents the preliminary precharge signal EN_PULSE from being immediately disabled even when the activation signal APCGDETB is disabled by receiving the read precharge control signal NSFTAPCGPB. NSFTAPCGPB) to receive feedback. To this end, the auto precharge method according to the present invention delays the activation signal APCGDETB and thus also delays the preliminary precharge signal EN_PULSE so that the preliminary precharge signal EN_PULSE is not immediately disabled and thus the read precharge control signal NSFTAPCGPB. The width of the enable period, i.e., the pulse width, can be sufficiently ensured. In other words, the width of the enable period of the read precharge control signal NSFTAPCGPB is determined by the delay value of the preliminary precharge signal generation step.

Therefore, the auto precharge method according to the present invention can determine the disable timing of the precharge signal EN_PULSE by the read precharge control signal NSFTAPCGPB regardless of the read or write operation of the semiconductor memory device, thereby preliminary precharge signal. It is possible to reduce the width of the enable interval of (EN_PULSE) and keep it constant. In addition, the auto precharge method according to the present invention can solve the problem of the prior art, which has a wide range of the enable period of the preliminary precharge signal EN_PULSE, which is malfunctioned by a cas instruction to another bank.

Although the present invention has been described by means of limited embodiments and drawings, the present invention is not limited thereto and is intended to be equivalent to the technical idea and claims of the present invention by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible.

1 is a configuration diagram of an auto precharge circuit according to the prior art,

2 is a detailed configuration diagram of the precharge control unit of FIG. 1;

3 is a detailed configuration diagram of a clock shift unit of FIG. 1;

4 is a detailed configuration diagram of the precharge signal generation unit of FIG. 1;

5 is a timing diagram showing an operation of an auto precharge circuit according to the prior art;

6 is a configuration diagram of an auto precharge circuit according to an embodiment of the present invention;

7 is a timing diagram showing the overall operation of the present invention.

Claims (10)

A preliminary precharge signal generation unit that is enabled in response to a cas command for a predetermined bank with auto precharge and generates a preliminary precharge signal disabled by a feedback read precharge control signal; A read precharge control signal generation unit configured to generate the read precharge control signal enabled when the burst operation end signal is enabled within the enable period of the preliminary precharge signal; A write precharge control signal generation unit configured to enable the write precharge control signal by delaying the read precharge control signal by a predetermined delay value; And A precharge signal generation unit for enabling an auto precharge signal in response to the read and write precharge control signals. Auto precharge circuit comprising a. The method of claim 1, The width of the enable period of the read precharge control signal is Determined by the delay value of the preliminary precharge signal generator Auto precharge circuit. The method of claim 1, The preliminary precharge signal generator, Activation means for outputting an activation signal for determining an enable time of the preliminary precharge signal; Preliminary precharge signal delay means for delaying the activation signal and outputting the preliminary precharge signal; And Reset means for disabling the activation signal in response to the read precharge control signal; Auto precharge circuit comprising a. The method of claim 3, wherein The preliminary precharge signal delay means includes: A plurality of latches; And A plurality of passgates alternately connected in series with the plurality of latches and turned on in response to internal clocks of the semiconductor memory device; Including The delay of the activation signal is synchronized with the internal clock. Auto precharge circuit. The method of claim 1, The read precharge control signal generator, When the burst operation end signal is not enabled, the read precharge control signal is enabled in response to a cas instruction for a bank other than the predetermined bank. Auto precharge circuit. The method of claim 1, The predetermined delay value is Delay to ensure the time required for the write operation, Auto precharge circuit. The method of claim 1, The write precharge control signal generator, A plurality of latches; And A plurality of passgates alternately connected in series with the plurality of latches and turned on in response to internal clocks of the semiconductor memory device; Including The delay of the read precharge control signal is synchronized with the internal clock. Auto precharge circuit. A preliminary precharge signal generation step of generating a preliminary precharge signal that is enabled in response to a cas command for a predetermined bank with auto precharge and is disabled by a feedback read precharge control signal; A read precharge control signal generation step of generating the read precharge control signal enabled when the burst operation end signal is enabled within the enable period of the preliminary precharge signal; A write precharge control signal generation step of enabling the write precharge control signal by delaying the read precharge control signal by a predetermined delay value; And A precharge signal generation step of enabling an auto precharge signal in response to the read and write precharge control signals Auto precharge method comprising a. The method of claim 8, The width of the enable period of the read precharge control signal is Determined by the delay value of the preliminary precharge signal generation step Auto precharge method. The method of claim 8, The preliminary precharge signal generation step, An activation signal generation step of outputting an activation signal for determining an enable time point of the preliminary precharge signal; A preliminary precharge signal delay step of delaying the activation signal to generate the preliminary precharge signal; And A reset step of disabling the activation signal in response to the read precharge control signal; Auto precharge method comprising a.

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