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KR20110118948A - Passive component-stacked semiconductor chip, 3-dimensional multi-chip and 3-dimensional multi-chip package having the same - Google Patents

Passive component-stacked semiconductor chip, 3-dimensional multi-chip and 3-dimensional multi-chip package having the same Download PDF

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Publication number
KR20110118948A
KR20110118948A KR1020100038369A KR20100038369A KR20110118948A KR 20110118948 A KR20110118948 A KR 20110118948A KR 1020100038369 A KR1020100038369 A KR 1020100038369A KR 20100038369 A KR20100038369 A KR 20100038369A KR 20110118948 A KR20110118948 A KR 20110118948A
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South Korea
Prior art keywords
stacked
substrate
semiconductor chips
chip
silicon vias
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KR1020100038369A
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Korean (ko)
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KR101139699B1 (en
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김정호
송은석
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한국과학기술원
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Publication of KR20110118948A publication Critical patent/KR20110118948A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor chip in which passive devices are stacked includes a substrate, an active layer, passive elements, and a plurality of through silicon vias. The active layer includes integrated devices, power patterns for transmitting a power voltage, ground patterns for transmitting a ground voltage, and signal patterns for transmitting an electrical signal, and is formed on one surface of a substrate. Passive elements are stacked on the other side of the substrate. The plurality of through-silicon vias are formed through the substrate to electrically connect passive elements and integrated devices, and are surrounded by a silicon dioxide (SiO 2 ) film. Some of the plurality of through silicon vias deliver a supply voltage to passive elements, and others of the plurality of through silicon vias deliver a ground voltage to passive elements.

Description

Passive component-stacked semiconductor chip, 3-dimensional multi-chip and 3-dimensional multi-chip package having the same}

The present invention relates to a semiconductor chip, and more particularly, to a semiconductor chip, a three-dimensional multi-chip and a three-dimensional multi-chip package including the same stacked passive elements.

As semiconductor chips become smaller and lighter, three-dimensional multi-chip packages capable of high speed / wideband input / output (I / O) transmission have been studied. The stacking technology can improve the integration and signal transmission characteristics by implementing an electronic circuit including a semiconductor chip or a semiconductor chip package.

Meanwhile, in implementing the electronic circuit, it is necessary to appropriately arrange passive elements such as a capacitor together with a semiconductor chip. Conventionally, in disposing a capacitor, an off-chip method in which the capacitor is mounted on a set board or a package PCB on which the semiconductor chip is mounted, and a capacitor inside the substrate of the semiconductor chip. Formed on-chip or on-die methods were used.

In the case of the off-chip method, since a capacitor manufactured in advance is mounted on a board, it may have a relatively large capacitance value. However, as the interconnection length of the semiconductor chip and the capacitor increases, the off-chip method has a relatively large parasitic inductance. However, there is a disadvantage in that deterioration of power transmission characteristics may occur. The on-chip method has a relatively small parasitic inductance, but due to the limitation of the size of the semiconductor chip, the capacitor formed inside the substrate has a relatively small capacitance, and thus is transferred to an electronic circuit including the semiconductor chip. There is a problem that noise is increased.

Accordingly, there is a need for a capacitor arrangement and a semiconductor chip including the same, which can reduce parasitic inductance, increase capacitance, and be easily applied to a three-dimensional integrated circuit while minimizing the length of the connection line between the semiconductor chip and the capacitor.

One object of the present invention for solving the above problems is to provide a semiconductor chip that is electrically connected to the passive elements stacked using through silicon vias.

Another object of the present invention is to provide a three-dimensional multi-chip and a three-dimensional multi-chip package including the semiconductor chip.

In order to achieve the above object of the present invention, a semiconductor chip in which passive elements are stacked according to an embodiment of the present invention includes a substrate, an active layer, passive elements, and a plurality of through silicon vias. The active layer includes integrated devices, power patterns transferring a power supply voltage, ground patterns transferring a ground voltage, and signal patterns transferring an electrical signal, and are formed on one surface of the substrate. The passive elements are stacked on the other surface of the substrate. The plurality of through silicon vias are formed through the substrate to electrically connect the passive elements and the integrated devices, and are surrounded by a silicon dioxide (SiO 2 ) film. Some of the plurality of through silicon vias deliver the power supply voltage to the passive elements, and others of the plurality of through silicon vias deliver the ground voltage to the passive devices.

The plurality of through silicon vias may be formed by generating a plurality of through holes in the substrate through a laser process and filling the plurality of through holes with a conductive material.

In one embodiment, the passive elements may be capacitors of a surface mount type.

In one embodiment, the passive elements may be MOS transistor based on-die capacitors.

In order to achieve the above object of the present invention, a three-dimensional multi-chip according to another embodiment of the present invention includes a plurality of stacked semiconductor chips and passive elements. The passive elements are stacked between two adjacent semiconductor chips among the plurality of semiconductor chips, or stacked on a surface of a semiconductor chip stacked on the top or bottom of the plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a substrate, an active layer, and a plurality of through silicon vias. The active layer includes integrated devices, power patterns transferring a power supply voltage, ground patterns transferring a ground voltage, and signal patterns transferring an electrical signal, and are formed on one surface of the substrate. The plurality of through silicon vias are formed through the substrate and are surrounded by a silicon dioxide film so that the integrated devices are electrically connected to an adjacent semiconductor chip among the plurality of semiconductor chips or an adjacent passive element among the passive elements. Some of the plurality of through silicon vias deliver the power supply voltage to the passive elements, and others of the plurality of through silicon vias deliver the ground voltage to the passive devices.

In example embodiments, the passive elements may be surface mount capacitors, and the passive elements may be formed by exposing the other surface of the substrate on which the active layer is not formed among the semiconductor chips stacked on the top or bottom of the 3D multi-chip. The semiconductor chip may be stacked on the other surface of the substrate.

In one embodiment, the passive elements may be MOS transistor based on-die capacitors. In this case, when one of the on-die capacitors is stacked between two adjacent semiconductor chips of the plurality of semiconductor chips, one of the on-die capacitors is electrically connected to the two adjacent semiconductor chips. It may include a plurality of through silicon vias formed through one of the on-die capacitors. In addition, the plurality of semiconductor chips and the plurality of on-die capacitors may be stacked in any order.

In order to achieve the above object of the present invention, a three-dimensional multi-chip package according to another embodiment of the present invention includes a base substrate, a plurality of semiconductor chips and passive elements. The plurality of semiconductor chips are stacked on the base substrate. The passive elements are stacked between two adjacent semiconductor chips among the stacked semiconductor chips, or stacked on a surface of a semiconductor chip stacked on the top or bottom of the stacked plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a substrate, an active layer, and a plurality of through silicon vias. The active layer includes integrated devices, power patterns transferring a power supply voltage, ground patterns transferring a ground voltage, and signal patterns transferring an electrical signal, and are formed on one surface of the substrate. The plurality of through silicon vias are formed through the substrate and are surrounded by a silicon dioxide film so that the integrated devices are electrically connected to an adjacent semiconductor chip among the plurality of semiconductor chips or an adjacent passive element among the passive elements. Some of the plurality of through silicon vias deliver the power supply voltage to the passive elements, and others of the plurality of through silicon vias deliver the ground voltage to the passive devices.

The semiconductor chip, the three-dimensional multi-chip, and the three-dimensional multi-chip package including the same according to the embodiments of the present invention are stacked, the passive elements are stacked on the opposite side of the active surface of the substrate on which the active layer is formed By implementing interconnects that electrically connect the passive elements and the semiconductor chip using through silicon vias, the length of the interconnect lines can be minimized, parasitic inductance of the passive elements can be reduced, and capacitance can be increased. This reduces the inductance of the power delivery network and improves power noise.

In addition, when using an on-die capacitor based on a MOS transistor, passive devices may be stacked at an arbitrary position such as an upper portion, a lower portion, or an intermediate portion of the three-dimensional multi-chip, thereby providing a three-dimensional multi-chip suitable for a three-dimensional integrated circuit. Can be.

1 is a cross-sectional view illustrating a semiconductor chip in which passive devices are stacked according to an embodiment of the present invention.
2 is a cross-sectional view showing an example of a three-dimensional multi-chip according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a semiconductor chip in which passive devices are stacked according to another embodiment of the present invention.
4 is a cross-sectional view illustrating an example of a 3D multi-chip according to another exemplary embodiment of the present invention.
5 is a cross-sectional view illustrating another example of a 3D multi-chip according to another exemplary embodiment of the present invention.
6 is a cross-sectional view illustrating still another example of a three-dimensional multichip according to another exemplary embodiment of the present invention.
7 is a cross-sectional view showing an example of a three-dimensional multi-chip package according to an embodiment of the present invention.
8 is a cross-sectional view showing another example of a three-dimensional multi-chip package according to an embodiment of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

1 is a cross-sectional view illustrating a semiconductor chip 100 in which passive devices are stacked according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor chip 100 in which passive devices are stacked includes a semiconductor chip 110 and passive devices 130. The semiconductor chip 110 includes a substrate 112, a plurality of through silicon vias 114, and an active layer 122 formed on one surface of the substrate 112.

The substrate 112 may be, for example, a semiconductor substrate made of silicon. The substrate 112 may be used to implement the semiconductor chip 110 through a semiconductor manufacturing process such as a CMOS process. A plurality of through silicon vias 114 is formed through the substrate 112.

The active layer 122 is formed on one surface of the substrate 112. The active layer 122 includes integrated devices 124, power patterns 126, ground patterns 128, and signal patterns 127. The integrated devices 124 generally represent electronic devices such as transistors and diodes formed on a semiconductor substrate or an integrated circuit including the electronic devices. The power patterns 126 transfer power voltages provided from the outside of the semiconductor chip 110 to the integrated devices 124. The ground patterns 128 transfer ground voltages provided from the outside of the semiconductor chip 110 and provide them to the integrated devices 124. The signal patterns 127 transfer electrical signals that may be applied to the semiconductor chip 110 in addition to the power supply voltage and the ground voltage to provide the integrated devices 124. The integrated devices 124 may perform device native operation such as switching operation, rectification operation, etc. based on the power supply voltage, the ground voltage, and the electrical signals.

Although the active layer 122 is illustrated as one layer in FIG. 1, the active layer may include a plurality of layers according to an embodiment. For example, the active layer 122 may include a device layer in which the integrated devices 124 are formed, a power pattern layer in which the power patterns 126 are formed, a ground pattern layer in which the ground patterns 128 are formed, and the signal patterns 127. It may be implemented including the formed signal pattern layer. In this case, the order of the power pattern layer, the ground pattern layer, and the signal pattern layer may be arbitrarily changed, and an insulating film may be formed between two adjacent layers to prevent signal leakage.

The passive elements 130 are stacked on the other surface of the substrate 112. That is, the passive elements 130 are stacked on the opposite side of one surface of the substrate 112 on which the active layer 122 is formed. In general, the surface on which the integrated devices 124 are formed is often disposed to face upward. Therefore, in this case, one surface of the substrate 112 on which the integrated devices are formed may be disposed on the top surface, and the passive device 130 may be stacked. The other side of 112 can be called the back side. In the conventional semiconductor chip, additional elements are not stacked on the other side of the substrate, that is, the bottom surface, but in the present invention, the passive elements 130 are stacked on the other side of the substrate 112 to reduce the overall size of the semiconductor chip 100. The length of the interconnect between the semiconductor chip and the passive elements 130 may be minimized.

In one embodiment, as shown in FIG. 1, the passive elements 130 may be capacitors in the form of surface mount technology (SMT). In the case of using the surface mount capacitor as described above, the parasitic inductance of the passive element 130 may be reduced as compared with the conventional off-chip capacitor mounting structure.

The plurality of through silicon vias 114 electrically connect the passive elements 130 and the integrated elements 124. That is, the plurality of through silicon vias 114 are electrically connected to the passive elements 130 through the solder bumps 132 and the integrated devices 124 through the power pattern 126 or the ground pattern 128. And can be electrically connected. The passive elements 130 may receive the power supply voltage through the through silicon vias connected to the power pattern 126 and the ground voltage through the through silicon vias connected to the ground pattern 128. Although not shown, some of the through silicon vias 114 may be connected to the signal pattern 127, and the passive elements 130 may supply the electrical signal through the through silicon vias connected to the signal pattern 127. You can get it.

In one embodiment, the plurality of through silicon vias 114 may be formed using a laser. In detail, a plurality of through holes may be generated in the substrate 112 through a laser process, and a plurality of through silicon vias 114 may be formed by filling a plurality of through holes with a conductive material. When the through holes are formed using the chemical etching process, the depth of the through silicon vias is about several um. However, when the through silicon vias 114 are formed using the laser process as described above, the through silicon vias 114 The depth is about 50 ~ 500um, so it can reduce the parasitic inductance and improve the signal transmission characteristics compared to using the chemical etching process.

In one embodiment, a silicon dioxide (SiO 2 ) film 116, which is a kind of insulating film, may be formed around the through silicon vias 114 to prevent direct electrical contact with the substrate 112. In addition, tantalum layers may be formed between the through silicon vias 114 and the silicon dioxide layer 116 to increase the adhesion between the through silicon vias 114 and the silicon dioxide layer 116.

According to an embodiment, the through silicon vias 114 and the integrated devices 124 may be formed in a different order according to the manufacturing process of the semiconductor chip. For example, when the via first process is applied, the through silicon vias 114 are first formed on the substrate 112, and then the active layer 122 including the integrated devices 124 may be formed. . In another example, when the via last process is applied, the through silicon vias 114 are formed after the active layer 122 including the integrated devices 124 is first formed on one surface of the substrate 112. Can be.

In the conventional off-chip capacitor arrangement, since the parasitic inductance of the capacitor is relatively large, a few nH, that is, about 1 to 9 nH, simultaneous switching output noise (Simultaneous Switching) for the wideband input / output (I / O) in the GHz band The noise margin of the Output Noise (SSON) was not good. In the semiconductor chip 100 in which passive devices are stacked according to an embodiment of the present invention, the surface mount capacitors 130 are stacked and penetrated on the opposite side of the active surface of the substrate 112 on which the active layer 122 is formed. By connecting the capacitor 130 and the integrated devices 124 of the semiconductor chip using the silicon vias 114, the length of the connection line may be minimized and the parasitic inductance of the capacitor 130 may be reduced. For example, in the semiconductor chip 100 in which passive devices according to an embodiment of the present invention are stacked in comparison with a conventional arrangement structure, the parasitic inductance of the capacitor 130 is reduced by about 1/4. In other words, since it has a value of about 0.1 to 0.9 nH, the overall inductance of the power delivery network is also reduced, resulting in a robust power delivery network in terms of power integrity (PI). have. In addition, since the capacitance of the capacitor 130 can be increased by several uF, that is, about 1 to 9 uF, current can be smoothly supplied even when high-speed input / output is switched simultaneously, and power noise can be reduced.

2 is a cross-sectional view illustrating a three-dimensional multi chip 200 in which passive devices are stacked according to an embodiment of the present invention.

Referring to FIG. 2, the 3D multi-chip 200 in which passive devices are stacked includes a plurality of semiconductor chips 210 and 220 and passive devices 230.

The plurality of semiconductor chips 210 and 220 may be stacked on each other. The plurality of semiconductor chips 210 and 220 include substrates 212 and 222, active layers 214 and 224, and a plurality of through silicon vias 216 and 226, respectively. For example, the first semiconductor chip 210 is stacked on the second semiconductor chip 220. In addition, the first semiconductor chip 210 may include a first substrate 212, a first active layer 214 formed on one surface of the first substrate 212, and a plurality of first through silicon vias 216. Although not shown, an insulating layer may be formed between the first semiconductor chip 210 and the second semiconductor chip 220.

The first substrate 212 may be a silicon substrate. Although not shown in detail, as shown in FIG. 1, the first active layer 214 includes integrated devices, power patterns carrying a power supply voltage, ground patterns carrying a ground voltage, and signal patterns carrying an electrical signal. can do. The plurality of first through silicon vias 216 may be formed through the first substrate 212, and may include the integrated devices included in the first semiconductor chip 210 and the first semiconductor chip 210 adjacent to the first semiconductor chip 210. The two semiconductor chips 220 or the passive elements 230 may be electrically connected to each other. In order to prevent direct electrical contact with the substrate 212, a silicon dioxide film 218, which is a kind of insulating film, may be formed around the first through silicon vias 216.

The second semiconductor chip 220 may also have a structure substantially the same as that of the first semiconductor chip 210. The first through silicon vias 216 included in the first semiconductor chip 210 and the second through silicon vias 226 included in the second semiconductor chip 220 are formed on the same coordinates to each other when stacked. Can be aligned. In addition, each of the plurality of semiconductor chips 210 and 220 may have a structure substantially the same as that of the semiconductor chip 110 of FIG. 1, and overlapping description thereof will be omitted.

The passive elements 230 are stacked on the surface of the semiconductor chip stacked on the top or bottom of the plurality of semiconductor chips 210 and 220. For example, the passive devices 230 may be surface mount capacitors. In this case, the passive devices 230 may include the substrate on which the active layers 214 and 224 of the semiconductor chips 210 and 220 are not formed. The other surfaces of 212 and 222 may be stacked on the exposed semiconductor chip. That is, as shown in FIG. 2, the passive elements 230 may be stacked on the first semiconductor chip 210 where the other surface of the substrate 212 is exposed. In particular, the passive element 230 may be stacked on the first semiconductor chip 210. 212) may be stacked on the other side. In addition, solder bumps 240 may be formed between the semiconductor chips 210 and 220 and the passive devices 230 to electrically connect the semiconductor chips 210 and 220 and the passive devices 230.

In FIG. 2, the three-dimensional multi-chip 200 is implemented by using two semiconductor chips 210 and 220 and passive elements 230. Can be implemented.

3 is a cross-sectional view illustrating a semiconductor chip 300 in which passive devices are stacked according to another embodiment of the present invention.

Referring to FIG. 3, a semiconductor chip 300 in which passive devices are stacked includes a semiconductor chip 310 and passive devices 330. The semiconductor chip 310 includes a substrate 312, a plurality of through silicon vias 314, and an active layer 322 formed on one surface of the substrate 312.

The substrate 312 may be a silicon substrate. The active layer 322 may include integrated devices 324, power patterns 326 for transmitting a power voltage, ground patterns 328 for transmitting a ground voltage, and signal patterns 327 for transmitting an electrical signal. Can be. The through silicon vias 314 are formed through the substrate 312, and may electrically connect the integrated devices 324 and the passive devices 330 included in the semiconductor chip 310. In order to prevent direct electrical contact with the substrate 312, the silicon dioxide film 316, which is a kind of insulating film, may be formed around the through silicon vias 314.

The semiconductor chip 300 in which the passive elements of FIG. 3 are stacked may have a structure substantially the same as that of the semiconductor chip 100 in which the passive elements of FIG. 1 are stacked except that the passive elements 330 have a different structure. That is, the semiconductor chip 310 has a structure substantially the same as the semiconductor chip 110 of FIG. 1, and overlapping description thereof will be omitted.

The passive elements 330 are stacked on the other side of the substrate 312, that is, on the opposite side of one surface of the substrate 112 on which the active layer 322 is formed. In one embodiment, passive elements 330 may be an MOS transistor based on-die capacitor. For example, the passive devices 330 may include a capacitor substrate 332, a plurality of capacitor elements 336 and a wiring layer 334 formed in the capacitor substrate 332.

Although not shown in detail, the passive elements 330 including the plurality of capacitor elements 336 may be formed by forming metal-insulator-metal capacitor structures in the silicon substrate 332. The capacitor structure may be formed of a PN junction capacitance or a gate capacitance. That is, the plurality of capacitor elements 336 may be capacitors in the form of MOS transistors formed in the capacitor substrate 332 through a semiconductor production process such as a silicon process. The wiring layer 334 includes wirings for electrically connecting the capacitor elements 336 or between the capacitor elements 336 and an external element such as the semiconductor chip 310.

The plurality of through silicon vias 314 electrically connect the passive elements 330 and the integrated elements 324. That is, the plurality of through silicon vias 314 are electrically connected to the passive elements 330 through the solder bumps 340, and are integrated with the integrated devices 324 through the power pattern 326 or the ground pattern 328. And can be electrically connected.

In the conventional on-chip capacitor arrangement structure, the parasitic inductance of the capacitor has a small value, but it is difficult to increase the capacitance of the capacitor due to the limitation of the chip size. That is, in the conventional on-chip capacitor, when a large number of MOS transistor caps are disposed, the size of the chip is increased and the net-die is reduced, so that a capacitance of 100 nF or less is implemented. In the semiconductor chip 300 in which passive devices are stacked according to an embodiment of the present invention, the on-die capacitors 330 are stacked and penetrated on the opposite side of the active surface of the substrate 312 on which the active layer 322 is formed. By connecting the capacitor 330 and the integrated devices 324 of the semiconductor chip using the silicon vias 314, the length of the connection line may be minimized and the capacitance of the capacitor 330 may be increased. For example, in the semiconductor chip 300 in which passive devices according to an embodiment of the present invention are stacked in comparison with a conventional arrangement structure, the capacitance of the capacitor 330 may be increased by several uF, that is, about 1 to 9 uF. This allows for smooth supply of current even when high-speed inputs and outputs are switched simultaneously, and can reduce power noise.

4 is a cross-sectional view showing an example of a three-dimensional multi-chip 400 according to another embodiment of the present invention, Figure 5 is a cross-sectional view showing another example of a three-dimensional multi-chip 500 according to another embodiment of the present invention 6 is a cross-sectional view illustrating still another example of the 3D multi-chip 600 according to another embodiment of the present invention. 4 through 6 illustrate three-dimensional multi-chips 400, 500, and 600 in which passive elements and a plurality of semiconductor chips are implemented in the form of MOS transistor-based on-die capacitors.

Referring to FIG. 4, the 3D multi-chip 400 includes a plurality of semiconductor chips 410 and 420 and passive elements 430.

The plurality of semiconductor chips 410 and 420 have a stacked structure. The plurality of semiconductor chips 410 and 420 include a substrate 412 and 422, an active layer 414 and 424, and a plurality of through silicon vias 416 and 426, respectively. The plurality of through-silicon vias 416 and 426 are formed through the substrates 412 and 422, and the integrated devices included in the semiconductor chips 410 and 420 and the adjacent semiconductor chips or the passive devices 430 may be formed. Can be electrically connected. Each of the plurality of semiconductor chips 410 and 420 may have a structure substantially the same as that of the semiconductor chip 310 of FIG. 3.

The passive elements 430 may have a structure substantially the same as that of the passive elements 330 of FIG. 3, and are stacked on the surface of the semiconductor chip stacked on the top or bottom of the plurality of semiconductor chips 410 and 420. The passive elements 430 may be stacked on a semiconductor chip in which the other surface of the substrates 412 and 422 on which the active layers 414 and 424 are not formed among the semiconductor chips 410 and 420 are exposed. That is, as shown in FIG. 4, the passive elements 430 may be stacked on the other surface of the substrate 412 of the first semiconductor chip 410. In addition, solder bumps 440 may be formed between the semiconductor chips 410 and 420 and the passive elements 430 to electrically connect the semiconductor chips 410 and 420 and the passive elements 430.

Referring to FIG. 5, the 3D multi-chip 500 includes a plurality of semiconductor chips 510, 520, and 530 and passive elements 540.

The plurality of semiconductor chips 510, 520, and 530 have a stacked structure. The plurality of semiconductor chips 510, 520, and 530 include a substrate 512, 522, and 532, an active layer 514, 524, and 534, and a plurality of through silicon vias 516, 526, and 536, respectively. The plurality of through silicon vias 516, 526, and 536 are formed through the substrates 512, 522, and 532, and have integrated semiconductors included in the semiconductor chips 510, 520, and 530, adjacent semiconductor chips, or passive devices. The devices 540 may be electrically connected to each other. Each of the plurality of semiconductor chips 510, 520, and 530 may have a structure substantially the same as that of the semiconductor chip 310 of FIG. 3.

The passive elements 540 may have a structure substantially the same as that of the passive elements 330 of FIG. 3, and are stacked between two adjacent semiconductor chips among the plurality of semiconductor chips 510, 520, and 530. That is, as shown in FIG. 5, the passive elements 540 may be stacked between the first semiconductor chip 510 and the second semiconductor chip 520. In addition, the semiconductor chips 510, 520, and 530 and the passive elements 540 may be electrically connected through the solder bumps 550.

As shown in FIG. 5, when the passive elements 540 are stacked between two adjacent semiconductor chips, the passive elements 540 are turned on to be electrically connected to the adjacent first and second semiconductor chips 510 and 520. And a plurality of through silicon vias 548 formed through the capacitor substrate 542 of the die capacitor 540. The plurality of through silicon vias 548 and the plurality of through silicon vias 516, 526, and 536 formed in the semiconductor chips 510, 520, and 530 may be formed on the same coordinate to be aligned with each other when stacked. Can be. In addition, a silicon dioxide film, which is a kind of insulating film, may be formed around the plurality of through silicon vias 548 to prevent direct electrical contact with the capacitor substrate 542.

Referring to FIG. 6, the 3D multi-chip 600 in which passive devices are stacked includes a plurality of semiconductor chips 610, 620, and 630 and passive devices 640 and 650.

The plurality of semiconductor chips 610, 620, and 630 have a stacked structure. The plurality of semiconductor chips 610, 620, and 630 include substrates 612, 622, and 632, active layers 614, 624, and 634, and a plurality of through silicon vias 616, 626, and 636, respectively. The plurality of through silicon vias 616, 626, and 636 are formed through the substrates 612, 622, and 632 and include integrated devices included in the semiconductor chips 610, 620, and 630, and adjacent semiconductor chips or passives. The devices 640 and 650 may be electrically connected to each other. Each of the plurality of semiconductor chips 610, 620, and 630 may have a structure substantially the same as that of the semiconductor chip 310 of FIG. 3.

Each of the passive elements 640 and 650 may have a structure substantially the same as that of the passive element 330 of FIG. 3, and is stacked between two adjacent semiconductor chips among the plurality of semiconductor chips 610, 620, and 630. . That is, as illustrated in FIG. 6, the first passive elements 640 are stacked between the first semiconductor chip 610 and the second semiconductor chip 620, and the second passive elements 650 may be the second semiconductor chip. It may be stacked between 620 and the third semiconductor chip 630. In addition, the semiconductor chips 610, 620, and 630 and the passive elements 640 and 650 may be electrically connected through the solder bumps 660.

When passive devices 640 and 650 are stacked between two adjacent semiconductor chips, as shown in FIG. 6, passive devices 640 and 650 are through silicon vias for electrically connecting two adjacent semiconductor chips. (648, 658). That is, the first passive elements 640 pass through the plurality of through silicon vias 648 formed through the first capacitor substrate 642 to be electrically connected to the adjacent first and second semiconductor chips 610 and 620. The second passive elements 650 may include a plurality of through silicon vias formed through the second capacitor substrate 652 to be electrically connected to adjacent second and third semiconductor chips 620 and 630. 658).

In FIG. 4, a three-dimensional multichip 400 is implemented using two semiconductor chips 410 and 420 and one on-die capacitor 430. In FIG. 5, three semiconductor chips 510, 520, and 530 are illustrated. And a three-dimensional multi-chip 500 using one on-die capacitor 540. In FIG. 6, three semiconductor chips 610, 620, and 630 and two on-die capacitors 640 and 650. Although the 3D multi-chip 600 is implemented using, the 3D multi-chip may be implemented using any number of semiconductor chips and on-die capacitors according to the exemplary embodiment. In addition, the stacking order of the semiconductor chips and the on-die capacitors may be arbitrarily selected according to the design.

As shown in FIGS. 4 to 6, through-through silicon vias are used to implement three-dimensional multi-chips 400, 500, and 600 with electrically connected semiconductor chips and passive devices, thereby minimizing the length of the connection line and reducing inductance. Capacitors with increased capacitance can be implemented. In addition, by using passive devices implemented with on-die capacitors based on MOS transistors, passive devices can be stacked on top or bottom of a 3D multi-chip, and passive devices can be stacked between adjacently stacked semiconductor chips. have. Accordingly, it is possible to provide a three-dimensional multi-chip more suitable for a three-dimensional integrated circuit structure in which a plurality of semiconductor chips are stacked.

7 is a cross-sectional view illustrating an example of a 3D multi-chip package 1000 according to an embodiment of the present invention.

Referring to FIG. 7, the 3D multi-chip package 1000 includes a base substrate 1100, a plurality of semiconductor chips 210 and 220, and passive devices 230.

The plurality of semiconductor chips 210 and 220 are stacked on the base substrate 1100. The package through hole via 1110 may pass through the base substrate 1100 to transmit an electrical signal, a power supply voltage, and a ground voltage. The solder ball 1120 electrically connects the base substrate 1100 and another external device.

The plurality of semiconductor chips 210 and 220 may be stacked on each other, and the plurality of semiconductor chips 210 and 220 may include a substrate 212 and 222, an active layer 214 and 224, and a plurality of through silicon vias 216. 226), respectively. The passive elements 230 may be, for example, a surface mount capacitor, and may be stacked on the other surface of the substrate 212 in which the active layers 214 and 224 of the first semiconductor chip 210 are not formed. In addition, the semiconductor chips 210 and 220, the passive elements 230, and the base substrate 1100 may be electrically connected through the solder bumps 240. The structures of the plurality of semiconductor chips 210 and 220 and the passive elements 230 may have a structure substantially the same as that of the 3D multi-chip 200 shown in FIG. 2, and overlapping descriptions thereof will be omitted.

8 is a cross-sectional view illustrating another example of the 3D multi-chip package 2000 according to an embodiment of the present invention.

Referring to FIG. 8, the 3D multi-chip package 2000 includes a base substrate 2100, a plurality of semiconductor chips 510, 520, and 530, and passive elements 540.

The plurality of semiconductor chips 510, 520, and 530 are stacked on the base substrate 2100. The package through hole via 2110 may penetrate the base substrate 2100 to transmit an electrical signal, a power supply voltage, and a ground voltage. The solder ball 2120 electrically connects the base substrate 2100 and another external device.

The plurality of semiconductor chips 510, 520, and 530 are stacked on each other, and the substrates 512, 522, and 532, the active layers 514, 524, and 534, and the plurality of through silicon vias 516, 526, and 536 are formed. Each includes. The passive elements 540 may be, for example, MOS transistor based on-die capacitors, and may be stacked between the first and second semiconductor chips 510 and 520. The passive elements 540 pass through the plurality of through silicon vias 548 formed through the capacitor substrate 542 of the on-die capacitor 540 to be electrically connected to the adjacent first and second semiconductor chips 510 and 520. ) May be included. In addition, the semiconductor chips 510, 520, and 530, the passive elements 540, and the base substrate 2100 may be electrically connected through the solder bumps 550. The structure of the plurality of semiconductor chips 510, 520, 530 and the passive elements 540 may have a structure substantially the same as that of the 3D multi-chip 500 illustrated in FIG. 5, and overlapping descriptions thereof will be omitted.

Hereinafter, a method of manufacturing a semiconductor chip according to an embodiment of the present invention will be described with reference to FIGS. 1 and 3.

First, a plurality of through silicon vias penetrating the substrate are formed. In example embodiments, a plurality of through holes may be formed in the substrate through a laser process, and the plurality of through silicon vias may be formed by filling a conductive material in the plurality of through holes.

Next, an active layer is formed on one surface of the substrate. The active layer includes integrated devices such as transistors and diodes, power patterns for transmitting a power supply voltage, ground patterns for transmitting a ground voltage, and signal patterns for transmitting an electrical signal. The integrated devices may be electrically connected to the plurality of through silicon vias through the power patterns or the ground patterns.

Next, passive elements are stacked on the other surface of the substrate. The passive elements may be electrically connected to the plurality of through silicon vias through solder bumps. That is, the integrated devices and the passive devices of the semiconductor chip may be electrically connected to each other through the plurality of through silicon vias.

In one embodiment, as shown in Figure 1, the passive element 130 may be a capacitor in the form of a surface mount. In another embodiment, as shown in FIG. 3, passive elements 330 may be an on-die capacitor based on a MOS transistor. Therefore, semiconductor chips manufactured through the method of manufacturing a semiconductor chip according to an embodiment of the present invention may be used to implement a 3D integrated circuit.

According to the present invention, by stacking passive elements on the opposite side of the active surface of the substrate on which the active layer is formed, and implementing a connection line for electrically connecting the passive element and the semiconductor chip using through silicon vias, the length of the connection line is minimized and the By providing parasitic inductance of passive elements, increasing capacitance, and providing semiconductor chips and three-dimensional multi-chips suitable for three-dimensional integrated circuits, they can be applied to package systems and electronic systems using the semiconductor chips as described above. Transmission is possible, reducing the inductance of the system's power delivery network and improving power noise.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

Claims (10)

Board;
An active layer formed on one surface of the substrate, including integrated devices, power patterns transferring a power supply voltage, ground patterns transferring a ground voltage, and signal patterns transferring an electrical signal;
Passive elements stacked on the other surface of the substrate; And
A plurality of through silicon vias formed through the substrate to be electrically connected to the passive elements and the integrated devices, and surrounded by a silicon dioxide (SiO 2 ) film,
Some of the plurality of through silicon vias deliver the power supply voltage to the passive devices, and the remaining of the plurality of through silicon vias transfers the ground voltage to the passive devices. . The semiconductor of claim 1, wherein the plurality of through silicon vias are formed by forming a plurality of through holes in the substrate through a laser process and filling a plurality of through holes with a conductive material. chip. The semiconductor chip of claim 1, wherein the passive elements are surface mount capacitors. The semiconductor chip of claim 1, wherein the passive devices are on-die capacitors based on MOS transistors. A plurality of stacked semiconductor chips; And
Passive elements stacked between two adjacent semiconductor chips of the plurality of semiconductor chips, or stacked on the surface of the semiconductor chip stacked on the top or bottom of the plurality of semiconductor chips,
Each of the plurality of semiconductor chips may include a substrate;
An active layer formed on one surface of the substrate, including integrated devices, power patterns transferring a power supply voltage, ground patterns transferring a ground voltage, and signal patterns transferring an electrical signal; And
The plurality of through silicon vias formed through the substrate and electrically connected to an adjacent semiconductor chip among the plurality of semiconductor chips or an adjacent passive element among the passive elements and surrounded by a silicon dioxide (SiO 2 ) film ( through silicon via),
Some of the plurality of through silicon vias deliver the power supply voltage to the passive elements, and the other of the plurality of through silicon vias delivers the ground voltage to the passive devices. The method of claim 5, wherein the passive elements are surface mount capacitors,
The passive elements may be stacked on the other surface of the substrate of the semiconductor chip, the other surface of the substrate on which the active layer is not formed, among the semiconductor chips stacked on the top or bottom of the three-dimensional multi-chip. . The 3D multi-chip of claim 5, wherein the passive devices are on-die capacitors based on MOS transistors. The semiconductor device of claim 7, wherein when one of the on-die capacitors is stacked between two adjacent semiconductor chips of the plurality of semiconductor chips, one of the on-die capacitors is electrically connected to the two adjacent semiconductor chips. And a plurality of through silicon vias formed through one of the on-die capacitors to be connected. The 3D multi-chip of claim 7, wherein the plurality of semiconductor chips and the plurality of on-die capacitors are stacked in any order. A base substrate;
A plurality of semiconductor chips stacked on the base substrate; And
Passive elements stacked between two adjacent semiconductor chips of the plurality of stacked semiconductor chips, or stacked on the surface of the semiconductor chip stacked on the top or bottom of the stacked plurality of semiconductor chips,
Each of the plurality of semiconductor chips may include a substrate;
An active layer formed on one surface of the substrate, including integrated devices, power patterns transferring a power supply voltage, ground patterns transferring a ground voltage, and signal patterns transferring an electrical signal; And
A plurality of through silicon vias formed through the substrate to be electrically connected to an adjacent semiconductor chip among the plurality of semiconductor chips or an adjacent passive element among the passive elements and surrounded by a silicon dioxide (SiO 2 ) film; silicon vias,
Some of the plurality of through silicon vias deliver the power supply voltage to the passive devices, and the other of the plurality of through silicon vias delivers the ground voltage to the passive devices.
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