KR20110059807A - Backside illuminated image sensor - Google Patents

Abstract

The back illuminated image sensor includes a substrate, a back passivation layer disposed on the back side of the substrate, and a transparent conductive layer disposed on the back passivation layer.

Description

Backlit Image Sensors {BACKSIDE ILLUMINATED IMAGE SENSOR}

The present invention relates to an illuminated back of an image sensor, in particular a back illuminated image sensor.

In general, in a Complementary Metal Oxide Semiconductor Active Pixel Sensor (CMOS APS), which may be referred to as CMOS image sensor in the following, the light receiving element, the digital control block, and the analog-to-digital converter The same peripheral circuitry is aligned in a limited area of the chip. Thus, the area ratio of the pixel array per chip area is limited to about 40%. In addition, since the pixel size is greatly reduced for the realization of high quality images, the amount of light that one light receiving element can collect is reduced and the noise is increased, thereby increasing various problems such as image loss resulting from the noise. .

Embodiments of the present invention relate to a back-illuminated image sensor, where light illuminates the back side of the (wafer) substrate.

According to one aspect of the invention, there is provided a back illuminated image sensor comprising a substrate, a back passivation layer disposed on the back side of the substrate, and a transmissive conductive layer disposed on the back passivation layer.

According to another aspect of the present invention, there is provided a light receiving element disposed on a first substrate, an interlayer insulating layer disposed on the first substrate having the light receiving element, the interlayer insulating layer spaced apart from the light receiving element and the first layer. 1 an alignment key passing through the substrate, a plurality of interconnect layers disposed on the interlayer insulating layer of the multilayer structure, wherein a rear surface of the lowest interconnect layer is connected to the alignment key; A front passivation layer to cover, a back passivation layer disposed on the back side of the first substrate, a transparent conductive layer disposed on the back passivation layer and connected to the alignment key, and on the transmissive conductive layer to face the light receiving element. A back illuminated image sensor is provided, comprising a color filter and a microlens disposed thereon.

1 is a cross-sectional view illustrating a back illuminated image sensor in accordance with one embodiment of the present invention.
2A-2J are cross-sectional views illustrating a method for manufacturing a back lit image sensor in accordance with one embodiment of the present invention.
3 shows an energy band when a negative voltage is applied to the transparent conductive layer.
4 shows the energy band when the back passivation layer is a silicon nitride layer.

Embodiments of the present invention relate to a back lit image sensor according to an embodiment of the present invention.

Referring to the drawings, the illuminated thickness of layers and regions is exaggerated to facilitate explanation. When referred to as being on a second layer "on" or on a substrate ", this may mean that the first layer is formed directly on the second layer or substrate, or the first It may also mean that there may be a third layer between the layer and the substrate. In addition, the same or similar reference numerals throughout the various embodiments of the present invention represent the same or similar elements in different drawings.

1 is a cross-sectional view illustrating a back illuminated image sensor in accordance with one embodiment of the present invention.

For convenience, only the gate electrode and the photodiode of the driving transistor of the unit pixel of the CMOS image sensor are illustrated in FIG. 1.

Referring to FIG. 1, a back-illuminated image sensor according to an embodiment of the present invention may include a second passivation layer 125 disposed on a back surface of a second semiconductor pattern 100-3A, a semiconductor pattern 100-3A, And a transparent conductive layer 326 disposed on the back passivation layer 125.

The second semiconductor pattern 100-3A includes a p-type conductive material (hereinafter, referred to as a first conductive material). The second semiconductor pattern 100-3A is doped with p-type impurity ions such as boron (B), which is a member of group 3 in the periodic table. The second semiconductor pattern 100-3A includes a silicon (Si) layer, a germanium (Ge) layer, a silicon germanium (SiGe) layer, a gallium phosphide (GaP) layer, a gallium arsenide (GaAs) layer, and a silicon carbide (SiC) layer. , A silicon germanium carbon (SiGeC) layer, an indium arsenide (InAs) layer, and a layered structure thereof. Preferably, the second semiconductor pattern 100-3A may include a Si layer. The second semiconductor pattern 100-3A may be a substrate or a bulk substrate formed on the buried insulating layer of the silicon on insulator (SOI) layer. In addition, the second semiconductor pattern 100-3A may be an epitaxial layer disposed on the SOI substrate. In this embodiment, the substrate is an SOI substrate formed over the buried insulating layer of the SOI substrate.

The back passivation layer 125 functions as an antireflective layer. Back passivation layer 125 is a dielectric coating layer formed over the optical surface. The antireflective layer reduces the light reflecting power of the optical surface in a predetermined range. In general, the operating principle of the reduction of light reflection power is that wavelengths reflecting from other interfaces are eliminated by destructive interference. In the simplest case, the antireflective layer designed for vertical incidence comprises a material having a quarter-wave layer. The refractive index of the material is close to the geographic mean of two neighboring media. In this case, two reflections of the same angle are created on the interface of the two media and then removed by destructive interference between them.

The back passivation layer 125 has a multilayer structure in which materials with different refractive indices are stacked. The number of layers for the multilayer structure is not limited, and the layers may be selected in a range that improves the reflective properties of the rear passivation layer 125. The back passivation layer 125 includes a layer having a lower refractive index than the second semiconductor pattern 100-3A. In addition, when the back passivation layer 125 has a laminated structure, as the layer is closer to the back of the second semiconductor pattern 100-3A, the layers start to have a low refractive index.

For example, the back passivation layer 125 includes a first insulating layer and a second insulating layer. The first insulating layer is formed between the second insulating layer and the second semiconductor pattern 100-3A. The second insulating layer includes a nitride layer. Preferably, the second insulating layer comprises a silicon nitride compound. More preferably, the second insulating layer comprises a silicon nitride layer or a silicon oxynitride layer. Here, the nitride layer is formed to have a thickness of about 50 nm to about 500 nm. The first insulating layer includes a material having a refractive index lower than that of the second insulating layer and lower than that of the second semiconductor pattern 100-3A. Preferably, the first insulating layer comprises an oxide layer. More preferably, the first insulating layer comprises a silicon oxide layer. The silicon oxide layer may be selected from the group consisting of a natural silicon oxide layer, a grown silicon oxide layer, and a deposited silicon oxide layer. Here, the silicon oxide layer is formed to have a thickness of about 2 nm to about 50 nm.

The transparent conductive layer 126 includes transparent conductive oxides (TCOs). The transparent conductive layer 126 may include one selected from the group consisting of an indium tin (ITO) layer, a zinc oxide (including ZnO, ZO) layer, a tin oxide (including SnO, TO) layer, and a zinc tin oxide (ZTO) layer. Can be. The ITO layer may be doped with one selected from the group consisting of cobalt (CO), titanium (Ti), tungsten (W), molybdenum (Mo) and chromium (Cr). The ZO layer is doped with one selected from the group consisting of magnesium (Mg), zirconium (Zr) and lithium (Li). The TCO layer is formed to have a thickness of about 10 nm to about 500 nm. The transparent conductive layer 126 may include a polysilicon layer or a metal layer. The polysilicon layer and the metal layer are formed to have a thin thickness for transmitting incident light to the second semiconductor pattern 100-3A. For example, the polysilicon layer is formed to have a thickness of approximately 40 nm or less. Preferably, the polysilicon layer is formed to have a thickness of about 1 nm to about 40 nm. The metal layer comprises a noble metal. For example, precious metals include gold (Au) or platinum (Pt). The precious metal is formed to have a thickness of about 1 nm or less. The precious metal may be formed to have a thickness of about 0.1 nm to about 1 nm.

A back-illuminated image sensor according to a first embodiment of the present invention is provided on a light receiving element 106 and a second substrate pattern 100-3A formed on a first substrate, such as a second semiconductor pattern 100-3A. First interlayer dielectric pattern 108A formed, alignment key 112 spaced from light receiving element 106 and passing through first interlayer dielectric pattern 108A and first semiconductor pattern 100-1A, multilayer structure Of first to fourth interconnect layers 113, 116, 119 and 122 formed on the first interlayer insulating pattern 108A of the first to fourth interconnect layers 113, 116, 119 and 122. The backside of the first interconnection layer 113 is connected to the alignment key 112, a passivation layer 124 covering the interconnection layers 113, 116, 119 and 122, disposed on the backside of the first substrate Number of lights disposed on the back passivation layer 125, the transparent conductive layer 126 formed on the rear surface of the first substrate to be connected to the alignment key 112, and the transparent conductive layer 126. And a color filter 128 and a microlens 130 overlapping the dragon element 106.

The first substrate 100 (see FIG. 2A) may be a bulk substrate, an epitaxial substrate, or a silicon-on-insulator (SOI) substrate. In consideration of device features, an SOI substrate on which a first semiconductor layer, a buried insulating layer, and a second semiconductor layer are stacked is used as the first substrate 100 and a relatively inexpensive bulk substrate is used as the second substrate 200 ( 2e). In the present invention, the first and second substrates 100 and 200 are SOI substrates.

Alignment key 112 functions as an alignment mark during the process of forming color filter 128 and microlens 130. Multiple sort keys 112 are provided. The backside of the plurality of alignment keys 112 is connected to the transparent conductive layer 126. The top surface of the alignment key 112 is connected to the first interconnect layer 113 among the first to fourth interconnect layers 113, 116, 119 and 122, and the alignment key 112 is applied with a negative voltage. A negative voltage applied from the unit 300 (see FIG. 3) is transmitted to the transparent conductive layer 126. Alignment key 112 may be formed of a conductive material, for example, metal or alloy. In addition, the alignment key 112 may be formed in the shape of a circle, oval, or polygon (such as triangle, rectangle, octagon, etc.). There is no limit on the number and size (width) of the sort keys 112.

The back-illuminated image sensor according to the first embodiment of the present invention is provided to the alignment key 112 or the transparent conductive layer 126 instead of the negative voltage applying unit 300 to invert the back of the first substrate 100. It may include a positive voltage applying unit (not shown) for applying a positive voltage (+).

Further, the back illuminated image sensor according to the first embodiment of the present invention further includes a barrier layer (not shown) surrounding the outer wall of the alignment key 112. The barrier layer (not shown) may include a metal layer or an insulator layer. In particular, the metal layer may comprise a Ti / TiN layer and the insulator layer may comprise a nitride layer, for example a silicon nitride layer, an oxide layer, for example a silicon oxide layer, or a laminate structure thereof, for example an oxide / nitride. It may comprise a layer.

In addition, the back-illuminated image sensor according to an embodiment of the present invention further includes a plurality of transistors to transmit and amplify the optical signals of the light receiving element 106. For example, the driving transistor may include both side surfaces of the gate electrode 104 and the gate electrode 104 formed between the first substrate pattern 100A, the first substrate pattern 100A, and the first interlayer insulating pattern 108A. Source and drain regions 107 formed in the first substrate 100 exposed on the substrate.

The back lit image sensor according to an embodiment of the present invention further includes a negative voltage applying unit 300. The negative voltage applying unit 300 directly provides a negative voltage to the transparent conductive layer 126. The negative voltage applying unit 300 also provides a negative voltage to the transparent conductive layer 126 through an alignment key 112 connected to the transparent conductive layer 126. The negative voltage applying unit 300 may be formed on the second substrate 200.

4 shows the energy band when the back passivation layer is a silicon nitride layer.

Referring to FIG. 4, the silicon nitride layer includes a negative charge. The silicon nitride layer containing positive charges reverses the backside of the exposed semiconductor layer. The reversed backside of the substrate reduces surface recombination and surface generation. Reduced surface recombination increases quantum efficiency, and reduced surface production reduces dark current leakage.

When the silicon nitride layer is connected to the substrate (or silicon oxide layer and substrate) in equilibrium, charge (which is electrons) accumulates at the interface between the silicon nitride layer and the substrate due to the positive charge of the silicon nitride layer. Thus, the valence electron band Ev is further separated from the Fermi level Ef at the interface between the silicon nitride layer and the substrate. In other words, an inversion state is achieved. The inverted state results in a conduction band Ec approaching the Fermi level Ef. When light is illuminated in an inverted state, charge (electrons), i.e. photocurrent, is generated. This results in much more electrons in the inversion layer that can diffuse towards the light receiving element, and charge (electrons) easily flows into the light receiving element. That is, the photocurrent generated at the interface easily flows to the light receiving element. Alternatively, a positive voltage can be applied to the transparent conductive layer 126 to invert the backside.

3 shows an energy band when a negative voltage is applied to the transparent conductive layer.

Referring to FIG. 3, in equilibrium, the valence electron band Ev approaches the Fermi level Ef. When a negative voltage is applied to the transparent conductive layer, the potential difference between the Fermi level Ef and the conduction band becomes high. It becomes difficult to generate charges (electrons), i.e. negative currents, and therefore negative currents cannot flow to the light receiving element. When light is illuminated in this state, a charge (electrons), i.e. a photocurrent, is generated and can diffuse towards the light receiving element. That is, the photocurrent generated at the interface easily flows to the light receiving element. 2A-2J are cross-sectional views of a method for manufacturing a back lit image sensor according to a second embodiment of the present invention. In this embodiment, the substrate is an SOI substrate.

The back illuminated image sensor according to the second embodiment of the present invention has a structure in which the device wafer and the handle wafer 200 are attached together. A device wafer is a wafer in which light receiving elements such as photodiodes are formed, and peripheral circuits such as digital blocks and analog-to-digital toilets are formed. In the following description, the element wafer and the handle wafer will be referred to as a first substrate and a second substrate, respectively.

Referring to FIG. 2A, the first substrate 100 is an SOI substrate. The SOI substrate includes a first semiconductor layer 100-1, a buried insulating layer 100-2, and a second semiconductor layer 100-3. The second semiconductor layer 100-3 may be doped with a first conductivity type and a second conductivity type. For example, the second semiconductor layer 100-3 is doped with the first conductivity type. In addition, the buried insulating layer 100-2 may be formed to have a thickness of about 500 μm to about 10,000 μm, and the second semiconductor layer 100-3 may be formed to have a thickness of about 1 μm to about 10 μm. Can be.

The insulating layer 101 is locally formed on the first substrate 100. The insulating layer 101 may be formed through a shallow trench isolation (STI) process or a LOCOS (LOCaI Oxidation of Silicon) process, but the insulating layer 101 is illustrated in FIG. 2A. Likewise, it is preferably formed using an STI process which is desirable for the realization of high directness. When the STI process is performed, the insulating layer 101 has a high filling ratio for high aspect ratio, or a high density plasma (HDP) having a laminated structure of an HDP layer or a spin on insulation (SOD) layer. It may comprise a layer.

A gate insulating layer 102 and a gate conductive layer 103 are formed over the first substrate 100 and then etched to form the gate electrode 104 of the drive transistor. At the same time, although not shown, gate electrodes of a transfer transistor, a reset transistor, and a selection transistor constituting a unit pixel of a CMOS image sensor may be formed.

The spacer 105 may be formed on both sidewalls of the gate electrode 104. The spacers 105 may include an oxide layer, a nitride layer, or a stacked structure thereof.

Before the spacers 105 are formed, the gate electrode 104 is formed. A lightly doped drain (LDD) region (not shown) doped with an n-type (hereinafter referred to as a second conductive type) is exposed on both sides of the gate electrode 104 to expose the first substrate 100. Is formed.

A photodiode that functions as the light receiving element 106 is formed in the first substrate 100 through an ion implantation process. In this case, the light receiving element 106 is doped to the second conductivity type. The photodiode has the relatively thin doping profile of FIG. 2A. However, this is for convenience and the doping profile (depth, width) can be changed as appropriate.

Source and drain regions 107 doped with a second conductivity type are formed on the first substrate 100 exposed on both sides of the spacers 105. Source and drain regions 107 have a higher doping concentration than LDD region and light receiving element 105.

To prevent surface noise of the light receiving element 106, a doped region (not shown) doped with the first conductivity type may be further formed to cover the top surface of the light receiving element 106.

Although it has been described above that the gate electrode 104, the spacers 105, the light receiving element 106 and the source and drain regions 107 are formed sequentially, their order of formation is not limited to the above embodiment, It can be changed according to manufacturing processes.

The first interlayer insulating layer 108 is formed to cover the first substrate 100 including the gate electrode 104, the spacers 105, the photodiode 106, and the source and drain regions 107. The first interlayer insulating layer 108 may include an oxide layer, for example, a silicon oxide layer (SiO ₂ ). In particular, the first interlayer insulating layer 108 may include a BoroPhosphoSilicate Glass (BPSG) layer, a Phosphosilicate Glass (PSG) layer, a BoroSilicate Glass (BSG) layer, and a non-doped layer. And a layer selected from the group consisting of an un-doped Silicate Glass (USG) layer, a Tetra Ethyle Ortho Silicate (TEOS) layer, an HDP layer, and a laminated layer thereof. . In addition, the first interlayer dielectric layer 108 may include a layer, such as a Spin On Dielectric (SOD) layer deposited by a spin coating process.

Referring to FIG. 2B, an etch process is performed to locally etch the first interlayer dielectric layer 108 to form a contact hole 109 exposing the source and drain regions 107. The etch process may be performed using a dry etch process or a wet etch process. It is desirable to perform a dry etch process so that a vertically etched surface can be obtained.

The first interlayer insulating layer 108 and the first substrate 100 are locally etched. Hereinafter, the etched first interlayer insulating layer 108 and the first substrate 100 are referred to as a first interlayer insulating pattern 108A and a first substrate pattern 100A, respectively. Accordingly, the via hole 110 extending from the first interlayer insulating pattern 108A to the first semiconductor pattern 100-1A is formed. In this case, the plurality of via holes 110 may be formed in a matrix configuration.

In particular, the via hole 110 has a vertical angle of about 88 degrees to about 90 degrees and a depth of about 20,000 mm, preferably about 4,000 mm to about 20,000 mm from the top surface of the first interlayer insulating pattern 108A. More preferably, the via holes 110 are formed to have a depth of about 1,000 GPa to about 10,000 GPa from the top surface of the second semiconductor pattern 100-3A. In addition, the via hole 110 has a critical dimension (CD) of approximately 0.1 μm to approximately 2.0 μm. Via hole 110 has a bottom width of less than approximately 1.6 μm, preferably approximately 1.0 μm to approximately 1.6 μm. When multiple via holes 110 are formed, the deviation of their angles, depths and widths is preferably less than 4%. In addition, there is no limitation on the number and shape of the via holes 110. In particular, the via hole 110 may be formed in various shapes, for example, in the form of a circle or a polygon (triangle, rectangle, pentagon, octagon, etc.).

On the other hand, there is no restriction on the order in which the contact holes 109 and the via holes 110 are formed. The contact hole 109 may be formed after the via hole 110 is formed. In addition, the contact holes 109 and the via holes 110 may be formed in-situ in the same plasma etching apparatus.

For example, via holes 110 are formed using a dry etching process in two steps.

The first step is to etch the first interlayer insulating layer 108. The etching process is performed under conditions where the etch selectivity of the first interlayer insulating layer 108 to the photoresist pattern (not shown) is in the range of 5: 1 to 2: 1, preferably 2.4: 1. The etch rate is also in the range of about 7,000 Λ / min to about 8,000 dl / min, preferably 7,200 dl / min. As etching conditions, the pressure is in the range of about 100 mTorr to about 200 mTorr, and the source power is in the range of about 100 W to about 2,000 W. Carbon fluorine compounds such as fluoroform (CHF ₃ ) or tetrafluoromethane (CF ₄ ) are used as the source gas, and argon (Ar) is additionally added to the source gas to increase the etching rate and anisotropy. do. The flow rate of CHF ₃ ranges from approximately 5 sccm to approximately 200 sccm, the flow rate of CF ₄ ranges from approximately 20 sccm to approximately 200 sccm, and the flow rate of Ar ranges from approximately 100 sccm to approximately 2,000 sccm.

The second step is to etch the first substrate 100. In a second step, the etch rate is in the range of approximately 1,000 lambda / min to approximately 3,000 dl / min, preferably 2,000 dl / min. As etching conditions, the pressure ranges from approximately 15 mTorr to approximately 30 mTorr. Source power (eg, RF power) ranges from approximately 400 W to approximately 600 W, and bias power to improve the straightness of ions ranges from approximately 80 W to approximately 120 W. Sulfur hexafluoride (SF ₆ ) and O ₂ are used as source gas. The flow rate of SF ₆ ranges from approximately 5 sccm to approximately 200 sccm, and the flow rate of O ₂ ranges from approximately 1 sccm to approximately 100 sccm.

In a second step, an etch process may be performed to etch a portion of the buried insulating layer 100-2 or to etch a portion of the buried insulating layer 100-2 and the first semiconductor layer 100-1. . In the former case, the buried insulating layer 100-2 may be excessively etched by about 100 kPa to about 4,000 kPa. Hereinafter, the etched buried insulating layer 100-2 and the etched first semiconductor layer 100-1 are referred to as a buried insulating pattern 100-2A and a first semiconductor pattern 100-1A, respectively.

Referring to FIG. 2C, barrier layers (not shown) may be formed on the inner surfaces of the via hole 110 (see FIG. 2B) and the contact hole 109 (see FIG. 2B). The barrier layer is a titanium (Ti) layer, titanium nitride (TiN) layer, tantalum (Ta) layer, tantalum nitride (TaN) layer, aluminum silicon titanium nitride (AlSiTiN) layer, nickel titanium (Niti) layer, titanium boron nitride (TiBN) ) Layer, a zirconium boron nitride (ZrBN) layer, a titanium aluminum nitride (TiAlN) layer, a titanium diboride (TiB ₂ ) layer, and laminated structures thereof, such as a Ti / TiN layer and a Ta / Tan layer. It may comprise one layer selected from the group. In order to minimize the reduction in the width of the contact holes 109, in particular the via holes 110, the barrier layer may be less than 100 GPa, preferably approximately 50 GPa, using an atomic layer deposition (ALD) process with good step coverage. It is formed to a thickness of approximately 100 mm 3. The barrier layer can also be formed through a metal organic chemical vapor deposition (MOCVD) process or a physical vapor deposition (PVD) process.

In addition, the barrier layer may include an oxide layer such as a silicon oxide layer, a nitride layer such as a silicon nitride layer, and a stacked structure thereof such as a nitride / oxide layer. In the case of a nitride / oxide layer, the oxide layer and nitride layer are formed in the liner such that the nitride / oxide layer has an overall thickness of less than 200 GPa. In this way, the reduction in the width of the via hole 110 is minimized.

The contact hole 109 and the via hole 110 are filled with a conductive material to form the first contact plug 111 and the alignment key 112. The conductive material may include one material selected from the group consisting of copper (Cu), platinum (Pt), tungsten (W), aluminum (Al), and alloys thereof. The conductive material is not limited to the materials listed above, but includes any metal or metal alloy having conductive properties. When W is used as the conductive material, a chemical vapor deposition (CVD) process or an ALD process is performed. When Al is used as the conductive material, a CVD process is used. When copper (Cu) is used as the conductive material, an electroplating process or a CVD process is performed.

As disclosed above, the first contact plug 111 and the alignment key 112 may be formed simultaneously. In addition, the alignment key 112 may be formed after forming the first contact plug 111, or vice versa. If the first contact plug 111 and the alignment key 112 are not formed at the same time, they may be formed of different materials. For example, the first contact plug 111 is formed of impurity-doped polysilicon, and the alignment key 112 is formed of the material disclosed above.

Referring to FIG. 2D, first to fourth interconnect layers 113, 116, 119 and 122, second to fourth contact plugs 115, 118 and 121, and second to fifth interlayer insulating layers 114, 117, 120, and 123 are formed. For example, a portion of the first interconnect layer 113 among the first to fourth interconnect layers 113, 116, 119, and 122 is electrically disconnected from the first contact plug 111 and the first contact plug. And another portion of the first interconnect layer 113 to the alignment key 112.

The first through fourth interconnect layers 113, 116, 119 and 122 are formed through a deposition process and an etching process. The first through fourth interconnect layers 113, 116, 119 and 122 are formed of a conductive material, for example a metal or an alloy containing at least two metals. Preferably, the first to fourth interconnect layers 113, 116, 119 and 122 are formed of aluminum (Al). The second to fourth contact plugs 115, 118, and 121 are formed in the second to fifth interlayer insulating layers 114, 117, 120, and 123 through a damascene process. In order to electrically connect the first to fourth interconnect layers 113, 116, 119 and 122 which are stacked vertically, the second to fourth contact plugs 115, 118 and 121 may be formed of a conductive material, for example. For example, it is formed of an impurity-doped polysilicon and a metal, or an alloy containing at least two metals. Preferably, the second to fourth contact plugs 115, 118, and 121 are formed of tungsten (W). The second to fifth interlayer insulating layers 114, 117, 120, and 123 are oxide layers selected from the group consisting of BPSG layers, PSG layers, BSG layers, USG layers, TEOS layers, HDP layers, and stacked structures thereof. It may include. In addition, the second to fourth interlayer insulating layers 114, 117, and 120 may be planarized using a CMP process.

There is no restriction on the number and structure of layers of the first to fourth interconnect layers 113, 116, 119 and 122 and the second to fourth contact plugs 115, 118 and 121. The number and structure of layers of interconnect layers and contact plugs can vary widely depending on the device design.

The front passivation layer 124 is formed over the fifth interlayer insulating layer 123. The front passivation layer 124 may include one layer selected from the group consisting of a BPSG layer, a PSG layer, a BSG layer, a USG layer, a TEOS layer, and an HDP layer. Preferably, front passivation layer 124 is formed using a TEOS layer or HDP layer with a thickness of approximately 1,000 GPa to approximately 40,000 GPa. In addition, the front passivation layer 124 may include a nitride layer or a stacked structure of an oxide layer and a nitride layer.

Front passivation layer 124 is planarized. The planarization process can be performed via a chemical mechanical polishing (CMP) process.

Thermal treatment may be performed to densify front passivation layer 124. Thermal treatment can be carried out through an annealing process using a furnace.

Referring to FIG. 2E, the first substrate pattern 100A fabricated through the processes of FIGS. 2A to 2D is coupled to the second substrate 200. The bonding process is performed using one method selected from the group consisting of oxide / oxide bonds, oxide / silicon bonds, oxide / metal bonds, mole oxides / adhesives / oxide bonds, and oxide / adhesive / silicon bonds.

For example, the oxide / oxide (formed on the second substrate 200) bond and the oxide / silicon (silicon substrate) bond are two substrates after plasma treatment and water treatment using O ₂ or N ₂ . To combine them. In addition to the method of joining two substrates after water treatment, the two substrates may be joined together after chemical treatment with amines. In an oxide / metal (formed on second substrate 200) bond, the metal layer may be formed of a metal such as titanium (Ti), aluminum (Al) or copper (Cu). In oxide / adhesive / oxide bonds and oxide / adhesive / silicone bonds, benzocyclobutyne (BCB) can be used as the adhesive member.

Referring to FIG. 2F, a back grinding process is performed to grind the back surface of the first substrate pattern 100A (see FIG. 2E). In this case, if the alignment key 112 is formed to pass through the buried insulation pattern 100-2A, the alignment key 112 is exposed by performing a back grinding process until the buried insulation pattern 100-2A is exposed. do. During this process, the buried insulation pattern 100-2A may be removed by a predetermined thickness. On the other hand, if the alignment key 112 is formed without passing through the buried insulation pattern 100-2A, that is, if the alignment key 112 extends into the buried insulation pattern 100-2A by a predetermined depth, the buried insulation Pattern 100-2A may be partially or completely removed to expose alignment key 112. Alternatively, the buried insulating pattern 100-2A may be etched through a separate etch process.

Referring to FIG. 2G, the buried insulation pattern 100-2A (see FIG. 2F) remaining on the second semiconductor pattern 100-3A is locally removed. The removal process is performed through a wet etch process. For example, when the buried insulation pattern 100-2A includes a silicon nitride layer, a wet etch process is performed using a buffered oxide etchant (BOE) or diluted HF (DHF).

Referring to FIG. 2H, the back passivation layer 125 is formed on the second semiconductor pattern 100-3A from which the buried insulation pattern 100-2A (see FIG. 2F) is removed. The back passivation layer 125 has a stacked structure of a first insulating layer and a second insulating layer having different refractive indices. The silicon oxide layer may be selected from the group consisting of natural oxide layers, grown oxide layers, and deposited oxide layers. The grown oxide layer is formed through one of a dry oxidation process, a wet oxidation process, and a radiative ion oxidation process. The deposited oxide layer is formed through a chemical vapor deposition (CVD) process. The silicon oxide layer and silicon nitride layer are formed to have a thickness of about 2 nm to about 50 nm and about 100 nm to about 500 nm, respectively.

On the other hand, the deposition process of the back passivation layer 125 having a multilayer structure may be performed in-situ in the same chamber to obtain increased stability and reduced processing time of the fabrication process. If an in-situ process is not possible, the deposition process may be performed ex-situ in different chambers.

In the back passivation layer 125, a silicon nitride layer is deposited on the back side of the alignment key 112. However, an etch-back process or CMP process is additionally performed to selectively remove a portion deposited on the backside of the alignment key 112. Thus, the back side of the alignment key 112 is exposed.

Referring to FIG. 2I, a transparent conductive layer 126 is formed over the back passivation layer 125. The permeable layer 126 is a TCO layer. The transmissive layer 126 may comprise one selected from the group consisting of an ITO layer, a ZO layer, a SnO and a ZTO layer. The ITO layer is doped with one selected from the group consisting of CO, Ti, W, Mo, and Cr. The ZO layer may be doped with one selected from the group consisting of Mg, Zr, and Li. The TCO layer is formed to have a thickness of about 10 nm to about 500 nm. The transparent conductive layer 126 may include a polysilicon layer or a metal layer. The polysilicon layer is formed to have a thickness of about 1 nm to about 40 nm for light transmission. The metal layer may be gold (Au) or platinum (Pt). The metal layer is formed to have a thickness of about 0.1 nm to about 1 nm.

Referring to FIG. 2J, the first planarization layer 127 may be formed on the transparent conductive layer 126. The first planarization layer 127 may be formed of an organic material.

The color filter 128 and the microlens 130 are formed on the first planarization layer 127. The second planarization layer 129 may be formed between the color filter 128 and the microlens 130. The second planarization layer 129 may be formed of an organic material.

Thereafter, a low temperature oxide (LTO) layer 130 is formed to cover the microlens 130.

The first substrate pattern 100A and the second substrate 200 are packaged by a packaging process. The packaging process includes a wire bonding process and a sawing process. Wire bonding is accomplished by coupling the pad to an external chip through the wire. Silicon through connections through interconnects 112 to bond pads rather than permeable conductive oxides are achieved by conventional techniques.

Embodiments of the present invention can achieve the following effects.

First, compared to conventional CMOS image sensors (front-illuminated image sensors), a back-illuminated image sensor that is illuminated from the back of a substrate (e.g., a semiconductor device) provides for the loss of light incident to the light receiving element. Can be minimized, increasing the light receiving effect.

Secondly, a back passivation layer is formed to prevent reflection of light incident on the back of the substrate. Therefore, the light collection efficiency of the light receiving element can be increased to improve the light receiving efficiency.

Third, the transparent conductive layer is formed on the back passivation layer of the substrate (eg, semiconductor layer). A negative voltage (-) is applied to the transparent conductive layer. Thus, it is possible to minimize the generation of dark currents and to prevent dark currents from the backside of the substrate from flowing to the light receiving element. Alternatively a positive voltage (+) is applied to the transparent conductive layer to invert the back side to prevent dark current from the back side of the substrate.

Fourth, in a method for fabricating a back-illuminated image sensor using a back grinding process, an alignment key having a via hole shape is formed in the substrate before the back grinding process of grinding the back side of the substrate, and the back grinding target of the substrate. This is controlled during the back grinding process. Thus, control of the back grinding process is facilitated.

Fifth, the rear side of the alignment key is connected to the transparent conductive layer. Thus, the negative voltage applied by the negative applying unit is transmitted to the transparent conductive layer through the alignment key. The negative voltage applying unit may be disposed on the second substrate rather than the first substrate. Various designs are possible in the packaging process.

Although the present invention has been described with reference to specific embodiments, the above embodiments of the present invention are for illustration and not limitation. In particular, although the invention has been applied to a CMOS image in an embodiment, the invention can be applied to any other charge coupled device (CCD), backlit image sensors, or 3D structured integrated devices.

It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the claims below.

Claims (26)

A method for manufacturing a back lit image sensor,
Forming a light-receiving element proximate the front side of the substrate;
Forming an interconnect layer over the front surface of the substrate;
Forming a transparent conductive layer proximate to the light receiving element on a back surface of the substrate; And
Forming a conductive alignment key electrically connecting the interconnect layer and the transparent conductive layer, the conductive alignment key extending between the interconnect layer and the transparent conductive layer through the substrate;
And a method for fabricating a back lit image sensor. The method of claim 1,
Forming the interconnect layer comprises forming a patterned metal layer and a patterned insulating layer. The method of claim 2,
Forming the patterned metal layer and the patterned insulating layer comprises forming a plurality of patterned metal layers and a plurality of patterned insulating layers. The method of claim 1,
Forming the interconnect layer includes forming a plurality of patterned metal layers, wherein the conductive alignment key is electrically connected to a patterned metal layer furthest from the front side of the substrate. How to make it. The method of claim 1,
Forming the transmissive conductive layer comprises forming the transmissive conductive layer from a material selected from the group consisting of ITO, ZO, SnO, and ZTO. The method of claim 5,
Wherein the transmissive conductive layer comprises an ITO layer, the method further comprising doping the ITO layer with an impurity selected from the group of impurities consisting of Co, Ti, W, Mo, and Cr. Method for manufacturing the sensor. The method of claim 5,
The transmissive conductive layer comprises a ZO layer, the method further comprising doping the ZO layer with an impurity selected from the group of impurities consisting of Mg, Zr, and Li. Way. The method of claim 1,
Wherein said transmissive conductive layer comprises a polysilicon layer, a noble metal layer, or both. The method of claim 1,
Forming the light receiving element comprises forming a photodiode on the substrate. The method of claim 1,
And forming both a color filter and a microlens on the transparent conductive layer in proximity to the light receiving element. A method for manufacturing a back lit image sensor,
Forming a light receiving element on the substrate;
Forming an interlayer insulating layer over said substrate in proximity to said light receiving element;
Forming an alignment key spaced apart from the light receiving element and passing through the interlayer insulating layer and the substrate;
Forming a plurality of interconnect layers in a multilayer structure over the interlayer dielectric layer, wherein the metal layer of the multilayer structure is electrically connected to the alignment key;
Forming a front passivation layer over the frontmost outermost layer of the plurality of interconnect layers;
Forming a back passivation layer on the substrate;
Forming a transmissive conductive layer over the back passivation layer proximate the light receiving element, the transmissive conductive layer being formed to be electrically connected to the alignment key;
And a method for fabricating a back lit image sensor. The method of claim 11,
And forming both a color filter and a microlens on the transparent conductive layer in proximity to the light receiving element. The method of claim 11,
Forming a further substrate over the front passivation layer. The method of claim 13,
Forming the back passivation layer comprises forming a multilayer structure comprising layers formed from materials having different indices of refraction. The method of claim 11,
And the back passivation layer comprises a layer having a lower index of refraction than the substrate. The method of claim 13,
And the back passivation layer comprises a layer having a lower index of refraction than the substrate. The method of claim 11,
Coupling an additional substrate in close proximity to the front passivation layer. The method of claim 17,
Wherein the additional substrate comprises a silicon-on-insulator substrate. The method of claim 11,
Forming the transmissive conductive layer comprises forming the transmissive conductive layer from a material selected from the group consisting of ITO, ZO, SnO, and ZTO. The method of claim 19,
The transmissive conductive layer comprises an ITO layer, the method further comprising doping the ITO layer with an impurity selected from the group of impurities consisting of Co, Ti, W, Mo, and Cr. Method for manufacturing the sensor. The method of claim 19,
The transmissive conductive layer comprises a ZO layer, the method further comprising doping the ZO layer with an impurity selected from the group of impurities consisting of Mg, Zr, and Li. Way. The method of claim 11,
Wherein said transmissive conductive layer comprises a polysilicon layer, a noble metal layer, or both. A method for manufacturing a back lit image sensor,
Forming an alignment key through a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate is a buried insulator disposed between a first semiconductor layer, a second semiconductor layer, the first semiconductor layer and the second semiconductor layer A layer, wherein the alignment key passes through the second semiconductor layer, the buried insulator layer, and partially passes through the first semiconductor layer;
Forming a light receiving element in the second semiconductor layer;
Forming a patterned metal layer proximate a rear surface of the second semiconductor layer, the patterned metal layer being formed to be electrically connected to the alignment key;
Removing the first semiconductor layer to expose the alignment key and the buried insulating layer; And
Removing the buried insulation layer to expose the alignment key using one or more processes to selectively remove the buried insulation layer while leaving exposed portions of the alignment key generally intact.
And a method for fabricating a back lit image sensor. The method of claim 23, wherein
Removing the first semiconductor layer comprises back-grinding the first semiconductor layer by a predetermined amount until the buried insulating layer and the alignment key are exposed. Method for manufacturing the sensor. 25. The method of claim 24,
Removing the buried insulator layer comprises selectively removing portions of the buried insulator layer from the second semiconductor layer using an etching process. The method of claim 25,
Wherein the etching comprises a wet etch process.

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