KR20090105176A - Liquid crystal display device and driving method of the same - Google Patents

Abstract

PURPOSE: A liquid crystal display and a driving method thereof are provided to improve image quality by supplying a corrected common voltage according to the pixel data. CONSTITUTION: A liquid crystal panel(102) includes a plurality of pixel areas in which a plurality of gate lines and data lines intersect. A data counter(110) counts the gradation value of the digital data outputted to each sub pixel in the pixel area. A common voltage generator(112) supplies the corrected common voltage to the liquid crystal panel by correcting the common voltage according to the count value after quantizing the count value.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method capable of reducing a die size and improving image quality.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such a flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting device, and the like.

Among them, the liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a liquid crystal cell and a driving circuit for driving the liquid crystal panel. The driving circuit drives the liquid crystal cell so that the image information is displayed on the liquid crystal panel.

In such a liquid crystal display device, an inversion driving method such as a frame inversion system, a line column inversion system, and a dot inversion system is used to drive pixels on the liquid crystal display panel. This is used.

The frame inversion type liquid crystal display panel driving method inverts the polarity of the data voltage (or data signal) supplied to the pixels on the liquid crystal display panel every time the frame is changed. In the liquid crystal display panel driving method of the line inversion method, the polarities of the data signals supplied to the pixels are inverted according to a line (column) on the liquid crystal display panel. In the dot inversion method, a data signal having a polarity opposite to that of the data signals supplied to neighboring pixels in the vertical and horizontal directions is supplied to each pixel on the liquid crystal display panel, and is supplied to every pixel on the liquid crystal display panel every frame. Causes the polarity of the data signals to be reversed. Of these inversion driving methods, the dot inversion method provides an image having excellent image quality compared to the frame and line inversion methods.

1 is a view showing a conventional liquid crystal display device.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 for displaying an image by driving a liquid crystal by a voltage between a pixel electrode and a common electrode, and data lines DL1 to DLm of the liquid crystal panel 2. To control the data driver 4 for driving the gate driver, the gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2, and the driving timing of the data and gate drivers 4 and 6; And a common voltage generator 10 for supplying the common voltage Vcom to the liquid crystal panel 2.

The liquid crystal panel 2 includes a thin film transistor TFT formed in a region defined by n gate lines GL1 through GLn and m data lines DL1 through DLm, and a liquid crystal connected to the thin film transistor TFT. With cells. The thin film transistor TFT supplies data from the data lines DL1 to DLm to the liquid crystal cell in response to a scan signal from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The timing controller 8 generates a gate control signal and a data control signal using a vertical / horizontal synchronization signal Vsync / Hsync, a data enable DE signal, and a predetermined clock signal supplied from a system (not shown).

The gate driver 4 supplies a scan signal, that is, a gate high voltage VGH, to the gate lines GL1 to GLn according to the gate control signal generated from the timing controller 8.

The data driver 6 supplies data voltages for one horizontal line to the data lines DL1 to DLm in accordance with the data control signal generated from the timing controller 8.

The common voltage generator 10 generates a common voltage Vcom, which is a DC voltage of a constant level, using the power supply voltage Vdd supplied from a power supply unit (not shown). The common voltage Vcom is a reference voltage of the liquid crystal panel 2 and becomes a voltage for driving the liquid crystal filled in the liquid crystal panel 2.

As shown in FIG. 2, the common voltage generator 10 of the liquid crystal display configured as described above includes a first resistor and a second resistor R1 and R2 for dividing the power supply voltage VDD, a first resistor and The variable resistor VR1 and the first capacitor C1 connected to the second resistors R1 and R2 to adjust the level of the divided power supply voltage VDD, and the first and second resistors R1 and R2. The power supply voltage VDD, which is divided by the power supply and controlled by the variable resistor VR1 and the first capacitor C1, is applied to the non-inverting terminal (+) and fed back from its output signal and the liquid crystal panel. The signal is supplied to the third resistor (R3), the fourth resistor (R4) and the second capacitor (C2) to receive a voltage whose compensation level is adjusted to the inverting terminal (-) and output the signal to the common electrode voltage (Vcom). 1 includes an operational amplifier 20.

As such, the common voltage generator has a problem in that dies, such as resistors, operational amplifiers, and capacitors, must be disposed on a substrate, and die size increases despite the size of the LCD. Will occur.

In addition, although the pixel data supplied to the pixel region of the liquid crystal panel is random, the common voltage supplied is fixed to one voltage, thereby degrading the image quality of the liquid crystal display.

In order to solve the above problems, the present invention can reduce the production cost and die size of the conventional common voltage generator, and can improve the image quality by supplying a common voltage corrected according to the pixel data supplied to the liquid crystal panel. There is provided a liquid crystal display device and a driving method.

A liquid crystal display according to the present invention comprises: a liquid crystal panel in which a plurality of pixel regions are formed in an area where a plurality of gate lines and a plurality of data lines cross each other; A data counter unit for counting a gray value of digital data output to each sub-pixel of the pixel area; And a common voltage generator for quantizing the count value counted by the data counter and supplying a corrected common voltage corrected to the common voltage supplied to the liquid crystal panel according to the quantized count value.

In addition, the driving method of the liquid crystal display according to the present invention includes a liquid crystal panel including a liquid crystal panel having a plurality of pixel regions formed in an area where a plurality of gate lines and a plurality of data lines cross each other, wherein the pixel region is provided. Counting, by the data counter unit, the gradation value of the digital data output to each sub-pixel of the? And quantizing the count value counted by the data counter part, correcting the common voltage supplied to the liquid crystal panel according to the quantized count value, and supplying the corrected common voltage by the common voltage generator. .

The liquid crystal display according to the present invention reduces die size by configuring a common common voltage integrated circuit (Vcom IC), unlike the conventional passive and active devices to supply a common voltage. To reduce costs.

In addition, the gray scale value of the digital data supplied to each sub-pixel in the pixel area of the liquid crystal display device is counted by the data counter unit, the counted count value is quantized, and the common voltage corrected with reference to the look-up table initially set is obtained. It is possible to improve the display quality of the liquid crystal display device by supplying to.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

3 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal panel 102 in which a plurality of pixel regions are formed in a region where a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm intersect, and pixels supplied to each pixel region. The data counter unit 110 for counting the gray scale value of the data and the common voltage generator 112 for adjusting the common voltage supplied to the liquid crystal panel 102 by quantizing the gray scale value counted by the data counter unit 110 are provided. It is configured to include.

The liquid crystal panel 102 includes a lower substrate and an upper substrate bonded to each other. At this time, the lower substrate and the upper substrate is configured to include a spacer (not shown) and a liquid crystal layer (not shown) to maintain a constant gap thereof.

The lower substrate is each liquid crystal cell region defined by crossing a plurality of data lines DL1 through DLm and a plurality of gate lines GL1 through GLn, and crossing the data lines DL and gate lines GL. And a pixel electrode of the liquid crystal cell Clc connected to the formed thin film transistor (TFT) and the thin film transistor TFT. In this case, the thin film transistor TFT supplies an image signal from the data line DL to the liquid crystal cell Clc in response to a gate pulse from the gate line GL.

The liquid crystal cell CLc may be equivalently represented as a liquid crystal capacitor because the liquid crystal cell CLc includes a common electrode Vcom facing the liquid crystal layer and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell also includes a storage capacitor Cst for maintaining the image signal charged in the liquid crystal capacitor until the next image signal is charged.

The upper substrate includes at least three color filters including red, green, and blue, a separation of each color filter, a black matrix defining a pixel cell, a common electrode Vcom supplied with a common voltage, and the like. Here, the common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. In the horizontal electric field driving method, the pixel electrode is formed on the lower glass substrate together with the pixel electrode. On the upper glass substrate and the lower glass substrate of the liquid crystal panel 102, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The timing controller 104 arranges the source data R, G, and B supplied from the outside into a data signal Data suitable for driving the liquid crystal panel 102, and arranges the aligned data signal Data in the data driver 106. Supplies). In addition, the timing controller 104 uses the main clock DCLK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync input from the outside, and the data control signal DCS and the gate control signal ( GCS) is generated to control driving timing of each of the data driver 106 and the gate driver 108. In this case, the data control signal DSC includes a source start pulse SSP, a source shift clock SSC, a source output enable SOE, and the gate control signal GCS includes a gate start pulse. GSP), a gate output enable signal (GOE), and a plurality of gate shift clocks (GSCs).

The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is a timing control signal for sequentially shifting the gate start pulse GSP by being input to a shift register in the gate driving circuit and having a pulse width corresponding to the ON period of the thin film transistor TFT. Is generated. The gate output signal GOE indicates the output of the gate driver 108.

In addition, the timing control signals include data timing control signals including a source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like. The source sampling clock SSC instructs a latch operation of data in the data driver 106 based on a rising or falling edge. A source output enable signal (SOE) indicates the output of the data driver 106. The polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal panel 102.

In addition, the timing controller 104 separates the digital video data into odd pixel data RGBodd and even pixel data RGBeven and supplies the data to the data driving circuit 106. In order to reduce the swing width of the EMI and the data voltage on the data transmission path, the timing controller 104 modulates the data by mini-low-voltage differential signaling (LVDS) or reduced swing differential signaling (RSDS). 106).

The data driver 106 adjusts the digital video data R, G, and B from the timing controller 104 according to the polarity control signal POL according to the data control signal DCS supplied from the timing controller 104. It converts into analog positive / negative gamma compensation voltage corresponding to and generates positive / negative analog data voltage and analog to one horizontal line image signal every one horizontal period in which scan signal is supplied to gate line GL. The data voltage is supplied to the data lines DL1 to DLm. In this case, the data driver 106 may be mounted on a tape carrier package or a chip on film and connected to the liquid crystal panel 102 or may be a chip on glass method. 102).

The gate driver 108 sequentially generates scan pulses, that is, gate pulses, and supplies them to the plurality of gate lines GL1 to GLn in response to the gate driving control signals GOE, GSP, and GSC supplied from the timing controller 104. do. At this time, the gate driver 108 is supplied with a power supply voltage Vdd from a power supply unit. Accordingly, the gate driver 108 generates the gate high voltage VGH and the gate low voltage VGL using the power supply voltage Vdd.

The gate driver 108 is a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a liquid crystal cell, and an output connected between the level shifter and the gate lines GL1 to GLn. Each buffer is configured. The gate driver 108 sequentially outputs scan pulses. In this case, the gate driver 108 is mounted on a COF or TCP and connected to gate pads formed on the lower substrate of the liquid crystal panel 102 by an anisotropic conductive film (ACF). In addition, the gate driver 108 simultaneously with the plurality of data lines DL1 to DLm, gate lines GL1 to GLn, and thin film transistors TFT formed in the pixel array using a gate in panel process. It may be formed directly on the lower glass substrate of the liquid crystal panel 102. In addition, the gate driver 108 may be directly bonded to the lower glass substrate of the liquid crystal panel 102 by a chip on glass (Ghip On Galss) method.

The data counter 110 receives the digital video data R, G, and B supplied to each pixel area from the timing controller 104. Here, the data counter 110 supplies the common voltage generator 112 with a count value Data_Sum that counts the gray value of digital data to be supplied to the R, G, and B subpixels of each pixel area in horizontal line units. do.

The common voltage generator 112 receives the count value Data_Sum counted by the data counter 110 and supplies the common voltage to the liquid crystal panel 102. The common voltage generator 112 is configured as a common voltage integrated circuit (Vcom IC), each of which can be programmed instead of an individual device. In this case, as shown in FIG. 4, the common voltage generator 112 includes the common voltage controller 114, the first and second quantization processors 124 and 126, the offset setting unit 118, and the lookup table ( 120, the common voltage correction unit 122 is configured.

The common voltage controller 114 processes the count value Data_Sum supplied from the data counter 110 and outputs a control signal. Here, the common voltage controller 114 supplies the count value Data_Sum supplied from the data counter 110 to the first quantization processor 124 to set an initial value to be stored in the lookup table 120. After processing the count value Data_Sum supplied in the execution mode by using the lookup table 120 set in the initialization mode, the appropriate common voltage is supplied by referring to the lockup table 120. Outputs a control signal for

The first quantization processor 124 quantizes the provided count value Data_Sum when the common voltage controller 114 is in an initialization mode. Here, the first quantization processing unit 124 sets the initial value to the look-up table 120 so that the maximum value is the maximum value in the gray value of the positive digital data of the liquid crystal panel 102 and the maximum value is the value in the gray value of the negative digital data. The data value of the lookup table 120 is quantized by counting the count value Data_Sum according to the range of the address defined in the lookup table 120 as shown in FIG. 5. Save it to the field.

The offset setting unit 118 quantizes the count value Data_Sum and corresponds to each count value Data_Sum 1 using a value corresponding to a range of grayscale values of the digital data stored in the data summation field of the lookup table 120. In order to compensate for the measured value, that is, the common voltage compensation value to be corrected at the default common voltage Vcom is measured and stored in the lookup table 120. In other words, the offset setting unit 118 uses the count value Data_Sum quantized by the first quantization processing unit 124 and stored in each lookup table address (LUT Address) to obtain a common voltage suitable for the liquid crystal panel 102. After the measurement, the result is stored in the lookup table 120.

The second quantization processor 126 quantizes the count value Data_Sum supplied by the common voltage controller 114 when the common voltage controller 114 is in the execution mode. Here, the second quantization processing unit 126 supplies the quantized count value Data_Sum to the lookup table 120.

As illustrated in FIG. 5, the lookup table 120 may correspond to each address in an initialization setting mode according to a range of addresses defined in the lookup table 120. By using the gray value of the quantized digital data in the digital data stored in each address and the common voltage value to be measured by the offset setting unit 118 is provided. In addition, the lookup table 120 is supplied to the second quantization processing unit 126 from the common voltage controller 114 in the execution mode, searches for a range corresponding to the quantized count value Data_Sum, and corrects the common voltage Vshift. It is provided to be supplied to the common voltage correction unit 122.

At this time, the look-up table 120 is installed after setting and storing the field values of the look-up table 120 in a device having a first quantization processing unit 124 and an offset setting unit 118 for setting the initial value separately Can be.

The common voltage corrector 122 adds the common voltage Vshift to be corrected supplied from the lookup table 120 and the default common voltage Vcom to generate a common voltage Pvcom suitable for the gray value of the digital data. Supplies).

In other words, as illustrated in FIG. 6A, the pixel voltages of 1280 × 800 and the positive and negative polarities of the liquid crystal cell are repeatedly applied in the gate line direction, and the data levels are W (White) and B ( Black), W, B ... or B, W, B, W ... on the liquid crystal panel repeatedly displayed, for example, each subpixel If the grayscale that can be output is 6 bits, the gray scale value of 0 to 63 gray scales, that is, the maximum negative digital data in Normally Wihte Mode, is the maximum polarity gray scale of the subpixel x (number of pixel areas × pixels). Number of subpixels (R, G, B) in the region) / 2. In other words, the maximum digital data output value of negative polarity is −120960 at −63 × (1280 × 3) / 2 and the grayscale value of the maximum digital data of positive polarity may be represented as 120960 at 63 × (1280 × 3) / 2. have.

As described above, as shown in FIG. 5, an address area defined in the lookup table 120 is quantized by the first quantization processing unit 124. If there are 32 LUT Address spaces, the range between -120960 and 12960 is divided into 32 and stored, and the offset setting unit 118 actually measures the corresponding value and then Vcom shift of the lookup table 120. Save it to the field.

Subsequently, when the pixel data to be executed is input to the timing controller 104, the common voltage generator of the execution mode is used to count the count value Data_Sum which counted the digital video data R, G, and B inputted to the data counter 110. Supplied to 112.

Next, the common voltage generator 112 supplies the input count value Data_Sum to the second quantization processor 126 and searches the voltage Vshift to be corrected by referring to the lookup table 120 with the quantized data. do.

Subsequently, when the data having the gray scale value (−120960) of the maximum negative digital data is input as described above, as shown in FIG. 6B, the lookup table 120 is referred to the default common voltage Vcom. When the common voltage corrected by ΔV ₁ = 0.300 [V] is supplied to the liquid crystal panel 102 and has the maximum positive digital gradation value 120960, as shown in FIG. 6C, at the default common voltage Vcom. The common voltage corrected by ΔV ₂ = -0.300 [V] is supplied to the liquid crystal panel 102 with reference to the lookup table 120.

The liquid crystal display device, unlike supplying a common voltage using conventional passive and active elements, is configured as a programmable common voltage integrated circuit (Vcom IC), thereby reducing die size and cost. Can reduce the cost.

In addition, the gray scale value of the digital data supplied to each sub-pixel in the pixel area of the liquid crystal display device is counted by the data counter, the counted count value is quantized, and the common voltage corrected with reference to the initially set look-up table is used. It is possible to improve the display quality of the liquid crystal display device by supplying to.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a view showing a conventional liquid crystal display device.

2 is a diagram illustrating a common voltage generator of a conventional liquid crystal display.

3 is a view showing a liquid crystal display according to an embodiment of the present invention.

4 is a diagram illustrating a common voltage generator according to an exemplary embodiment of the present invention.

5 is a view showing a look-up table according to an embodiment of the present invention.

6A to 6C illustrate common voltage correction according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

112: common voltage generator 114: common voltage controller

118: offset setting unit 120: look-up table

122: common voltage correction unit 124, 126: first and second quantization processing units

Claims (8)

A liquid crystal panel in which a plurality of pixel regions are formed in regions where the plurality of gate lines and the plurality of data lines cross each other; A data counter unit for counting a gray value of digital data output to each sub-pixel of the pixel area; And a common voltage generator for quantizing the count value counted by the data counter and supplying a corrected common voltage corrected to the common voltage supplied to the liquid crystal panel according to the quantized count value. Display. The method of claim 1, The common voltage generator is a programmable common voltage integrated circuit (Vcom IC). The method of claim 1, And the data counter unit counts a gray value of digital data of each horizontal line unit supplied to the plurality of data lines. The method of claim 1, The common voltage generator, A common voltage controller for processing a count value supplied from the data counter and outputting a control signal in an initialization mode or an execution mode; First and second quantization processing units for quantizing the gray level values supplied to the common voltage controller; An offset setting unit for setting a common voltage to be corrected by using the first gray level value quantized by the first quantization processing unit in the initialization mode; A look-up table storing a common voltage to be corrected set by the offset setting unit corresponding to the first gray level value quantized by the first quantization processor; And a common voltage corrector configured to process and output the common voltage and the common voltage to be corrected with reference to the lookup table according to the second grayscale value processed by the second quantization processor in the execution mode. Liquid crystal display device. A driving method of a liquid crystal display device comprising a liquid crystal panel in which a plurality of pixel regions are formed in an area where a plurality of gate lines and a plurality of data lines intersect. Counting, by a data counter, a gray value of digital data output to each sub-pixel in the pixel area; And quantizing the count value counted by the data counter, correcting the common voltage supplied to the liquid crystal panel according to the quantized count value, and supplying the corrected common voltage by the common voltage generator. Driving method of liquid crystal display device. The method of claim 5, wherein The counting step, And a gray value of digital data of each horizontal line unit supplied to the plurality of data lines. The method of claim 5, wherein Supplying the common voltage, Processing a count value supplied from the data counter unit in a common voltage controller and outputting a control signal in an initialization mode or an execution mode; Quantizing a first count value in a first quantization processor in the initialization mode; Storing the quantized first count value in a look up table; And measuring, by an offset setting unit, a common voltage to be corrected corresponding to a count value stored in the look-up table and storing the common voltage in the look-up table. The method of claim 7, wherein Quantizing a second count value in a second quantization processor in the execution mode; Mapping the quantized second count value to the lookup table; Outputting a common voltage to be corrected in the lookup table corresponding to the quantized second count value; And outputting a common voltage corrected using the common voltage and the common voltage to be corrected by the common voltage corrector.

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