KR20090072297A - Array substrate for display device and method of fabricating the same - Google Patents

Abstract

An array panel for a display device and a manufacturing method thereof maintaining the performance characteristic of a switching device are provided to block static electricity which is generated among the manufacturing process the display panel. A video data is inputted to a data line. A gate line is crossed toward data line. The scan signal is inputted to the gate line. Common voltage is inputted to the common voltage input line. A display pixel(100) and a static electricity prevention circuit unit(200) are formed in an intersection unit of the gate line and the data line. A switching thin film transistor is connected to data line and gate line. The display pixel includes a storage capacitor for the storage of video data.

Description

Array substrate for display device and manufacturing method thereof {Array substrate for display device and method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a display device and a method of manufacturing the same, and more particularly, to an array substrate for a display device and a method of manufacturing the same, wherein an antistatic circuit is configured for each pixel to minimize damage from static electricity.

Among the display devices, for example, liquid crystal displays have advantages of small size, thinness, and low power consumption, and are used as notebook computers, office automation devices, and audio / video devices. In particular, an active matrix liquid crystal display device using a thin film transistor (hereinafter referred to as "TFT") as a switch element is suitable for displaying a dynamic image.

FIG. 1 is a block diagram showing a basic configuration of a general liquid crystal display device, and is largely divided into a liquid crystal panel 2 and an LCM driving circuit unit 26.

In each configuration, the interface 10 includes data (RGB Data) and control signals (input clock, horizontal synchronous signal, vertical synchronous signal, data input) input from the drive system such as a personal computer to the LCM drive circuit unit 26. Able signal, etc.) are input and supplied to the timing controller 12. Low voltage differential signal (LVDS) interface and TTL interface are mainly used for data and control signal transmission from the drive system. In addition, the interface function may be collected and used together with the timing controller 12 in a single chip.

As illustrated in FIG. 2, the liquid crystal panel 2 forms a plurality of pixel regions by crossing a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn on a glass substrate. In the region, a thin film transistor TFT and a liquid crystal LC are configured to form a liquid crystal pixel to display a screen.

The timing controller 12 drives a source driver 18 composed of a plurality of drive integrated circuits and a gate driver 20 composed of a plurality of gate driver integrated circuits using a control signal input through the interface 10. Generate a control signal for In addition, the data input through the interface 10 is transmitted to the source driver 18.

The reference voltage generator 16 generates reference voltages of a digital to analog converter (DAC) used in the source driver 18. Reference voltages are set by the producer based on the transmittance-voltage characteristics of the panel.

The source driver 18 selects reference voltages of the input image data in response to control signals input from the timing controller 12, and controls the rotation angle of the liquid crystal molecules by supplying the selected reference voltage to the liquid crystal panel 2. do.

The gate driver 20 performs on / off control of thin film transistors TFTs arranged on the liquid crystal panel 2 in response to control signals input from the timing controller 12. Source driver 18 by sequentially driving thin film transistors TFT on the liquid crystal panel 2 by one line by sequentially enabling the gate lines GL1 to GLn by one horizontal synchronizing time. The analog image signals supplied from the plurality of pixels are applied to the pixels connected to the respective TFTs.

The power supply voltage generator 14 supplies operating power of each component and generates and supplies a common electrode voltage of the liquid crystal panel 2.

Although not shown, the apparatus further includes a backlight unit having one or more lamps to supply light to the liquid crystal panel 2.

3, a non-display in which an image is not displayed in order to prevent static electricity from flowing into a liquid crystal pixel (or display area A / A), which is generally formed inside the liquid crystal panel 2. An electrostatic discharge (ESD) prevention circuit (hereinafter referred to as an ESD circuit) is configured in the region NA / A.

The ESD circuit 50 is generally configured at the inlet of the data line to which the aspect data is applied to the liquid crystal pixel. In general, the ESD circuit 50 forms a circuit through a diode connection of a thin film transistor (TFT) and common high voltage static electricity introduced into the data line is common. The voltage Vcom flows to the common wiring CL to which the voltage Vcom is applied.

However, the method of configuring the ESD circuit 50 in the non-display area NA / A of the liquid crystal panel 2 may prevent static electricity flowing into the display area A / A from the outside. The static electricity generated inside the display area A / A does not perform any function at all.

That is, for example, the static electricity generated in the alignment layer rubbing process or the polarizer attachment process performed in the array substrate manufacturing process of the liquid crystal panel 2 may not be blocked.

The present invention has been made to solve the above problems, it is possible to block the static electricity generated in the array manufacturing process of the display panel using a liquid crystal panel or E-ink, such as to prevent the inflow of the display pixel more reliable It aims to provide.

In order to achieve the above object, the present invention includes a data line to which the image data is input; A gate line crossing the data line and to which a scan signal is input; A common voltage input line to which a common voltage is input; The present invention provides an array substrate for a display device including a display pixel formed at an intersection of the data line and the gate line and an antistatic circuit part.

In the array substrate, the display pixel may be formed of one of liquid crystal and E-ink.

In the array substrate, the display pixel may include a switching thin film transistor connected to the data line and the gate line, respectively.

In the array substrate, the display pixel may include a storage capacitor for storing the image data.

In the array substrate, the common voltage input line is formed in parallel with the gate line.

In the array substrate, the antistatic circuit portion comprises: a first antistatic element configured between the data line and the common voltage input line; A second antistatic device configured between the data line and the gate line; And a third antistatic device configured between the gate line and the common voltage input line.

The first to third antistatic devices may be thin film transistors.

Each of the first antistatic device and the third antistatic device has a diode connection structure.

The second antistatic device is controlled by a voltage input to the common voltage input line.

In addition, the present invention includes the steps of defining a pixel region with a data line and a gate line crossing each other on the substrate; Forming a display pixel including a common voltage input line and a switching thin film transistor in the pixel area; It provides a method of manufacturing an array substrate for a display device comprising forming an antistatic circuit portion in the pixel region.

In the manufacturing method, the switching thin film transistor, forming a gate line, a gate electrode connected to the gate line, and the common voltage input line on the substrate; Forming a gate insulating layer on the gate line, the gate electrode, and the common voltage input line; Forming a data line intersecting the gate line on the gate insulating layer, a semiconductor layer, a source electrode connected to the data line on the semiconductor layer, and a drain electrode spaced apart from the source electrode; Forming a protective layer having the data line, the source and drain electrodes, and a drain contact hole exposing a portion of the drain electrode on the exposed gate insulating layer; The method may further include forming a pixel electrode in an area that does not overlap the gate line on the passivation layer.

In the manufacturing method, the antistatic circuit portion is a first to third thin film transistor, the first thin film transistor is formed to be connected to the data line and the common voltage input line, the second thin film transistor and the data line The third thin film transistor may be connected to the gate line and the common voltage input line, and the third thin film transistor may be connected to the gate line and the common voltage input line.

The first to third thin film transistors may be formed simultaneously with the switching thin film transistor.

According to the present invention having the above characteristics, it is possible to block the static electricity generated during the manufacturing process of the display panel flowing into the display pixel to maintain a stable operating characteristics of the switching element, and also to manufacture the display panel without additional process There is an advantage.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

FIG. 4 is an equivalent pixel circuit diagram illustrating an array substrate for a display device according to an exemplary embodiment of the present invention. FIG. 4 illustrates an example of a display device using liquid crystal.

First, the biggest feature of the array substrate for a display device according to the present invention is that an antistatic circuit is configured for each display pixel.

Therefore, referring to FIG. 4, an array substrate for a display device according to an exemplary embodiment of the present invention includes a display pixel 100 and an antistatic circuit part at an intersection of a data line D and a gate line G defined as one pixel area P. There is a characteristic that constitutes 200) at the same time.

The display pixel 100 is illustrated as a liquid crystal display pixel that displays an image according to an electric field applied between the common electrode and the pixel electrode using the liquid crystal Clc. However, the display pixel 100 may also be an E-ink or the like.

Accordingly, the display pixel 100 includes a switching thin film transistor TFT connected to the gate line G and the data line D, and includes a liquid crystal Clc and a storage capacitor connected to the switching thin film transistor TFT. Cst is configured. In the display pixel 100, the switching thin film transistor TFT is controlled to be switched by a scan signal input from the gate line G, and the image data input to the data line D is stored in the storage capacitor. Cst) and is written to the liquid crystal Clc to display an image.

In addition, the antistatic circuit unit 200 is configured together with the display pixel 100 to form a pixel area P for one pixel, and various antistatic circuits may be applied. The antistatic circuit unit used will be described by way of example.

The antistatic circuit formed in the antistatic circuit unit 200 includes first to third thin film transistors TFT1 to TFT3, each of which is an NMOS type.

Accordingly, the first thin film transistor TFT1 is formed in parallel with the data line D and the gate line G, to which image data is supplied, so that the common voltage input line CL is supplied with a common voltage Vcom to a common electrode. A diode connection structure is disposed between the first and second diodes, and the static electricity flowing from the data line D to the display pixel 100 is blocked.

The second thin film transistor TFT2 is configured between the data line D and the gate line G, and is switched by the voltage supplied from the common voltage input line CL, thereby switching the common voltage input line ( Blocking of static electricity flowing into the display pixel 100 from CL) is performed.

The third thin film transistor TFT3 has a diode connection structure between the common voltage input line CL formed in parallel with the gate line G, and the display pixel 100 is formed from the gate line G. Shut off static electricity entering the system.

As described above, even the static electricity generated in the display panel by the first to third thin film transistors TFT1 to TFT3 can block the inflow into the display pixel 100 and thus the switching thin film transistor configured in the display pixel 100. There is an advantage that can prevent the destruction of the (TFT) or the characteristic change.

FIG. 5 is a flowchart illustrating a method of manufacturing an array substrate for a display device according to the present invention, which will be described with reference to FIG. 4.

First, the pixel region P in which the display pixel 100 and the antistatic circuit unit 200 are to be formed is defined as a data line D and a gate line G crossing each other on the substrate.

When the pixel area is defined, the display pixel is formed by including the common voltage input line CL (st2), and the antistatic circuit part 200 is formed simultaneously with the display pixel 100 (st3). )

In this case, since the constant residual prevention circuit part 200 includes first to third thin film transistors TFT1 to TFT3, the constant residual prevention circuit part 200 may be formed at the same time when the switching thin film transistor TFT of the display pixel 100 is formed.

For example, referring to FIG. 6, a manufacturing process of the switching thin film transistor TFT is described below. First, a gate electrode 302 connected to the gate line G at a lowermost layer of the substrate 300, and a gate insulating layer at an upper layer thereof. 304). Next, a semiconductor layer 306 including an active layer 306a and an ohmic contact layer 306b is formed on the gate insulating layer 304, and source and drain electrodes 308 and 310 spaced apart from each other on the semiconductor layer 306. The source electrode 308 is connected to the data line D.

Next, a protective layer 312 is formed on the exposed semiconductor layer 306 and the source and drain electrodes 308 and 310.

Although not shown, a drain contact hole for exposing a part of the drain electrode 310 of the switching TFT is formed, and a pixel electrode is formed on the passivation layer 312 so that the pixel electrode and the drain electrode are mutually formed. Configure to connect.

Although not shown in the drawings, a liquid crystal layer is formed on the array substrate, and a color filter substrate having a common electrode and a color filter is positioned at a position opposite the array substrate with the liquid crystal layer interposed therebetween.

The first to third thin film transistors TFT1 to TFT3 of the antistatic circuit part 200 are also configured in the same manner as the switching thin film transistor TFT manufactured by the above-described method. Only the connection configuration of each electrode of the thin film transistors TFT1 to TFT3 is different.

Therefore, the manufacturing process by the anti-static circuit unit 200 in the manufacturing process of the array substrate for a display device according to the present invention has the advantage that can be formed at the same time in the manufacturing of the switching thin film transistor (TFT).

1 is a block diagram showing the basic configuration of a general liquid crystal display device

FIG. 2 is a view schematically illustrating a configuration of a liquid crystal panel among the components of FIG. 1.

3 is a view for explaining the configuration of the antistatic circuit according to the prior art;

4 is an equivalent pixel circuit diagram illustrating an array substrate for a display device according to an exemplary embodiment of the present invention.

5 is a flowchart illustrating a method of manufacturing an array substrate for a display device according to the present invention.

6 is a cross-sectional view illustrating a manufacturing process of a switching thin film transistor (TFT) in the configuration of an array substrate for a display device according to the present invention.

<Brief description of the main parts of the drawing>

D: data line G: gate line

CL; Common voltage input line P: pixel area

100: display pixel 200: antistatic circuit portion

TFT: Switching Thin Film Transistor

TFT1 to TFT3: first to third thin film transistors

Claims (13)

A data line to which image data is input; A gate line crossing the data line and to which a scan signal is input; A common voltage input line to which a common voltage is input; Display pixels and anti-static circuits formed at the intersection of the data line and the gate line Array substrate for display device comprising a The method according to claim 1, The display pixel is an array substrate for a display device, characterized in that consisting of one of the liquid crystal, E-ink The method according to claim 1, The display pixel includes a switching thin film transistor connected to the data line and the gate line, respectively. The method according to claim 1, The display pixel includes a storage capacitor for storing the image data. The method according to claim 1, And the common voltage input line is formed in parallel with the gate line. The method according to claim 1, The antistatic circuit portion, A first antistatic device configured between the data line and the common voltage input line; A second antistatic device configured between the data line and the gate line; A third antistatic device configured between the gate line and the common voltage input line Array substrate for display device comprising a The method of claim 6, Wherein the first to third antistatic devices are thin film transistors. The method of claim 6, Wherein the first antistatic device and the third antistatic device each have a diode connection structure. The method of claim 6, And the second antistatic device is controlled to be switched by a voltage input to the common voltage input line. Defining a pixel region with data lines and gate lines crossing each other on the substrate; Forming a display pixel including a common voltage input line and a switching thin film transistor in the pixel area; Forming an antistatic circuit part in the pixel region Method of manufacturing an array substrate for a display device comprising a The method of claim 10, The switching thin film transistor, Forming the gate line, a gate electrode connected to the gate line, and the common voltage input line on the substrate; Forming a gate insulating layer on the gate line, the gate electrode, and the common voltage input line; Forming a data line intersecting the gate line on the gate insulating layer, a semiconductor layer, a source electrode connected to the data line on the semiconductor layer, and a drain electrode spaced apart from the source electrode; Forming a protective layer having the data line, the source and drain electrodes, and a drain contact hole exposing a portion of the drain electrode on the exposed gate insulating layer; Forming a pixel electrode in an area that does not overlap the gate line on the passivation layer; Method of manufacturing an array substrate for a display device comprising a The method of claim 10, The antistatic circuit portion is a first to third thin film transistor, the first thin film transistor is formed to be connected to the data line and the common voltage input line, the second thin film transistor is the data line, the gate line and the And a third thin film transistor connected to the common voltage input line, the third thin film transistor connected to the gate line and the common voltage input line. The method according to claim 12, Wherein the first to third thin film transistors are formed simultaneously with the switching thin film transistor.

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