KR20090044469A - Apparatus and method for driving liquid crystal display of 2 dot inversion type - Google Patents

Abstract

The present invention relates to a technique for preventing a horizontal line phenomenon from occurring due to a luminance difference between horizontal lines in a 2-dot inversion driving liquid crystal display device. The present invention includes a timing controller for appropriately varying the even-numbered high section of the source out enable signal or the gate out enable signal to solve the unbalance of the charge amount between the even horizontal line and the odd horizontal line; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel and a data driver for supplying a pixel signal to each data line are achieved.

2-dot inversion, horizontal phenomenon

Description

 A device and method for driving a 2-dot inversion liquid crystal display device {APPARATUS AND METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY OF 2 DOT INVERSION TYPE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technology of a liquid crystal display device, and more particularly, to a driving device and a method of a two-dot inversion liquid crystal display device suitable for preventing a horizontal line phenomenon generated in a two-dot inversion driving method.

Recently, with the development of information technology (IT), the importance of the flat panel display device as a visual information transmission medium has been further emphasized, and low power consumption, thinning, light weight, and high quality are required to secure improved competitiveness in the future.

A liquid crystal display (LCD), which is a typical display device of a flat panel display device, is an apparatus for displaying an image using optical anisotropy of liquid crystal, and has advantages such as thin, small size, low power consumption, and high quality.

Such a liquid crystal display device is a display device in which image information is individually supplied to pixels arranged in a matrix, and a desired image is displayed by adjusting light transmittance of the pixels. Accordingly, the liquid crystal display includes a liquid crystal panel in which pixels, which are the smallest unit for implementing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. Since the LCD does not emit light by itself, a backlight unit is provided to supply light to the LCD. The driver includes a timing controller and a data driver and a gate driver.

FIG. 1 is a block diagram of a liquid crystal display according to the related art, and as shown therein, a gate control signal GDC and a data control signal DDC for controlling driving of the gate driver 12 and the data driver 13. A timing controller 11 for outputting the digital pixel data RGB and reordering the digital pixel data RGB; A gate driver 12 for supplying a gate signal to each gate line GL1 to GLn of the liquid crystal panel 14; A data driver 13 for supplying a pixel signal to each of the data lines DL1 to DLm of the liquid crystal panel 14; The liquid crystal panel 14 includes a liquid crystal cell driven by the gate signal and the pixel signal in a matrix form to display an image. The operation thereof will be described as follows.

The timing controller 11 may include a gate control signal GDC for controlling the gate driver 12 and a data control signal for controlling the data driver 13 using a vertical / horizontal synchronization signal and a clock signal supplied from the system. DDC). In addition, the timing controller 11 samples digital pixel data (hereinafter, referred to as 'data') RGB input from the system, rearranges the digital pixel data (hereinafter referred to as 'data'), and supplies the same to the data driver 13.

Examples of the gate control signal GDC include a gate start pulse GSP, a gate shift clock GSC, a gate out enable GOE, and the like. As an example of the data control signal DDC, a source start pulse SSP), source shift clock SSC, source out enable SOE, polarity signal POL, and the like.

The gate driver 12 sequentially supplies the gate signals to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 11, thereby supplying the gate signals to the gate lines GL1 to GLn. The connected thin film transistor TFT is turned on in the corresponding gate line unit.

The data driver 13 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 11. The pixel signal thus converted is supplied to the data lines DL1 to DLm on the liquid crystal panel 14.

The liquid crystal panel 14 has a data line (DL1~DLm) and a gate line, to the intersection of the (GL1~GLn) having a plurality of liquid crystal cells (C _LC) disposed in a matrix form a plurality of liquid crystal cells (C _LC Are driven by the pixel signal and the gate signal to display a desired image.

For reference, in the above description, the gate driver 12 and the data driver 13 are described as being separately installed from the liquid crystal panel 14, but recently, they are COF (Chip On Film) and COG (Chip On Glass). There is a tendency to be mounted on the liquid crystal panel 14 by mounting techniques, such as these.

Such a liquid crystal display uses an inversion method to prevent deterioration of the liquid crystal cells. In particular, the liquid crystal display device provides an excellent image quality compared to other inversion methods, but to compensate for the dot inversion method that consumes a lot of power. The vertical two-dot inversion scheme as shown in FIG. 2B is mainly used.

2A and 2B illustrate polarities of pixel signals supplied to liquid crystal cells in a vertical two-dot inversion scheme divided into odd frames (previous frames) and even frames (current frames). In the odd and even frames shown in FIGS. 2A and 2B, the vertical two-dot inversion scheme changes the polarity of the pixel signal in dots in the horizontal direction, as in the conventional dot inversion scheme, while in the vertical direction. It is characterized by a change of 2 dots.

3 is a waveform diagram of a pixel signal driven according to the vertical 2-dot inversion scheme.

However, in the vertical two-dot inversion method, a difference in charging amount appears between the even horizontal line and the odd horizontal line due to the load characteristic of the data driver 13, which is represented by the luminance difference. For example, FIG. 4 illustrates the charging charge amount of two pixels that are continuous in the vertical direction in FIG. 2A or FIG. 2B, and the charging charge amount Qo of a pixel positioned in an odd horizontal line is an even horizontal line. It can be seen that less than the charge amount Qe of the pixel located at.

The reason for this is that in the case of pixels in the odd horizontal line, the polarity is changed from the positive (+) to the negative (-) signal and vice versa, which requires a relatively long charging rise time or fall time. For example, the pixel located on the even horizontal line is changed in a signal of the same polarity, so that less time is required.

In this case, based on the TN mode, a pixel located in the odd horizontal line and having a small amount of charging charge Qo is positioned in the even horizontal line, and thus, is brighter than a pixel having a large amount of charged charge Qe. As a result, a luminance difference is generated between the odd horizontal line and the even horizontal line. As a result, a 2-line dim phenomenon occurs on the screen as shown in FIG. 5.

The horizontal line phenomenon may be caused by the pixel voltage deviation due to the parasitic capacitance between two adjacent gate lines, and FIGS. 6A and 6B show a generation portion and an equivalent circuit of the parasitic capacitance.

That is, parasitic capacitance Cpp is generated between the storage metal for the storage capacitance and the pixel electrode of the previous stage near the adjacent gate line GLn and GLn + 1, thereby generating a luminance difference between the corresponding horizontal lines. As shown in FIG. 5, a horizontal line phenomenon occurred on the screen.

In the conventional liquid crystal display device in which the vertical 2-dot inversion method is applied as described above, the luminance between the odd horizontal line and the even horizontal line is changed by the parasitic capacitance between two adjacent horizontal lines due to the difference in the charge amount between the even horizontal line and the odd horizontal line. A difference is generated, which causes a problem in that a horizontal line (2-Line Dim) phenomenon occurs.

Accordingly, an object of the present invention is to prevent the luminance difference between the odd horizontal line and the even horizontal line by appropriately changing the interval of the gate-out enable signal with respect to the even horizontal line.

In order to achieve the above object, the present invention provides a timing controller for varying an even-numbered high section of a source out enable signal or a gate-out enable signal so that an unbalanced charge amount can be eliminated between an even horizontal line and an odd horizontal line. Wow; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to a gate signal control signal supplied from the timing controller; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel in response to a data signal control signal supplied from the timing controller.

According to yet another aspect of the present invention, a memory for changing the even-highest period of the source out enable signal or the gate out enable signal is not connected or the header information of the memory does not satisfy the condition. Otherwise, outputting the even-highest period of the source out enable signal or the gate out enable signal as it is; If the memory for changing the even-highest period of the source out enable signal or the gate-out enable signal is connected and the header information of the memory satisfies the condition, the even-numbered source of the source out enable signal or the gate out enable signal is And adjusting the high section according to a value set by the controller in the memory.

According to an embodiment of the present invention, an unbalanced charge amount between an even horizontal line and an odd horizontal line is obtained by appropriately increasing the even-high period of a source out enable signal or a gate-out enable signal so that the output time of the corresponding even-numbered pixel signal is correspondingly reduced. The phenomenon is eliminated, and thereby there is no luminance difference between the odd horizontal line and the even horizontal line, thereby preventing the occurrence of a horizontal line (2-Line Dim) phenomenon.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 7 is a block diagram showing an embodiment of a driving apparatus of a two-dot inversion liquid crystal display according to the present invention. As shown therein, the driving of the gate driving unit 72 and the data driving unit 73 is controlled. The gate control signal GDC and the data control signal DDC are output, and the even-highest period of the source-out enable signal or the gate-out enable signal is appropriately varied so that the charge amount between the even and the odd horizontal lines can be changed. A timing controller 71 for eliminating an imbalance phenomenon; A gate driver 72 outputting a gate signal to each gate line GL1 to GLn of the liquid crystal panel 74 in response to a gate signal control signal supplied from the timing controller 71; A data driver 73 for supplying a pixel signal to each of the data lines DL1 to DLm of the liquid crystal panel 74 in response to a data signal control signal supplied from the timing controller 71; It includes a liquid crystal panel 74 having a liquid crystal cell driven by the gate signal and the pixel signal in the form of a matrix to display an image.

The timing controller 71 is configured to vary the even-highest period of the source out enable signal or the gate out enable signal based on the header value stored in the EPI rom 71A.

Referring to Figures 8 to 10 attached to the operation of the present invention configured as described above in detail as follows.

The timing controller 71 in the control board 70 uses a vertical / horizontal synchronization signal Hsync / Vsync and a clock signal CLK supplied from the system to control the gate driver 72. And a data control signal DDC for controlling the data driver 73. In addition, the timing controller 71 samples the digital pixel data RGB input from the system, rearranges the digital pixel data RGB, and supplies the same to the data driver 73.

The gate driver 72 sequentially supplies the gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 71, thereby corresponding thin film transistor TFT on the horizontal line. ) Are turned on. Accordingly, pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

In more detail, the gate driver 72 shifts the gate start pulse according to the gate shift clock to generate a shift pulse. The gate driver 72 supplies a gate signal consisting of gate on / off sections (signals) to the corresponding gate line GL in a horizontal period in response to the shift clock. In this case, the gate driver 72 supplies the gate-on signal only in the enable period in response to the gate-out enable signal, and supplies the gate-off signal (gate low signal) in other periods.

The data driver 73 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 71. The pixel signal thus converted is supplied to the data lines DL1 to DLm on the liquid crystal panel 74.

In more detail, the data driver 73 generates a sampling signal by shifting the source start pulse according to the source shift clock. Subsequently, the data driver 73 sequentially inputs and latches the pixel data RGB in predetermined units in response to the sampling signal. The data driver 73 converts the latched pixel data RGB for one line into an analog pixel signal and supplies the same to the data lines DL1 to DLm. In this case, the data driver 73 converts the positive and negative pixel signals in response to the polarity control signal. For example, the data driver 73 inverts the pixel signal in a vertical two-dot inversion manner in response to a polarity control signal whose polarity is inverted every two horizontal periods. The data driver 73 supplies the pixel signals to the data lines DL1 to DLm only during the enable period in response to the source output enable signal.

The liquid crystal panel 74 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC And a thin film transistor (TFT) connected to each of them.

The thin film transistor TFT is turned on when the gate signal is supplied from the gate line GL, and supplies the pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when the gate off signal is supplied through the gate line GL to maintain the pixel signal charged in the liquid crystal cell C _LC .

The liquid crystal cell C _LC includes a pixel electrode connected to a common electrode and a thin film transistor TFT with a liquid crystal interposed therebetween. The liquid crystal cell C _LC further includes a storage capacitor C _ST so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In the liquid crystal cell C _LC , an arrangement state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, and light transmittance is adjusted accordingly to implement gradation.

For reference, in the above description, the gate driver 72 and the data driver 73 are separately installed from the liquid crystal panel 74. However, in recent years, they are COF (Chip On Film) and COG (Chip On Glass). There is a trend to be mounted on the liquid crystal panel 14 by a mounting technique such as).

The liquid crystal display device of the present invention is driven by a vertical two-dot driving method. When the on periods of all the gate signals are set at the same interval, the even horizontal line and the odd horizontal line are caused by the load characteristic of the data driver 73. Differences in the amount of charging charge appear between the lines and this is indicated by the luminance difference.

The reason why the luminance difference between the even horizontal line and the odd horizontal line is generated is that the voltage of the pixel located on the odd (or even) horizontal line is a positive polarity (+) signal to a negative polarity signal (-) or vice versa. As the polarity change is made, it requires a relatively long rise time or fall time, and thus the charging time is insufficient. On the other hand, the voltage of the pixel located in the even (or odd) horizontal line is changed in the signal of the same polarity. This is because less time is required, which allows more charging time.

The luminance difference between the even horizontal line and the odd horizontal line may be generated by parasitic capacitance between two adjacent gate lines.

In this case, based on the TN mode, a pixel located in the odd horizontal line and having a small amount of charge charges is located in the even horizontal line, so that it is relatively brighter than a pixel having a large charge amount, and thus the luminance between the odd horizontal line and the even horizontal line is increased. Differences were generated, thereby causing a 2-Line Dim phenomenon.

Therefore, in the present invention, the EPIROM 71A is added to the control board 70, and by using this, the even-numbered high section of the source out enable signal SOE is varied as shown in FIG. The imbalance between the charge charges between the lines was eliminated.

For example, when the even-highest period of the source out enable signal SOE is increased, the output time of the even-numbered pixel signal is correspondingly reduced. Therefore, as shown in FIG. 8, if the odd-high section of the source-out enable signal SOE is fixed and the even-numbered high section is appropriately increased, an unbalanced charge amount between the even and the odd horizontal lines may be eliminated.

Hereinafter, the process of changing the even-highest period of the source out enable signal SOE to eliminate the unbalance of the charge amount between the even / odd horizontal lines will be described.

When the power is turned on, the timing controller 71 checks whether the ypyrom 71A is connected to itself and does not perform the high section variable process of the source out enable signal SOE. (S1, S4)

The timing controller 71 reads the first column of the Y pyrom 71A as shown in FIG. 10 when it is found that the Y pyrom 71A is connected to the timing controller 71. The first column is a header, and a high section variable process of the source out enable signal SOE is performed according to this value (S2).

If any one of the data values of addresses 00h to 04h among the header values is 'FFh', the section variable process of the source out enable signal SOE is not performed. In other words, even if the values of addresses 05h and 06h are changed, if any of the data values of addresses 00h to 04h is 'FFh', the originally set high section is not changed without changing the even-highest section of the source out enable signal SOE. Keep it the same (S3, S4)

If all data values of addresses 00h to 04h are recorded as '00' in the header, the length of the high section of the source out enable signal SOE is determined according to the data values of the addresses 05h and 06h (S5).

The data value of the address 05h is a value for determining the odd-high period of the source out enable signal SOE, and is set to a fixed value (eg, 0.279 μs) according to the model. In contrast, the data value of address 06h is a value that determines the even-highest interval of the source out enable signal SOE, and is adjusted by the coordinator in the production process, for example, within a range of 0.279 μs to 3.007 μs. Is set in.

To this end, the coordinator connects the PC or controller to the YPIROM 71A through a connector, and sets the even-highest section of the source out enable signal within the range of 0.279 μs to 3.007 μs. At this time, the screen is set to an optimal value that does not generate 2-Line Dim through several adjustments.

In addition, the data value of the address 07h is a value that determines the access period of the EPI rom 71A in order for the timing controller 71 to perform a high section variable process of the source out enable signal SOE.

That is, the upper bit value of the data value of the address 07h is a value for determining whether the periodic access operation is '1', the periodic access operation is performed, and '0' does not perform the periodic access operation. The lower bit value of the data value of the address 07h is a value for determining the access period. If the value is '1', the access operation is performed every 55 frame periods. If the value is '0', the access operation is performed only when the blue 31 gray pattern is used.

In other words, if the data value of the address 07h is '00' or '01', no periodic access operation is performed. In addition, when the data value of the address 07h is '10', the access operation is performed every 55 frame periods. In addition, when the data value of the address 07h is '11', the access operation is performed only when the blue (or white) 31 gray pattern is used.

For reference, the remaining portion of the data region of the Ypyrom 71A of FIG. 10 except for the header portion of the first column is a data region related to color coordinate information or company information.

In the above description, the high period of the source out enable signal SOE is varied in order to eliminate the luminance difference between the odd horizontal line and the even horizontal line, but the present invention is not limited thereto.

As another example of this, the high section of the gate-out enable signal GOE may be varied. In this case, the same effect may be obtained.

1 is a block diagram of a liquid crystal display device according to the prior art.

2A and 2B are pixel polarity arrangement diagrams of a frame in a vertical 2-dot inversion scheme.

3 is a waveform diagram of a pixel signal of a vertical 2-dot inversion method;

4 is a waveform diagram showing the charge amount of an odd-numbered pixel.

5 is a schematic diagram of a screen in which a horizontal line phenomenon occurs due to a luminance difference between adjacent horizontal lines;

6A is a plan view of a liquid crystal panel showing a site of generation of parasitic capacitance.

6B is an equivalent circuit diagram of a liquid crystal panel according to generation of parasitic capacitance.

Fig. 7 is a block diagram of a drive device for a 2-dot inversion liquid crystal display device according to the present invention.

8 is a waveform diagram illustrating a variable section of a source out enable signal.

9 is a control flowchart of a driving method in a two-dot inversion liquid crystal display device according to the present invention;

10 is a data format diagram of Ypyrom applied to the present invention.

*** Description of the symbols for the main parts of the drawings ***

70: control board 71: timing controller

71A: YPIROM 72: Gate driver

73: data driver 74: liquid crystal panel

Claims (7)

A timing controller for varying the even-numbered high section of the source out enable signal or the gate-out enable signal according to the high section variable information of the memory to eliminate an unbalanced charge amount between the even horizontal line and the odd horizontal line; A gate driver for outputting a gate signal to each gate line of the liquid crystal panel in response to a gate signal control signal supplied from the timing controller; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel in response to a data signal control signal supplied from the timing controller. The apparatus of claim 1, wherein the memory comprises two pyroms. The apparatus of claim 1, wherein the variable information of the high section of the memory is recorded in a header area of the memory. The method of claim 1, wherein the high section variable information includes information indicating whether to perform a high section variable process, information indicating how much to vary, and determining an access cycle of the memory to perform a high section variable process. At least one information driving device for a two-dot inversion liquid crystal display device characterized in that it is included. A first process of outputting the even-highest period of the source out enable signal or the gate-out enable signal when the change condition of the even-highest high section of the source out enable signal or the gate-out enable signal is not satisfied. and; If the condition for changing the even-highest period of the source out enable signal or the gate-out enable signal is satisfied, adjust the even-highest period of the source out enable signal or the gate-out enable signal according to the adjuster's setting value. And a second step of outputting the driving method. The change condition of the even-highest period of the source out enable signal or the gate-out enable signal is not a memory for changing the even-highest period or the header information of the memory satisfies the condition. And a case where it is not included. 6. The method of claim 5, wherein the setting value of the second process is set to a value at which the horizontal line phenomenon does not occur through several modifications while the adjuster looks at the screen.

Images