KR101467213B1 - Apparatus for driving liquid crystal display of 2 dot inversion type - Google Patents

Abstract

The present invention relates to a technique for preventing a horizontal line phenomenon from occurring due to a difference in charge charge amount between a horizontal line in which the polarity of a pixel signal is changed and a horizontal line in which the polarity of the pixel signal is not changed in a version with a two- According to the present invention, there is provided a liquid crystal display device comprising: a timing controller for adjusting and outputting an ON period of a gate signal for a horizontal line having no change in polarity of a pixel signal and a horizontal line having a polarity change; And a gate driver for outputting a gate signal input from the timing controller to each gate line of the liquid crystal panel. The adjustment of the on duration of the gate signal is achieved by adjusting the duration of the gate masking signal or adjusting the output timing of the gate masking signal.

Horizontal line phenomenon, gate masking signal

Description

 BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a driving apparatus for a 2-dot inversion liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique of a liquid crystal display device, and more particularly to a driving device of a version liquid crystal display device having two dots suitable for preventing a horizontal line phenomenon generated in a version driving method with two dots.

2. Description of the Related Art In recent years, as information technology (IT) has advanced, flat panel displays have become more important as visual information delivery media. In order to secure more competitive power in the future, low power consumption, thinness, lightness and high image quality are required.

Description of the Related Art [0005] A liquid crystal display (LCD), which is a typical display device of a flat panel display, is an apparatus for displaying an image using optical anisotropy of a liquid crystal, and has advantages of thinness, small size, low power consumption and high image quality.

Such a liquid crystal display device is a display device capable of displaying a desired image by individually supplying image information to pixels arranged in a matrix form and adjusting the light transmittance of the pixels. Therefore, the liquid crystal display device includes a liquid crystal panel in which pixels, which are minimum units for realizing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. In addition, since the liquid crystal display device can not emit light by itself, a backlight unit for supplying light to the liquid crystal display device is provided. The driving unit includes a timing controller, a data driving unit, and a gate driving unit.

1 is a block diagram of a conventional liquid crystal display device. As shown in FIG. 1, a gate control signal GDC and a data control signal DDC for controlling the driving of the gate driver 12 and the data driver 13, A timing controller 11 for sampling the digital pixel data RGB, rearranging and outputting the sampled pixel data RGB; A gate driver 12 for supplying gate signals to the gate lines GL1 to GLn of the liquid crystal panel 14; A data driver 13 for supplying pixel signals to the data lines DL1 to DLm of the liquid crystal panel 14; And a liquid crystal panel 14 driven by the gate signal and the pixel signal to display an image.

The timing controller 11 generates a gate control signal GDC for controlling the gate driving unit 12 and a data control signal for controlling the data driving unit 13 using the vertical and horizontal synchronizing signals and the clock signals supplied from the system DDC). The timing controller 11 samples digital pixel data (RGB) input from the system, reorders them, and supplies the sampled data to the data driver 13.

The gate driver 12 sequentially supplies a gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 11, 14 are selected.

The data driver 13 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray level in response to a data control signal DDC input from the timing controller 11 And supplies the converted pixel signals to the data lines DL1 to DLm on the liquid crystal panel 14. [

The liquid crystal panel 14 has a data line (DL1~DLm) and a gate line, to the intersection of the (GL1~GLn) having a plurality of liquid crystal cells (C _LC) disposed in a matrix form a plurality of liquid crystal cells (C _LC Are driven by the pixel signal and the gate signal to display a desired image.

In the above description, the gate driver 12 and the data driver 13 are separately provided from the liquid crystal panel 14. However, in recent years, they have been widely used in various fields such as COF (Chip On Film), COG (Chip On Glass) In the liquid crystal panel 14 by a mounting technique such as the above.

In order to prevent deterioration of the liquid crystal cells, the liquid crystal display device uses an inversion method. In particular, the liquid crystal display device provides an excellent image quality in comparison with other inversion methods. However, in order to compensate for a power consumption- Method. In other words, when the dot inversion method is used, a flicker phenomenon occurs when the frame frequency is reduced from 50 Hz to 30 Hz at a normal 60 Hz in order to reduce power consumption. In order to compensate for this, a vertical 2 A dot inversion method is used.

FIGS. 2A and 2B show polarity of a pixel signal supplied to the liquid crystal cells divided into a radix frame (previous frame) and an excellent frame (current frame) in a version with a vertical two-dot version. In the odd-numbered frame and the odd-numbered frame shown in Figs. 2A and 2B, the polarity of the pixel signal is changed in the horizontal direction by the dot unit as in the conventional dot-inversion method, There is a characteristic that it changes in 2 dot unit.

However, since the output characteristic of the gate signal is not good due to the characteristic of the GIP (GIP: Gate In Panel) model, when the conventional method of outputting the gate signal only in the actual charging period is employed, the charging time of the pixel is insufficient.

Therefore, a method of opening a gate of a thin film transistor (TFT), which is a switching device, in advance in a pre-charging period before the actual charging period is used. Such a driving method is called a gate overlap overlap) driving method.

3 is a timing chart of a gate signal to which the gate overlap driving method is applied. 3 (a) is a waveform diagram of a pixel signal driven by a vertical two-dot method, and (b) - (e) of FIG. 3 is a waveform diagram of a gate signal of the gate driver 12 according to the gate overlap driving. (GS1 to GS4), and FIG. 3 (f) is a waveform diagram of the gate masking signal (GMS).

It can be seen that the gate masking signals GMS between the first and third gate signals GS1 and GS3 and between the second and fourth gate signals GS2 and GS4 are all set to be the same . As a result, it can be seen that the ON intervals of all the gate signals GS1 to GS are set to the same interval as shown in FIGS. 3B to 3E.

However, due to the load characteristic of the data driver 13, a difference in charging charge amount between the excellent horizontal line and the odd horizontal line appears in the version system with substantially vertical two-dot, which is represented by the luminance difference. For example, FIG. 4 illustrates the amount of charged charges of two consecutive pixels in FIG. 2A or FIG. 2B. When the charged charge amount Qo of a pixel located on the odd horizontal line is equal to an even horizontal line Which is smaller than the charged charge amount Qe of the pixel located.

The reason for this is that for a pixel located in the radial horizontal line, the polarity change is made from a positive (+) to negative (-) signal or vice versa, requiring a relatively long rise or fall time, This is because the pixels located on the excellent horizontal line are changed in the signal of the same polarity, and such a time is less necessary.

In this case, when the TN mode is used as a reference, a pixel having a small amount of charge Qo located on the odd horizontal line is located on the even horizontal line and becomes relatively brighter than a pixel having a large amount of charge Qe. As a result, a luminance difference is generated between the odd horizontal line and the excellent horizontal line, thereby causing a 2-line dim phenomenon on the screen as shown in FIG.

In the conventional liquid crystal display device to which the vertical 2-dot version method is applied, the on period of the gate signal of each horizontal line is set to be the same. As a result, the amount of charge that the polarity inversion is generated is smaller than that of the pixel that does not have polarity inversion. Accordingly, there is a problem that a luminance difference occurs between the odd horizontal line and the excellent horizontal line, thereby causing a 2-line dim phenomenon.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a liquid crystal display device having a two-dot version driving method, which uses a gate masking signal to appropriately adjust the on- And the like.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a timing controller for outputting a gate signal and a data control signal; A gate driver for outputting the gate signal output from the timing controller to each gate line of the liquid crystal panel; And a data driver for generating a pixel signal according to the data control signal output from the timing controller and outputting the pixel signal to each data line of the liquid crystal panel, A data processing unit for sampling pixel data (RGB), rearranging and outputting the sampled pixel data; A timing signal generator for generating first and second gate masking signals having different output timings; A gate masking signal selector for selecting one of the first and second gate masking signals according to a change in the polarity of the pixel signal; And controlling a width of a precharging interval and a charging interval in an ON interval of an original gate signal in accordance with a gate masking signal selected by the gate masking signal selector and controlling a width of the precharging interval and a charging interval, And a gate signal processor for outputting the signal to the gate driver in accordance with a horizontal line having no change in polarity of the signal and a horizontal line having a polarity change of the pixel signal.

And the ON period of the gate signal includes a precharging period and a charging period for the pixel signal.

A gate masking signal period is adjusted or an output timing of the gate masking signal is adjusted in order to vary the interval of the gate signal.

In a liquid crystal display device to which a two-dot version driving method is applied, a gate signal is used to appropriately adjust the on period of a gate signal between horizontal lines and output, thereby changing a polarity of a horizontal signal It is possible to reliably prevent the occurrence of a horizontal line phenomenon due to the difference in luminance between the horizontal lines.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram showing an embodiment of a driving apparatus for a 2-dot inversion type liquid crystal display according to the present invention. As shown in FIG. 6, the gate driving unit 62 and the data driving unit 63 The gate control signal GDC and the data control signal DDC are outputted and the on period of each gate signal for the horizontal line having no change in the polarity of the pixel signal and the horizontal line having the polarity change is used as the gate masking signal A timing controller 61 for adjusting and outputting different outputs; A gate driver 62 for outputting gate signals supplied from the timing controller 61 to the gate lines GL1 to GLn of the liquid crystal panel 64; A data driver 63 for supplying pixel signals to the data lines DL1 to DLm of the liquid crystal panel 64; And a liquid crystal panel (64) for driving liquid crystal cells arranged in a matrix form by the gate signal and the pixel signal to display an image.

The timing controller 61 includes: a data processing unit 61A for sampling digital image data (RGB) input from the outside and rearranging the sampled pixel data; And outputs a gate control signal GDC and a data control signal DDC for controlling the driving of the gate driver 62 and the data driver 63. In addition, A timing signal generator 61B for outputting gate masking signals GMS_even and GMS_odd for the horizontal line; A gate masking signal selector 61C for selecting and outputting a corresponding one of the gate masking signals GMS_even and GMS_odd according to a horizontal line having no change in polarity of the pixel signal and a horizontal line having a polarity change; The ON period of the original gate signal inputted from the timing signal generating section 61B is masked with the gate masking signal inputted from the gate masking signal selecting section 61C so that the horizontal line having no change in the polarity of the pixel signal And a gate signal processing unit 61D which is set differently according to the horizontal line and outputs it to the gate driving unit 62. [

Hereinafter, the operation of the present invention will be described in detail with reference to FIGS. 7 to 9. FIG.

The timing signal generator 61B of the timing controller 61 generates a gate control signal for controlling the gate driver 62 by using the vertical / horizontal synchronizing signal Hsync / Vsync supplied from the system and the clock signal CLK And a data control signal DDC for controlling the data driver 63 and GDC. The data processor 61A of the timing controller 61 samples digital pixel data (RGB) input from the system, reorders the data, and supplies the data to the data driver 63.

The gate driver 62 sequentially supplies the gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 61, 64 are selected.

To be more specific, the gate driver 62 shifts the gate start pulse according to the gate shift clock to generate a shift pulse. In response to the shift clock, the gate driver 62 supplies a gate signal composed of a gate on / off period (signal) to the corresponding gate line GL in each horizontal period. In this case, the gate driver 62 supplies the gate-on signal only in the enable period in response to the gate output enable signal, and supplies the gate-off signal (gate low signal) in the other periods.

The data driver 63 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray level value in response to the data control signal DDC input from the timing controller 61 , And supplies the converted pixel signals to the data lines DL1 to DLm on the liquid crystal panel 64. [

To be more specific, the data driver 63 shifts the source start pulse according to the source shift clock to generate a sampling signal. Subsequently, the data driver 63 sequentially receives and latches the pixel data RGB in units of a predetermined unit in response to the sampling signal. The data driver 63 converts the latched pixel data RGB into analog pixel signals and supplies them to the data lines DL1 to DLm. In this case, the data driver 63 converts the polarity control signal into a positive polarity pixel signal and a negative polarity pixel signal. For example, the data driver 63 inverts the pixel signal in a vertical two-dot inversion manner in response to a polarity control signal whose polarity is inverted every two horizontal periods. The data driver 63 supplies the pixel signals to the data lines DL1 to DLm only in the enable period in response to the source output enable signal.

The liquid crystal panel 64 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC (TFT) connected to each of the TFTs.

The thin film transistor TFT is turned on when a gate signal is supplied from the gate line GL and supplies a pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when a gate off signal is supplied through the gate line GL, so that the pixel signal charged in the liquid crystal cell C _LC is maintained.

The liquid crystal cell C _LC includes a common electrode and a pixel electrode connected to the thin film transistor TFT via a liquid crystal. The liquid crystal cell C _LC further includes a storage capacitor C _ST to maintain the charged pixel signal stably until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In such a liquid crystal cell C _LC , the alignment state of the liquid crystal having dielectric anisotropy is varied according to the pixel signal charged through the thin film transistor (TFT), so that the light transmittance is adjusted to realize the gradation.

In the above description, the gate driving unit 62 and the data driving unit 63 are separately provided from the liquid crystal panel 64. However, in recent years, they have been widely used in various fields such as COF (Chip On Film), COG (Chip On Glass) Or the like mounted on the liquid crystal panel 64 by a mounting technique such as the above.

The liquid crystal display of the present invention is driven by a vertical two-dot driving method, and includes a gate overlap (gate) which opens a gate of a thin film transistor (TFT) which is a switching element in advance by using a gate signal having a precharging interval before an actual charging period gate overlap drive scheme is applied.

However, when the ON intervals of all the gate signals are set to the same interval, there is a difference in charge amount between the excellent horizontal line and the odd horizontal line due to the load characteristic of the data driver 63, which is represented by the luminance difference. The reason for this is that polarity changes from positive (+) to negative (-) signals or vice versa for pixels located on the odd (or even odd) horizontal line and require a relatively long rise or fall time (Or the odd-numbered) horizontal line is changed in the signal of the same polarity, the time required for the pixel is changed, so that the charging time can be relatively secured It is because.

In this case, when a TN mode is used as a reference, a pixel having a small amount of charged charges located on a radial horizontal line is positioned in a superior horizontal line, and becomes relatively brighter than a pixel having a large amount of charged charges, A difference is generated, thereby causing a 2-line dim phenomenon.

Accordingly, in the present invention, the imbalance in the amount of charge charge is eliminated between the pixels located in the odd horizontal line and the odd horizontal line by using the gate masking signal. Hereinafter, a specific embodiment will be described in detail.

In the first embodiment of the present invention, a gate masking signal having a different pulse width is used to control the on period of each gate signal for a horizontal line having no change in polarity of a pixel signal and a horizontal line having a polarity change.

To this end, the timing signal generator 61B outputs the original gate signal for the odd horizontal line and the odd horizontal line. The timing signal generator 61B outputs the gate masking signal with respect to the gate signal of the odd horizontal line shorter than the gate masking signal with respect to the gate signal of the excellent horizontal line.

Here, the radix horizontal line means a horizontal line (n-1 horizontal line, n + 1 horizontal line, n + 3 horizontal line ...) in which the polarity of the pixel signal changes from positive to negative or vice versa, (N horizontal line, n + 2 horizontal line, and n + 4 horizontal line) in which the polarity of the pixel signal is maintained from positive to positive or from negative to negative.

The gate masking signal selecting unit 61C selects and outputs the gate masking signal for the on period of the gate signal of the odd and even horizontal lines at the corresponding time point.

Accordingly, the gate signal processing unit 61D masks the original gate signal of the odd and even horizontal lines inputted from the timing signal generating unit 61B with the gate masking signal inputted from the gate masking signal selecting unit 61C The on period of the gate signal with respect to the odd horizontal line is relatively longer than the on period of the gate signal with the even horizontal line and the gate signal having the adjusted on period is outputted to the gate driver 62 side.

For example, the timing signal generator 61B generates and outputs the gate masking signal for the on period of the gate signal of the odd horizontal line in a short form as shown in (f) of FIG. 7, and outputs the gate signal The gate masking signal for the ON period of the gate signal is generated and outputted in a long form as shown in (e) of FIG.

Accordingly, the ON intervals of the gate signals GS2 and GS4 of the odd horizontal line outputted from the gate signal processing unit 61D are relatively long as shown in Figs. 7B and 7D, The on period of the gate signal of the horizontal line becomes relatively short as shown in Figs. 7 (a) and 7 (c).

The gate signal processing unit 61D outputs the masked gate signals GS1 to GS4 to the gate driver 62 as described above.

The gate signals GS1 to GS4 in FIGS. 7A to 7D correspond to the gate signals GS1 to GS4 in FIGS. 3B to 3E.

That is, the gate signal GS1 of the excellent horizontal line shown in FIG. 7A is a gate signal corresponding to the pixel signal of the n-th positive polarity in FIG. 3A.

The gate signal GS2 of the odd horizontal line shown in FIG. 7B is a gate signal corresponding to the (n + 1) -th negative pixel signal in FIG. 3A.

The gate signal GS3 of the excellent horizontal line shown in FIG. 7C is a gate signal corresponding to the pixel signal of the (n + 2) th negative polarity in FIG. 3A.

The gate signal GS on the odd horizontal line shown in (d) of FIG. 7 is a gate signal corresponding to the (n + 3) th positive pixel signal in FIG.

As a result, by masking the gate signal as described above, a luminance difference is not generated between the odd-numbered horizontal line and the superior horizontal line (between the adjacent two horizontal lines), and a horizontal line (2-Line Dim) phenomenon .

In the second embodiment of the present invention, the timing of the gate masking signal is adjusted to control the ON period of each gate signal for the horizontal line having no change in the polarity of the pixel signal and the horizontal line having the polarity change. The controller 61 includes: a data processing unit 61A for sampling and outputting digital pixel data (RGB) input from the outside; And outputs a gate control signal GDC and a data control signal DDC for controlling the driving of the gate driver 62 and the data driver 63. In addition, A timing signal generator 61B for adjusting and outputting the output timings of the gate masking signals GMS_even and GMS_odd for the horizontal lines; A gate masking signal selector 61C for selecting and outputting a corresponding one of the gate masking signals GMS_even and GMS_odd according to a horizontal line having no change in polarity of the pixel signal and a horizontal line having a polarity change; The pre-charging period or the charging period of the original gate signal inputted from the timing signal generator 61B is adjusted according to the gate masking signals GMS_even and GMS_odd inputted from the gate masking signal selector 61C, And a gate signal processing unit 61D for outputting different signals. This will be described with reference to FIG.

The timing signal generator 61B outputs the original gate signals for the odd horizontal lines and the even horizontal lines. 9 (a) is a waveform diagram of a pixel signal driven by a vertical two-dot version system, and FIGS. 9 (b) - (e) show gate signals GS1 to GSn output from the timing signal generator 61B. GS4).

The timing signal generator 61B adjusts the timing of the gate masking signal (GMS) to adjust the precharging period or the charging period of the pixel signal. 9 (h) and 9 (i) are waveform diagrams of excellent and odd gate masking signals GMS_even and GMS_odd in the prior art, and FIGS. 9 (f) and 9 (GMS_even) and (GMS_odd) of the adjusted odd and even number of gate masking signals GMS_even and GMS_odd.

As shown in FIGS. 9F and 9H, the excellent gate masking signal GMS_even according to the present invention is outputted in a delayed manner as compared with the prior art gate masking signal GMS_even. As shown in FIGS. 9 (g) and 9 (i), the odd gate masking signal GMS_odd according to the present invention is output in a form pulled forward in comparison with the conventional gate masking signal GMS_odd.

The gate masking signal selection unit 61C selects the gate masking signals GMS_even and GMS_odd having the timing adjusted as described above for each time point and outputs them to the gate signal processing unit 61D.

Accordingly, the gate signal processing unit 61D uses the timing signals GMS_even and GMS_odd, which are inputted from the gate masking signal selecting unit 61C, And adjusts a precharging period or a charging period of the gate signal of the odd and even horizontal lines inputted from the odd-numbered line 61B.

The gate signal GS1 of the excellent horizontal line shown in FIG. 9B shows a gate signal corresponding to the pixel signal of the n-th positive polarity. The gate signal processing unit 61D outputs the gate signal GS1, And uses the radix gate masking signals GMS_even and GMS_odd to reduce the charging duration of the on-duration of the gate signal.

The gate signal GS2 of the odd horizontal line shown in FIG. 9C indicates the gate signal corresponding to the pixel signal of the (n + 1) th negative polarity. The gate signal processing section 61D performs the above- The precharge period is shortened during the on period of the gate signal by using the gated even masking signals GMS_even and GMS_odd.

The gate signal GS3 of the excellent horizontal line shown in FIG. 9D shows a gate signal corresponding to the pixel signal of the (n + 2) -th negative polarity. The gate signal processor 61D adjusts the timing (GMS_even) and (GMS_odd) of the odd-numbered, odd-numbered gate signals to output a reduced charging interval during the on-period of the gate signal.

The gate signal GS4 of the odd horizontal line shown in FIG. 9E shows a gate signal corresponding to the pixel signal of the (n + 3) th positive polarity. The gate signal processing section 61D has the timing The precharge period is shortened during the on period of the gate signal by using the gate masking signals GMS_even and GMS_odd of the odd and even numbers.

In other words, the gate signal processing unit 61D uses polarity-modulated gate masking signals GMS_even and GMS_odd whose timings are adjusted as described above, The charging period is shortened during the on period of the gate signal for the gate signals GS1 and GS3 of the excellent horizontal line with no polarity change, For the gate signals GS2 and GS4 of the gate signal, the precharging interval is shortened during the ON period of the gate signal.

Therefore, a luminance difference is not generated between the odd-numbered horizontal line and the superior-horizontal line, so that a 2-line dim phenomenon does not occur on the screen as shown in FIG.

1 is a block diagram of a conventional liquid crystal display device.

Figures 2a and 2b are pixel polarity arrangements of a version 2 frame with vertical 2 dots.

3 (a) is a waveform diagram of a pixel signal of a version system in which vertical two dots are provided.

3 (b) - (e) are waveform diagrams of gate signals.

3 (f) is a waveform diagram of a gate masking signal.

4 is a waveform chart showing the charge amount of the odd odd-numbered pixel.

5 is a schematic view of a screen in which a horizontal line phenomenon appears due to a luminance difference between adjacent horizontal lines;

6 is a block diagram of a vertical two-dot inversion type liquid crystal display device according to the present invention.

7 (a) - (d) are waveform diagrams of gate signals according to the present invention.

FIGS. 7 (e) and 7 (f) are waveform charts of the odd-numbered gate masking signals applied to the present invention. FIG. 8 is a schematic view of a screen in which a difference in luminance between adjoining horizontal lines is eliminated and no horizontal line phenomenon occurs according to the present invention.

FIG. 9A is a waveform diagram of a pixel signal of a version system in which vertical two dots are provided. FIG.

9 (b) - (e) are waveform diagrams of gate signals.

9 (f) and 9 (g) are waveform diagrams of an even-odd-numbered gate masking signal whose timing is adjusted by the present invention.

9 (h) and 9 (i) are waveform diagrams of the original excellent masking signal of odd number.

DESCRIPTION OF THE REFERENCE SYMBOLS

61: timing controller 61A: data processing section

61B: Timing signal generator 61C: Gate masking signal selector

61D: gate signal processor 62: gate driver

63: data driver 64: liquid crystal panel

Claims (12)

delete delete delete delete delete delete A timing controller for outputting a gate signal and a data control signal; A gate driver for outputting the gate signal output from the timing controller to each gate line of the liquid crystal panel; And And a data driver for generating a pixel signal according to the data control signal output from the timing controller and outputting the pixel signal to each data line of the liquid crystal panel, The timing controller includes: A data processing unit for sampling and outputting digital pixel data (RGB) input from the outside; A timing signal generator for generating first and second gate masking signals having different output timings; A gate masking signal selector for selecting one of the first and second gate masking signals according to a change in the polarity of the pixel signal; And The pre-charging period and the width of the charging period are adjusted in the ON period of the original gate signal according to the gate masking signal selected by the gate masking signal selector, And a gate signal processor for outputting the gate signal to the gate driver in accordance with a horizontal line having no change in polarity of the pixel signal and a horizontal line having a polarity change of the pixel signal. 8. The method of claim 7, Wherein the first gate masking signal is output later than the original first gate masking signal. ≪ RTI ID = 0.0 > 1 < / RTI > 8. The method of claim 7, Wherein the second gate masking signal is output faster than the original second gate masking signal. delete 8. The method of claim 7, The gate signal processing unit, Wherein a width of a charging interval of the gate signal output to a horizontal line having a polarity change of the pixel signal is longer than a width of a charging interval of the gate signal output to a horizontal line having no change in polarity of the pixel signal, Wherein the width of the charging period is controlled during the ON period of the gate signal of the switching transistor. 8. The method of claim 7, The gate signal processing unit, Wherein a width of a precharging period of the gate signal output to a horizontal line having a polarity change of the pixel signal is smaller than a width of a precharging period of the gate signal output to a horizontal line having no change in polarity of the pixel signal And controlling the width of the charging interval in the ON period of the original gate signal to output the adjusted charging signal.

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