KR20090015725A - Buffer circuit of semiconductor memory apparatus - Google Patents

Abstract

A buffer circuit of a semiconductor memory device is provided to avoid an increase of an area by adding an equalization function to a buffer without changing an existing buffer structure. A buffer circuit of a semiconductor memory device includes a buffer unit(100), a delay unit(200), and an equalizer unit(300). The buffer unit outputs an output signal by buffering a first input signal(OUT) and a second input(OUTB). The delay unit delays the output signal during a predetermined time and outputs the delayed signal as an equalization signal. The equalizer unit equalizes the output signal in response to the equalization signal.

Description

Buffer circuit of semiconductor memory device {Buffer Circuit of Semiconductor Memory Apparatus}

The present invention relates to a semiconductor memory device, and more particularly to a buffer circuit.

BACKGROUND OF THE INVENTION In semiconductor memory devices, the frequency of high-speed signals is increasing. Accordingly, high-speed signals are transmitted not only in the internal chip that operates the system but also in the interconnection on the PCB that connects the chip. However, as semiconductor memory devices become faster, phenomena that do not have to be considered at low frequencies occur. For example, the characteristics deteriorate under the influence of conductor loss, dielectric loss, and inter-symbol interference (ISI). Here, the conductor loss refers to the loss caused by the finite conductance of the conductor used in the signal line. The electric loss is a loss caused by a dielectric component existing between the signal line and the metal. Inter-Symbol Interference (ISI) refers to a 40% difference in the size of the signal received at the receiver according to data when there are many frequency losses due to the length of the channel. The distortion level of the received signal varies depending on the transmitted data due to the effect of frequency loss. The ISI is a major problem in the current trend of signal transmission systems that transmit high-speed signals in serial. This problem occurs because a channel has characteristics of a low pass filter in the frequency domain. As a result, the loss is increased as the transmission of the high-speed signal. Therefore, the loss generated in the transmission of the high speed signal can be compensated by incorporating the characteristics of the high pass filter. The method of incorporating the characteristics of the high pass filter is to apply equalization.

Here, the low pass filter refers to detecting and passing low frequency components, and the high pass filter cuts low frequency components and detects and passes high frequency components.

In addition, the equalization (Equalization) means to adjust the high frequency and low frequency. In general, the characteristics of a channel appear like a low pass filter. The transmission of a high-speed signal causes a greater channel loss. Therefore, this is compensated by connecting a device that increases high frequency or attenuates low frequency to serve as a high pass filter.

In order to perform equalization on the conventional input buffer, a capacitor was used. However, there is a problem that a large area is required to apply a capacitor to the on-chip.

The buffer circuit of the semiconductor memory device according to the present invention has an object to reduce an increase in the area caused by adding an equalization function.

A buffer circuit of a semiconductor memory device according to the present invention includes a buffer unit for outputting an output signal by buffering a first input signal and a second input signal; A delay unit delaying the output signal by a predetermined time and outputting the equalized signal; And an equalizer unit equalizing the output signal in response to the equalized signal.

The buffer circuit of the semiconductor memory device according to the present invention has an effect of minimizing an area by adding an equalization function without changing the existing buffer structure at all.

1 is a block diagram of a buffer circuit of a semiconductor memory device according to the present invention.

Conventionally, a capacitor was provided to perform equalization, but in the present invention, a MOS transistor is provided so that the buffer itself can perform the equalization function.

Referring to FIG. 1, a buffer circuit of a semiconductor memory device according to an exemplary embodiment of the present invention may include a buffer unit configured to output first and second output signals OUT and OUTB by comparing a difference between potential levels of data input signals IN and INB. A delay unit 200 for delaying the first and second output signals OUT and OUTB for a predetermined time and outputting the first and second equalized signals EQ and EQB, and the first and second output signals. And an equalizer 300 for equalizing the first and second output signals OUT and OUTB in response to the two equalizing signals EQ and EQB. Here, the first and second output signals OUT and OUTB are differential signals having phases opposite to each other. The first and second equalized signals EQ and EQB are also differential signals having opposite phases.

2 is a circuit diagram of a buffer circuit of a semiconductor memory device according to the present invention.

2, a buffer circuit of a semiconductor memory device includes a buffer unit 100, a delay unit 200, and an equalizer unit 300.

The buffer unit 100 may include first and second NMOS transistors N1 and N2 for inputting differential signals IN and INB, a third NMOS transistor N3 for activating the buffer unit 100, and First and second resistors R1 and R2 are included. The first NMOS transistor N1 includes a gate receiving the data input signal IN, a drain connected to the first node S1, and a source connected to the third node S3. The second NMOS transistor N2 includes a gate that receives the inverted data output signal OUTB, a drain connected to the second node S2, and a source connected to the third node S3. The third NMOS transistor N3 includes a gate configured to receive a bias voltage Bias, a drain connected to the third node S3, and a source connected to the ground voltage VSS terminal. The first resistor R1 is connected between the power supply voltage VDD terminal and the first node S1, and the second resistor R2 is connected between the power supply voltage VDD terminal and the second node S2. .

The delay unit 200 receives the second output signal OUTB and receives a first delay unit 210 and a first output signal OUT for delaying a predetermined time and outputting a second equalized signal EQB. The second delayer 220 outputs a first equalized signal EQ by delaying a predetermined time.

The equalizer 300 includes fourth and fifth NMOS transistors N4 and N5 for equalization. The fourth NMOS transistor N4 includes a gate receiving the second equalization signal EQB, a drain connected to the drain of the first NMOS transistor N1, and a source connected to the third node S3. The fifth NMOS transistor N5 includes a gate receiving the first equalization signal EQ, a drain connected to the drain of the second NMOS transistor N2, and a source connected to the third node S3. .

The buffer circuit of the semiconductor memory device according to the present invention is a form in which the fourth and fifth NMOS transistors N4 and N5, which are steering MOS transistors, are added to a general buffer circuit. The fourth and fifth NMOS transistors N4 and N5 are connected in parallel with the first or second NMOS transistors N1 and N2, respectively, and adjust an offset. Gates of the fourth and fifth NMOS transistors N4 and N5 are fed back with the fed back first and second equalized signals EQ and EQB in opposite phases. That is, when the data input signal IN is input to the first NMOS transistor N1, the second equalization signal EQB is input to the fourth NMOS transistor N4 paired with the data input signal IN. When the inverted data input signal INB is input to the second NMOS transistor N2, the first equalization signal EQ is input to the fifth NMOS transistor N5 paired with the inverted data input signal INB.

The buffer circuit turns on the first NMOS transistor N1 and turns on the second NMOS transistor N2 when the data input signal IN maintains a low level and transitions to a high level. Turn it off. At this time, the first node S1 has a low potential level, and the second output signal OUTB outputs an output signal OUTB having a low level. The second output signal OUTB of the 'low' level is delayed by a predetermined time via the delay unit 200 and output as the second equalized signal EQB. The second equalization signal EQB of the 'low' level turns off the fourth NMOS transistor N4.

Meanwhile, the second node S2 has a high potential level and outputs an output signal OUT having a 'high' level. The output signal OUT of the 'high' level is delayed by a predetermined time via the delay unit 200 and output as the equalized signal EQ of the 'high' level. The equalization signal EQ of the 'high' level turns on the fifth NMOS transistor N5. At this time, the first NMOS transistor N1 and the fifth NMOS transistor N5 are simultaneously turned on, thereby accelerating current discharge.

Therefore, the first NMOS transistor N1 is turned on, and after a predetermined time, the fifth NMOS transistor N5 is turned on to simultaneously discharge current, thereby increasing the response speed of the buffer circuit. In addition, after the second NMOS transistor N2 is turned on and a predetermined time has passed, the fourth NMOS transistor N4 is turned on to simultaneously discharge current, thereby increasing the response speed of the buffer circuit.

The buffer circuit according to the present invention does not necessarily need to operate the fourth and fifth NMOS transistors N4 and N5 in pairs, and may be selectively applied to either side. In addition, the reference voltage may be applied by replacing the inverted data input signal INB.

3 is a circuit diagram of a delay unit shown in FIG. 2.

Referring to FIG. 3, the delay unit 200 includes a first delay unit 210 and a second delay unit 220. Since the first delayer 210 and the second delayer 220 have the same configuration, the first delayer 120 will be described, for example.

The first retarder 220 includes an even number of inverters IV1: IVn connected in series with the second output signal OUTB as an input. The first delayer 210 receives the second output signal OUTB and delays the predetermined time for a predetermined time and outputs the second equalized signal EQB.

Here, the delay unit 200 may use any delay circuit such as an inverter chain and a differential amplifier chain. That is, if the delay time can be adjusted using the delay circuit as described above, the performance of equalization can be maximized.

4 illustrates an output waveform of a buffer circuit of a semiconductor memory device according to the present invention.

Referring to FIG. 4, if the voltage of the data input signal IN is higher than the inverted data input signal INB, which is a differential signal, the input signal voltage IN_V is the power supply voltage VDD. It becomes a level. Here, the input signal voltage IN_V refers to the voltage of the data input signal IN minus the voltage of the inverted data input signal INB. In this case, the first output signal OUT has a high potential level, and the second output signal OUTB, which is a differential signal, has a low potential level, so that the second output whose voltage of the first output signal OUT is a differential signal. It becomes higher than the voltage of the signal OUTB. Therefore, the output signal voltage OUT_V rises to the power supply voltage VDD level. Here, the output signal voltage OUT_V refers to a voltage obtained by subtracting the voltage of the second output signal OUTB, which is a differential signal, from the voltage of the first output signal OUT. The first output signal OUT is output as the first equalized signal EQ having a predetermined value delayed through the delay unit 200. The first equalizing signal EQ turns on the fifth NMOS transistor N5 to lower the potential level of the first output signal OUT. Therefore, the output signal voltage OUT_V, which has maintained the power supply voltage VDD level, becomes lower by a predetermined value.

On the contrary, when the voltage of the inverted data input signal INB is higher than the voltage of the data input signal IN, the input signal voltage IN_V becomes the ground voltage VSS level. The potential level of the second output signal OUTB, which is a differential signal, is high, and the potential level of the first output signal OUT is low, so that the voltage of the second output signal OUTB, which is a differential signal, is the first output signal. It becomes higher than the voltage of (OUT). Therefore, the output signal voltage OUT_V transitions to the ground voltage VSS level. The second output signal OUTB, which is a differential signal, is output as the second equalized signal EQB delayed by a predetermined time via the delay unit 200. The second equalizing signal EQB turns on the fourth NMOS transistor N4, and the potential level of the second output signal OUTB, which is a differential signal, becomes low. Therefore, the output signal voltage OUT_L rises a predetermined value above the ground voltage VSS level. As the level states of the fourth and fifth NMOS transistors N4 and N5 are changed according to the delayed first and second equalization signals EQ and EQB, data transfer is accelerated to equalize. This is to amplify a relatively high frequency signal while reducing the amplitude of the data input signals IN and INB including a lot of low frequency signals, and thus have characteristics of a high pass filter.

The buffer circuit of the semiconductor memory device according to the present invention adds fourth and fifth NMOS transistors N4 and N5, which are steering MOS transistors for adjusting an offset, in order to combine the characteristics of a high pass filter. It was equipped with. As the buffer circuit according to the present invention performs equalization without changing the structure of the existing buffer circuit, the extent of area increase becomes smaller than that of the existing structure.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a buffer circuit of a semiconductor memory device according to the present invention;

2 is a circuit diagram of a buffer circuit of a semiconductor memory device according to the present invention;

3 is a circuit diagram of a delay unit shown in FIG. 2, and

4 is a timing diagram of a buffer circuit of a semiconductor memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: buffer unit 200: delay unit

300: equalizer part

Claims (4)

A buffer unit for outputting an output signal by buffering the first input signal and the second input signal; A delay unit for delaying the output signal by a predetermined time and outputting the equalized signal;  And an equalizer unit for equalizing the output signal in response to the equalized signal. The method of claim 1, The buffer unit, A first NMOS transistor having a gate input to the first input signal and connected between a first output node and a first common node, A second NMOS transistor having a gate input to the second input signal and connected between a second output node and the first common node, and A buffer circuit of the semiconductor memory device, wherein the gate voltage is input to the bias voltage, and the third NMOS transistor is connected between the first common node and the ground voltage terminal. The method of claim 1, The delay unit, A first delayer for receiving a first output signal and delaying the predetermined time for outputting a first equalized signal; and And a second delayer receiving the second output signal and delaying the predetermined time for outputting a second equalized signal. The method of claim 2, The equalizer part, A fourth NMOS transistor receiving the first equalized signal and connected in parallel with the first NMOS transistor; And a fifth NMOS transistor configured to receive the second equalized signal and be connected in parallel with the second NMOS transistor.

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