KR20080064261A - Pre-emphasis output circuit with adjustable tapped delay line - Google Patents

Abstract

A pre-emphasis output circuit is provided to perform a pre-emphasis operation without inputting an additional clock signal and recovering a clock of data because a plurality of delayers does not have the same delay time. In a pre-emphasis output circuit, a main driver(11) receives and amplifies a data signal, and outputs the data signal at an output terminal. A shared load(14) is connected to the output terminal of the main driver. A delay line(13) includes a plurality of delayers which are connected in series and control delay time according to a control voltage respectively, receives the data signals and outputs the delay signals to delay the data signals as much as the delay time, to each delayer. A plurality of tap drivers(121,122,123,124) amplify the delay signals and includes the pre-emphasis output circuit connected to add the delay signals at an output terminal of the main driver.

Description

PRE-EMPHASIS OUTPUT CIRCUIT WITH ADJUSTABLE TAPPED DELAY LINE}

1 is a block diagram illustrating a pre-emphasis output circuit having a tap delay line according to an embodiment of the present invention.

2 is a circuit diagram illustrating a voltage controlled delay device of a pre-emphasis output circuit according to an embodiment of the present invention.

3 is a graph illustrating a change in delay time according to a control voltage of the voltage controlled delay device of FIG. 2.

FIG. 4 is a graph of measuring a pre-emphasis output signal of the pre-emphasis output circuit of FIG. 1 by adjusting a control voltage.

FIG. 5 is a circuit diagram illustrating a buffer of the pre-emphasis output circuit of FIG. 1.

6 is a flowchart illustrating a preemphasis output method according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11: main driver

121, 122, 123, 124: Tab Driver

13: delay line

131, 132, 133, 134: voltage controlled delay

14: shared load

151, 152, 153, 154, 155: buffer

The present invention relates to an output circuit, and more particularly to a pre-emphasis output circuit.

When the transmitting end transmits a digital signal through a lossy channel, the receiving end receives the transmitted signal in a distorted state according to the frequency characteristics of the channel. In general, since a lossy channel has more loss in the high frequency region, the high frequency component of the signal transmitted through the channel is attenuated more than the low frequency component. The high frequency components of a digital signal mainly correspond to the part where the voltage level of the signal changes rapidly, that is, the rising edge or the falling edge. Therefore, the signal passing through the lost channel will have a distorted waveform than the original waveform, and the time of arrival of the transmitted signal for each frequency may vary, resulting in a lot of jitter and overall reduction in timing margin. . On the other hand, inter-symbol interference (ISI) is also a problem. Loss in the channel results in a different time the signal arrives by frequency component, which can lead to incorrect transmission of overlapping data over long channels or high-speed communications.

To solve these problems, the equalization technique is used to compensate for the distortion during the passage of the channel by highlighting or suppressing the signal by frequency band, and finally adjusting the waveform of the signal so that the receiver can receive the original signal. ), And one of the representative techniques of equalization is the pre-emphasis technique. The pre-emphasis technique is a method of reinforcing a high frequency band of a signal by a predetermined amount before transmitting a signal at a transmitter, and transmitting the enhanced signal. As explained above, the high-frequency components of the signal appear mainly at the edges. The preemphasis technique is to increase the magnitude of the signal at the edges as much as the channel attenuates.

Conventional output buffers with tapped delay lines use delay lines with one or more taps to compensate for signal losses, which have the same delay time. As a result, signal loss can be properly compensated for only during a predetermined period. However, in order for the taps to have the same delay time, the taps must be synchronized to one clock signal. That is, in addition to the data signal to the output circuit, the clock signal must be supplied separately or the clock signal must be recovered from the data signal. Therefore, it is necessary to have a transmission path for the clock signal or to have a clock and data recovery circuit. In both cases, the area of the circuit or the power consumption are large.

In addition, since the delay time is fixed and the degree of pre-emphasis cannot be adjusted, the inter-data interference phenomenon cannot be effectively improved.

An object of the present invention is to provide an output circuit having a tap delay line that can adjust the delay time.

Another object of the present invention is to provide a preemphasis method using a tap delay line that can adjust a delay time.

The pre-emphasis output circuit according to an embodiment of the present invention is provided with a main driver for receiving and amplifying a data signal and outputting it at an output terminal, a shared load connected to an output terminal of the main driver, a delay line, and the delay signals, respectively. And a plurality of tap drivers coupled to amplify and add delayed output signals at the output terminal of the main driver. The delay line includes a plurality of serially connected delayers each of which can adjust a delay time according to a control voltage, and receive delay signals for delaying the data signal by the delay time for each of the delayers. Output

In some embodiments, the main driver and the tap drivers are current amplifiers, and the sum of the output currents of the main driver and the tap drivers flows through the shared load to generate a pre-emphasized output signal.

According to an embodiment, the electronic device may further include a buffer configured to adjust a level of a signal according to a predetermined logic standard between an output of the delayers and an input of the tap driver.

According to an embodiment, the control voltage may be applied independently for each delay, or may be applied equally to all the delays.

According to an embodiment, the retarder may be a current mode logic circuit having an active load whose load magnitude is adjusted by the control voltage. In this case, the active load may be implemented as a PMOS transistor.

The pre-emphasis output method according to another embodiment of the present invention includes amplifying a data signal to generate a main output signal, and using the plurality of serially connected delayers each of which can adjust a delay time according to a control voltage. Outputting the delayed signals respectively delaying the data signal by the delay time for each period, amplifying the delayed signals to generate delayed output signals, and adding the main output signal and the delayed output signals to the pre-em; Generating a persis output signal.

In some embodiments, the main output signal may be current amplified by the data signal, and the delay output signals may be current amplified by the delay signals, respectively.

According to an embodiment, the method may further include adjusting the level of the data signal or the delay signals according to a predetermined logic standard.

According to an embodiment, the control voltage may be applied independently for each delay, or may be applied equally to all the delays.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram illustrating a pre-emphasis output circuit having a tap delay line according to an embodiment of the present invention. Referring to FIG. 1, the pre-emphasis output circuit 10 includes a main driver 11, a plurality of tap drivers 121, 122, 123, and 124, a delay line 13, a shared load 14, and a plurality of. Buffers 151, 152, 153, 154, 155. In FIG. 1, all signals are illustrated based on a differential signal, but may be applied to a single-ended signal as it is.

The operation of the pre-emphasis output circuit 10 will be described briefly. The data signals DATA and DATAB to be output are applied to the main driver 11 and the delay line 13, respectively. The data signals DATA and DATAB applied to the main driver 11 are amplified at a predetermined amplification rate. The delay line 13 includes a plurality of voltage controlled delayers 131, 132, 133, and 134 connected in series. The delay line 13 includes a time delay, ie, a delay, through the delayers 131, 132, 133, and 134. The time is determined according to the control voltages Vc1, Vc2, Vc3 and Vc4. The data signals DATA and DATAB are delayed by a predetermined delay while passing through the respective delayers 131, 132, 133, and 134, and the respective delayers 131, 132, 133, and 134 are the preceding delayers. Receives the delayed signal output from the output delay signals further delayed by each delay time. The tap drivers 121, 122, 123, and 124 amplify the delay signals at predetermined amplification rates, respectively. In this case, the amplification ratios of the tap drivers 121, 122, 123, and 124 may be the same. The signals output from the tap drivers 121, 122, 123, and 124 are summed with the output of the main driver 11 at the summing nodes NA and NB, and the preemphasis output signal OUT by the shared load 14. , OUTB) is generated.

The components of the pre-emphasis output circuit 10 will be described in detail. First, the main driver 11 amplifies the data signals DATA and DATAB in accordance with a predetermined output interface standard. The main driver 11 may be a simple differential current amplifier.

The delay line 13 includes a plurality of serially connected delayers 131, 132, 133, and 134. Each of the delayers 131, 132, 133, and 134 receives the control voltages Vc1, Vc2, Vc3, and Vc4 as voltage control delayers, and the control voltages Vc1, Vc2, Vc3, and Vc4. The delay times of the respective delayers 131, 132, 133, and 134 are respectively determined. The control voltages Vc1, Vc2, Vc3, and Vc4 may all be the same or may be provided differently. The outputs of the respective delayers 131, 132, 133, 134 are provided to the tap drivers 121, 122, 123, 124, respectively. The total delay time of the delay line 13 is closely related to the preemphasis period of the preemphasis output signals OUT and OUTB. Therefore, by controlling the control voltages Vc1, Vc2, Vc3, and Vc4, it is possible to control how much the data signals DATA and DATAB will be pre-emphasized.

The tap drivers 121, 122, 123, and 124 receive the outputs of the respective delayers 131, 132, 133, and 134 and amplify them at a predetermined amplification rate. The tap drivers 121, 122, 123, 124 may be differential current amplifiers. The tap drivers 121, 122, 123, and 124 may be variable biased to adjust amplification rate. The output currents of the tap drivers 121, 122, 123, and 124 are summed with the output current of the main driver 11 at the summation nodes NA and NB. Since the tap drivers 121, 122, 123, and 124 share the shared load 14 with the main driver 11 at the summing nodes NA and NB, the output signal pre-emphasized according to the sum of the respective output currents is a voltage. It appears at the summing node (NA, NB) in the form of. When the data signals DATA and DATAB are logic high, the pre-emphasis output signals OUT and OUTB are lowered by the outputs of the tap drivers 121, 122, 123, and 124 at the output of the main driver 11 to rise. When the data signals DATA and DATAB are logic low, the pre-emphasis output signals OUT and OUTB are outputted from the output of the main driver 11 of the tap drivers 121, 122, 123, and 124. Incremented by the outputs, the falling edge portion is highlighted.

The pre-emphasis output circuit 10 adds a buffer 151 in front of the main driver 11 or between each output of the delay line 13 and the tap drivers 121, 122, 123, and 124, respectively. It may further include a buffer (152, 153, 154, 155). The buffers 151 to 155 may be adjusted so that data signals applied to the main driver 11 or delay signals applied to the tap drivers 121, 122, 123, and 124 do not deviate from a predetermined output interface standard. The operation of the 11 and the tap drivers 121, 122, 123, and 124 can be guaranteed.

2 is a circuit diagram illustrating a voltage controlled delay device of a pre-emphasis output circuit according to an embodiment of the present invention.

Referring to FIG. 2, the voltage controlled delay unit 131 is a differential pair in the form of current mode logic (CML) having active loads 1311 and 1312. The active loads 1311 and 1312 are implemented with PMOS transistors, and the sizes of the active loads 1311 and 1312 are adjusted according to the control voltage Vc. When the control voltage Vc is low, the active loads 1311 and 1312 have a small size, so that a large current can flow in the differential pair of the retarder 131, so that the voltages DELAY and DELAYB of the output terminal are the voltage IN of the input terminal. , INB) is immediately followed and the delay time is short. On the contrary, when the control voltage Vc is high, the active loads 1311 and 1312 have a large size and a current that can flow through the differential pair of the retarder 131 is small, so that the voltages of the output terminals DELAY and DELAYB are the voltages of the input terminals. (IN, INB) cannot be immediately followed, resulting in a large delay time.

3 is a graph illustrating a change in delay time according to a control voltage of the voltage controlled delay device of FIG. 2. Referring to FIG. 3, it can be seen that the delay time is short when the control voltage applied to the PMOS active load is low, but the delay time is longer as the control voltage is increased. Therefore, the voltage control delay of FIG. 2 can adjust the control voltage even with a simple structure, and thus, when used in the preemphasis output circuit of FIG. 1, the delay time for the preemphasis can be effectively adjusted.

FIG. 4 is a graph of measuring a pre-emphasis output signal of the pre-emphasis output circuit of FIG. 1 by adjusting a control voltage. Referring to FIG. 4, when the pre-emphasis output signal is at a logic low, the pre-emphasis output signal represents 1.4 V, which is lower than 1.6 V, which is a non-pre-emphasized voltage level on the falling edge. When logic high, the preemphasis output signal exhibits 2.2V, which is higher than the non-preemphasized voltage level of 2V on the rising edge, with longer preemphasis intervals as the control voltage increases.

FIG. 5 is a circuit diagram illustrating a buffer of the pre-emphasis output circuit of FIG. 1. Referring to FIG. 5, a signal having the same logic level as the input signal is output by inverting the input signal twice.

In the pre-emphasis output circuit of the present invention described above, the retarder does not necessarily have to have the structure of FIG. 2 and can be simply applied to the pre-emphasis output circuit as long as it can vary the delay time with a control voltage. . Similarly, the buffer does not necessarily have the structure of FIG. 5, and may be applied to the preemphasis output circuit as long as the input signal is a buffer that can be adjusted to conform to a predetermined logic standard.

6 is a flowchart illustrating a preemphasis output method according to an embodiment of the present invention. Referring to FIG. 6, the pre-emphasis output method first includes amplifying a data signal according to a predetermined output interface standard to generate a main output signal (S61). The data signal is applied to a plurality of series connected delayers whose delay time is adjusted according to a control voltage, and the plurality of delayers generate a plurality of delay signals for delaying the data signal by a delay time (S62). The plurality of delay signals are each amplified at a predetermined amplification rate and generated as a delayed output signal (S63). The delayed output signals are summed with the main output signal to generate a final pre-emphasized output signal (S64).

In some embodiments, the main output signal and the delayed output signals may be current amplified data signals.

The pre-emphasis output circuit and the pre-emphasis output method according to an embodiment of the present invention do not have to have the same delay time because the plurality of delays do not all have to receive separate clock signals or recover clocks from data. Pre-emphasis can be performed. In addition, the delay time of the delay unit can be adjusted by the control voltage, and the degree of pre-emphasis by the adjusted delay time can be adjusted to effectively cope with the inter-data signal interference (ISI).

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (12)

A main driver for receiving and amplifying a data signal and outputting the same at an output terminal; A shared load connected to the output terminal of the main driver; A delay line which includes a plurality of serially connected delayers each of which can adjust a delay time according to a control voltage, and outputs, for each of the delayers, delay signals that receive the data signal and delay the data signal by the delay time. ; And And a plurality of tap drivers coupled to receive and amplify the delay signals, respectively, and to add delay output signals at the output terminal of the main driver. 2. The pre-emulator of claim 1, wherein the main driver and the tap drivers are current amplifiers, and a summated output current of the main driver and the tap drivers flows through the shared load to generate a pre-emphasized output signal. Persis output circuit. The preemphasis output circuit according to claim 1, further comprising a buffer for adjusting a level of a signal according to a predetermined logic standard between the outputs of the delayers and the input of the tap driver. The preemphasis output circuit of claim 1, wherein the control voltage is independently applied to each delay unit. 2. The pre-emphasis output circuit of claim 1 wherein the control voltage is equally applied to all retarders. 2. The preemphasis output circuit of claim 1 wherein the retarder is a current mode logic circuit having an active load whose load magnitude is adjusted by the control voltage. The preemphasis output circuit of claim 6, wherein the active load is implemented by a PMOS transistor. Amplifying the data signal to generate a main output signal; Outputting delay signals each of which delays the data signal by the delay time for each of the delayers, using a plurality of series-connected delayers each of which can adjust a delay time according to a control voltage; Amplifying each of the delay signals to produce delayed output signals; And Generating a preemphasis output signal by summing the main output signal and the delayed output signals. The method of claim 8, wherein the main output signal is current amplified by the data signal, and the delay output signals are current amplified by the delay signals, respectively. 9. The method of claim 8, further comprising adjusting the level of the data signal or the delay signals to a predetermined logic standard. The method of claim 8, wherein the control voltage is independently applied to each delay unit. 9. The method of claim 8 wherein the control voltage is equally applied to all retarders.

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