KR20080084389A - Liquid crystal display and driving method thereof - Google Patents

Abstract

An LCD(Liquid Crystal Display) device is provided to reduce size and the number of output pins of a control PCBs(Printed Circuit Board) by implementing an output port of a timing controller as a single output port. An LCD(Liquid Crystal Display) panel(30) includes first and second data line groups, plural gate lines across the first and second data line groups, and plural liquid crystal cells. First and second data circuit groups include data ICs(Integrated Circuit) for supplying data to the first and second data line groups. First and second source PCBs(Printed Circuit Board)(41A,41B) are connected to the first and second data line groups. A timing controller(31) outputs timing control signals for controlling the first and second data line groups, and data through a single output port. A control PCB(40) includes the timing controller. Connection wires are used for connecting electrically the single output port to the first and second source PCBs.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 shows a liquid crystal display device having a single source PCB.

3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a diagram showing in detail the connection structure of the timing controller and data ICs shown in FIG. 3; FIG.

5 is a block diagram illustrating in detail a data processor of the timing controller illustrated in FIGS. 3 and 4.

6 and 7 are waveform diagrams showing an output example of the data modulator shown in FIG.

8 is a diagram illustrating a signal transmission path between the timing controller and data ICs shown in FIG. 4;

9 is a block diagram showing in detail the data IC shown in FIG.

FIG. 10 is a circuit diagram showing in detail the DAC shown in FIG.

11 and 12 are views illustrating an example in which a source PCB is separated and an output port of a timing controller is configured as a double output port.

<Description of Symbols for Main Parts of Drawings>

30 liquid crystal display panel 31 timing controller

32: data driving circuit 33: gate driving circuit

40: Control PCB 41A, 41B, 131A, 131B: Source PCB

42: source COF 43A, 43B, 113A, 113B: FFC

44, 114A, 114B: Connection wiring 51, 121: 2-port extension

52, 122: data modulator 53: single output port

61: shift register 62: data recovery unit

63, 64: Latch 65: DAC

66: charge share circuit 67: output circuit

71: P-decoder 72: N-decoder

73: multiplexer 120: left and right data separation unit

141, 142: Double output port

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for simplifying a control printed circuit board (hereinafter referred to as "PCB").

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in a liquid crystal cell Clc, “DL” denotes a data line to which a data voltage is supplied, and “GL”. Denotes a gate line to which a scan voltage is supplied.

In recent years, as a liquid crystal display device has a large screen, a development of not only a small but also a medium-large model is in progress. As shown in FIG. 2, the liquid crystal display includes a control PCB 20, a source PCB 22, a cable 21 electrically connecting the source PCB 22 and the control PCB 20, a source PCB 22, and a liquid crystal display. A plurality of source chip on film (COF) connected to panel 25 is provided.

The source COF 24 is electrically connected to the data PCBs of the source PCB 22 and the liquid crystal display panel 25. A data integrated circuit (hereinafter referred to as "IC") 23 is mounted on this source COF 24. The source COF 24 may be replaced with a source Tape Carrier Package (TCP).

Signal wirings for transmitting digital video data and timing control signals from the control PCB 20 are formed in the source PCB 23.

The control circuit 20 includes a control circuit and a data transmission circuit. The control PCB 20 supplies data to the data IC of the source PCB 22 and timing control signals for controlling the operation of the data IC to the source PCB 22 through the cable 21.

In the liquid crystal display device of FIG. 2, when the liquid crystal display panel 25 becomes large, the data lines and the source TCPs 24 increase accordingly, and as a result, the source PCB 22 also becomes large. In this case, the alignment of the source PCB 22 and the source TCP 24 becomes difficult. As the source PCB 22 grows larger, automated mounting devices, such as conventional Surface Mount Technology (SMT) equipment, are designed based on a relatively small size of the source PCB 22 and thus cannot handle the large source PCB 22. As the control PCB 20 increases in size, the number of circuit elements such as a memory increases and the number of output pins increases.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which divides the source PCB and reduces the size of the control PCB and the number of output pins.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a first and a second data line group each including a plurality of data lines, and a plurality of gate lines intersecting the first and second data line groups. A liquid crystal display panel including a plurality of liquid crystal cells arranged in a matrix form; A first data circuit group including data ICs for supplying data to the first data line group; A first source PCB to which the first data circuit group is connected; A second data circuit group including data ICs for supplying data to the first data line group; A second source PCB to which the second data circuit group is connected; A timing controller for controlling the first and second data circuit groups and a timing controller configured to output the data through a single output port; A control PCB on which the timing controller is mounted; And connection wirings for electrically connecting the single output port to the first and second source PCBs.

Each of the first and second data circuit groups includes any one of a chip on film (COF) and a tape carrier package (TCP) on which the data IC is mounted.

The connection wires may include a first cable for electrically connecting the first source PCB and the control PCB; A second cable for electrically connecting the second source PCB and the control PCB; And two port connection wires formed on the control PCB to electrically connect the single output port to the first and second cables.

The timing controller includes: a two-port expansion unit for dividing digital video data input at an input frequency into odd pixel data and even pixel data, and outputting the data at one-half frequency of the input frequency; And a data modulator for modulating data from the two-port expansion unit to reduce a swing width of data output through the single output port and output the data at a frequency twice as high as the input frequency.

The data modulator modulates the data using any one of a mini low-voltage differential signaling (LVDS) scheme and a reduced swing differential signaling (RSDS) scheme.

The control PCB includes a memory for supplying waveform option information of the timing control signal to the timing controller; And a voltage source for generating a driving voltage of the liquid crystal display panel.

In a method of driving a liquid crystal display according to an exemplary embodiment of the present invention, a first data circuit group including data ICs for supplying data to a first data line group is connected to a first source PCB, and data is transmitted to the first data line group. Connecting a second data circuit group including data ICs to supply a second source PCB; Mounting a timing controller having a single output port on a control PCB; And electrically connecting the single output port to the first and second source PCBs to supply timing control signals and data from the single output port to the first and second source PCBs.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 12.

Referring to FIG. 3, the liquid crystal display according to the exemplary embodiment includes a liquid crystal display panel 30, a timing controller 31, a data driving circuit 32, and a gate driving circuit 33.

In the liquid crystal display panel 30, liquid crystal molecules are formed between two glass substrates. The liquid crystal display panel 30 includes m × n liquid crystal cells Clc in which m data lines D1 to Dm and n gate lines G1 to Gn are arranged in a matrix by a cross structure. Include.

The lower glass substrate of the liquid crystal display panel 30 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes 1 of a liquid crystal cell Clc connected to a TFT, and The storage capacitor Cst and the like are formed. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 30. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 30, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The timing controller 31 receives timing signals such as a vertical / horizontal synchronization signal, a data enable signal, a clock signal, and generates control signals for controlling the operation timing of the data driver circuit 32 and the gate driver circuit 33. . These control signals include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source sampling clock (SSC). And a source output enable signal SOE and a polarity control signal POL. The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit and is a timing control signal for sequentially shifting the gate start pulse GSP, and is generated with a pulse width corresponding to the ON period of the TFT. The gate output signal GOE indicates the output of the gate driving circuit 33. The source sampling clock SSC instructs a latch operation of data in the data driving circuit 32 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 32. The polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 30. Hereinafter, detailed descriptions of the gate timing control signal for controlling the gate driving circuit 33, that is, the gate start pulse GSP, the gate shift clock signal GSC, and the gate output enable signal GOE will be omitted. do. In addition, the timing controller 31 separates the digital video data into odd pixel data RGBodd and even pixel data RGBeven and supplies the data to the data driving circuit 32. In order to reduce the swing width of the EMI and the data voltage on the data transmission path, the timing controller 31 modulates the data by mini-low-voltage differential signaling (LVDS) or reduced swing differential signaling (RSDS). 32).

The data driving circuit 32 latches the digital video data RGBodd and RGBeven under the control of the timing controller 31. The data driving circuit 32 converts the digital video data into analog positive / negative gamma compensation voltages according to the polarity control signals POL / FGDPOL to generate positive / negative analog data voltages and converts the data voltages into data. Supply to lines D1 to Dm.

The gate driving circuit 33 includes a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. It consists of a plurality of gate drive integrated circuits. The gate driving circuit 33 sequentially outputs scan pulses.

FIG. 4 is a view showing an assembled state of the liquid crystal display panel 30, the data driving circuit 32, and the timing controller 31 shown in FIG.

Referring to FIG. 4, the data driver circuit 32 includes a plurality of data ICs 32a. Multiple data ICs 32a are each mounted in a source COF 42. Source COFs 42 are divided into two divided first and second source PCBs 41A, 41B. The input terminals of the source COFs 42 are electrically connected to the output terminals of the first and second source PCBs 41A and 41B, and the output terminals of the first and second source COFs 42 are ACF ( It is electrically connected to data pads formed on the lower glass substrate of the liquid crystal display panel 30 through an anisotropic conductive film. The first and second source PCBs 41A and 41B have bus wirings for transmitting digital video data RGBodd and RGBeven, bus wirings for transmitting data timing control signals, and bus wirings for driving voltages. do.

Input terminals of the first source PCBs 41A are connected to two port connecting wires 44 formed on the control PCB 40 via a first flexible flat cable (FFC) 43A. The input terminals of the second source PCBs 41B are connected to the two port connecting wires 44 formed on the control PCB 40 via the second flexible flat cable (FFC) 43B.

The control PCB 40 has a circuit such as a DC-DC converter for generating a driving voltage of the timing controller 31, the EEPROM 31a, and the liquid crystal display panel 30, and a two-port connection wiring. Field 44 is formed. The driving voltages generated by the DC-DC converter are gate high voltage (Vgh), gate low voltage (Vgl), common voltage (Vcom), high potential supply voltage (Vdd), low potential supply voltage (Vss), and high potential supply voltage. A plurality of gamma reference voltages, etc., which are divided between Vdd and the low potential power supply voltage Vss. The gamma reference voltages are divided in the data ICs 32a by the number of gray levels that can be represented by the number of bits of the digital video data RGBodd and RGBeven, and subdivided into analog gamma compensation voltages corresponding to each gray level. The gate high voltage Vgh and the gate low voltage Vgl are swing voltages of the scan pulse. The EEPROM 31a stores waveform option information for timing control signals generated from the timing controller 31 for each of a plurality of modes, and supplies waveform information to the timing controller 31 in a corresponding mode according to a command from a user. The timing controller 31 generates timing control signals in different forms in each mode according to the waveform option information from the EEPROM 31a.

The two port connecting wires 44 formed on the control PCB 40 are patterned in a “Y” shape so that the single output port 53 of the timing controller 31 shown in FIG. 5 is connected to the first and second FFCs 43A. , 43B). The digital video data (RGBodd, RGBeven) and timing control signals generated from the timing controller 40 and the driving voltages generated from the DC-DC converter through the two port connection wires 44 are first and second. It is supplied to FFC 43A, 43B.

5 is a diagram illustrating a data processing portion in the timing controller 31.

Referring to FIG. 5, the timing controller 31 includes a two port extension unit 51 and a data modulation unit 52.

The two-port expansion unit 51 separates the digital video data RGB inputted from the main board of the system at a predetermined frequency f into the odd pixel data RGBodd and the even pixel data RGBeven, and the data RGBodd. , RGBeven is supplied to the data modulator 52 at 1/2 frequency (1/2 f). The swing widths of the data RGBodd and RGBeven output from the two-port expansion unit 51 are relatively high, such as 3.3 V, which is a TTL (transistor-to-transistor) level.

The data modulator 52 modulates the data using the mini LVDS method to reduce the swing widths of the data RGBodd and RGBeven from the two-port expansion unit 51 to about 300 mV to 600 mV and to reduce the frequency of the data according to the mini LVDS clock. Increase to 2x. The signals output from the data modulator 52 include three pairs of RGB pixel data RGBodd, three pairs of even pixel data RGBeven, and one pair of mini clocks Mini CLK. Each pair includes a positive signal and a negative signal. Meanwhile, the data modulator 52 may modulate data by the RSDS method.

6 and 7 illustrate an example of data output from the data modulator 52, which is an example of data modulated by the mini LVDS method.

In FIG. 6, "Data CLK" is a data clock generated from the main board of the system, and "mini LVDS CLK" is a clock generated from the data modulator 52 and transmitted with the data. &Quot; mini LVDS RGB " is a positive data waveform modulated by the data modulator 52 including the reset waveform. The data modulator 52 generates the negative data waveform with the inverse phase of the positive data waveform, and includes six pairs of data including the positive data waveform P and the negative data waveform N, respectively, as shown in FIG. 7. And a pair of mini LVDS clocks to the data ICs 32a. The first data IC 32a sampling the first data recognizes the start pulse (start) generated after the reset waveform as the data sampling start time and starts sampling the data supplied after the start pulse (start).

8 shows a signal transmission path between the timing controller 31 and the data ICs 32a.

Referring to FIG. 8, among the digital video data modulated by the timing controller 31 using the mini LVDS method or the RSDS method, the left data RGBodd and RGBeven are single output ports 53 and 2 of the timing controller 31. It is transmitted to the data ICs 32a connected to the first source PCB 41A via the port connection wiring 44 and the first FFC 43A. The left data RGBodd and RGBeven are data to be displayed on the left half screen of the liquid crystal display panel 30. The right data RGBodd and RGBeven modulated by the timing controller 31 in the mini LVDS method or the RSDS method include the single output port 53, the two-port connection wiring 44, and the second FFC of the timing controller 31. The data ICs 32a are connected to the second source PCB 41B via 43B. The right data RGBodd and RGBeven are data to be displayed on the right half screen of the liquid crystal display panel 30.

The leftmost first data IC 32a for sampling the first data samples the carry signal indicating the sampling timing of the next data after sampling the data after the start pulse by the number of output channels thereof in FIGS. 6 and 7. a carry) is generated and supplied to the second data IC 32a. Similarly, the carry signal is sequentially transmitted to neighboring data ICs 32a. The carry signal between the first and second source PCBs 41A and 41B is transmitted to the second FFC 43B, the two port connection wiring 44 formed on the control PCB 40 and the first FFC 43A. Is sent via. On the other hand, the data sampling direction of the data ICs 32a can be reversely adjusted. In this case, a carry signal is transmitted between the first and second source PCBs 41A and 41B via the first FFC 43A, the two port connection wiring 44 and the second FFC 43B. .

The driving voltages generated from the DC-DC converter mounted on the control PCB 40 are all data ICs 32a via the two port connection wiring 44, the first FFC 43A, and the second FFC 43B. Are supplied at the same time.

9 and 10 are circuit diagrams showing the data IC 32a in detail.

9 and 10, each of the data ICs 32a may include a shift register 61, a data recovery unit 62, a first latch array 63, a second latch array 64, and a digital-to-analog converter. Hereinafter referred to as "DAC" 65, a charge share circuit 66, and an output circuit 67 are included.

The data recovery unit 62 temporarily stores odd pixel data RGBodd and even pixel data RGBeven separated by the timing controller 31, and modulates the demodulation method corresponding to the modulation method by the timing controller 31. Restore the data. For example, the data recovery unit 62 generates '1' when the positive data is high logic and generates '0' when the positive data is low logic to restore the data. The data recovery unit 62 supplies the restored data RGBodd and RGBeven to the first latch array 63.

The shift register 61 shifts the sampling signal according to the source sampling clock SSC. In addition, the shift register 61 generates a carry signal Carry when data exceeding the number of latches of the first latch array 63 is supplied.

The first latch array 63 samples the digital video data RGBeven and RGBodd from the data restoring unit 62 in response to a sampling signal sequentially input from the shift register 61, and stores the data RGBeven. , RGBodd) is latched by one horizontal line, and then one horizontal line of data is simultaneously output.

The second latch array 64 latches one horizontal line of data input from the first latch array 63 and then, during the low logic period of the source output enable signal SOE, the other latches 64 of the other data ICs 32a. The digital video data RGBeven and RGBodd latched simultaneously with the second latch array 64 are output.

The DAC 65 includes a P-decoder (PDEC) 71 supplied with a positive gamma reference voltage GH and an N-decoder (NDEC) 72 supplied with a negative gamma reference voltage GL as shown in FIG. 10. And a multiplexer 73 for selecting the output of the P-decoder 71 and the output of the N-decoder 72 in response to the polarity control signals POL. The P-decoder 71 decodes the digital video data RGBeven and RGBodd input from the second latch array 64, and outputs a positive gamma compensation voltage GH corresponding to the gray level of the data. The decoder 122 decodes the digital video data RGBeven and RGBodd input from the second latch array 64 and outputs a negative gamma compensation voltage GH corresponding to the grayscale value of the data. The multiplexer 73 selects a positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal POL.

The charge share circuit 66 shorts the neighboring data output channels during the high logic period of the source output enable signal SOE to output the average value of the neighboring data voltages as the charge share voltage, or the source output enable signal. The common voltage Vcom is supplied to the data output channels during the high logic period of the SOE to reduce the sudden change of the positive data voltage and the negative data voltage.

The output circuit 67 includes a buffer to minimize attenuation of the analog data voltage supplied to the data lines D1 to Dk.

Meanwhile, as shown in FIG. 11, a method of separating the source PCB and dividing the output ports of the timing controller 111 into a plurality of divisions of the source PCB may be considered. In this case, the timing controller 111 and the control PCB 110 may be considered. Is bound to grow.

This will be described in detail as follows.

Assuming that the output ports of the timing controller 111 are divided into two, the timing controller 111 includes the left / right data separator 120, the two-port expander 121, and the data modulator 52 as shown in FIG. 12. ).

The left / right data separator 120 separates the input digital video data RGB input at the input frequency f into left data RGBl and right data RGBr using a frame memory. The data RGBl and RGBr output from the left and right data separators 120 are supplied to the two-port expansion unit 121 at 1/2 frequency f / 2 of the input frequency. When the output port of the timing controller 111 is separated by the left / right data separation unit 120, the size of the timing controller 111 is inevitably increased.

The two-port expansion unit 121 stores the left and right data RGBl and RGBr inputted from the left and right data separation unit 120 at 1/2 frequency f / 2 and the odd pixel data RGBlodd and RGBrodd. The data is separated into even pixel data RGBleven and RGBreven, and the data RGBodd and RGBeven are supplied to the data modulator 52 at 1/4 frequency f / 4.

The data modulator 122 increases the frequency of the data (RGBlodd, RGBrodd, RGBleven, RGBreven) from the 2-port expansion unit 121 according to the 4x mini LVDS clock when modulating data in the mini LVDS method. The left data (RGBlodd, RGBleven) and the right data (RGBrodd, RGBreven) are split and output to different output ports at the same frequency f. Since the left data RGBlodd and RGBleven and the right data RGBrodd and RGBreven each include three pairs of odd pixel data, three pairs of even pixel data, and one pair of mini clocks, the output pins of the timing controller 111 The number is required twice or more as compared to the embodiment of the present invention described above. The left data RGBlodd and RGBleven are transmitted to the first source PCB 131A via the first output port 141 and the first connection line 113A of the timing controller 111 and the right data RGBrodd and RGBreven. Is transmitted to the second source PCB 131B via the second output port 141 and the second connection wiring 113B of the timing controller 111.

As a result, when separating the source PCB, it is preferable to configure the output port of the timing controller as a single port in order to reduce the number of timing controllers and their output pins and to reduce the size of the control PCB.

As described above, the LCD and the driving method thereof according to the present invention can reduce the size of the control PCB and the number of output pins by dividing the source PCB and configuring the output port of the timing controller as a single output port.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A liquid crystal display panel including first and second data line groups each including a plurality of data lines, a plurality of gate lines intersecting the first and second data line groups, and a plurality of liquid crystal cells arranged in a matrix; A first data circuit group including data ICs for supplying data to the first data line group; A first source PCB to which the first data circuit group is connected; A second data circuit group including data ICs for supplying data to the first data line group; A second source PCB to which the second data circuit group is connected; A timing controller for controlling the first and second data circuit groups and a timing controller configured to output the data through a single output port; A control PCB on which the timing controller is mounted; And And connecting wires for electrically connecting the single output port to the first and second source PCBs. The method of claim 1, Each of the first and second data circuit groups, And any one of a chip on film (COF) and a tape carrier package (TCP) in which the data IC is mounted. The method of claim 1, The connection wirings, A first cable for electrically connecting the first source PCB and the control PCB; A second cable for electrically connecting the second source PCB and the control PCB; And And two port connection wires formed on the control PCB to electrically connect the single output port to the first and second cables. The method of claim 1, The timing controller, A two-port expansion unit for dividing digital video data input at an input frequency into odd pixel data and even pixel data and outputting the data at a frequency 1/2 of the input frequency; And And a data modulator for modulating data from the two-port expansion unit to reduce a swing width of data output through the single output port and output the data at a frequency twice as high as the input frequency. Device. The method of claim 4, wherein The data modulator, A liquid crystal display device characterized by modulating the data by any one of a mini low-voltage differential signaling (LVDS) scheme and a reduced swing differential signaling (RSDS) scheme. The method of claim 1, The control PCB, A memory for supplying waveform option information of the timing control signal to the timing controller; And And a voltage source for generating a driving voltage of the liquid crystal display panel. A first and second data line groups each including a plurality of data lines, a plurality of gate lines intersecting the first and second data line groups, and a liquid crystal display panel in which a plurality of liquid crystal cells are arranged in a matrix form. In the driving method of a liquid crystal display device, A second data circuit group including data ICs for supplying data to the first data line group, the first data circuit group including data ICs for supplying data to the first data line group, and the data ICs for supplying data to the first data line group Connecting to a second source PCB; Mounting a timing controller having a single output port on a control PCB; And Electrically connecting the single output port to the first and second source PCBs to supply timing control signals and data from the single output port to the first and second source PCBs. A method of driving a liquid crystal display device.

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