KR20080061693A - Vertical light emitting diode having a scattering center where a plurality of insulating layers are stacked and a manufacturing method thereof - Google Patents

Abstract

According to the present invention, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer are sequentially formed on a sacrificial substrate, and two or more insulating layers having different refractive indices are alternately stacked on the second conductive semiconductor layer. Partially patterning the stacked insulating layers to form a plurality of scattering centers spaced apart from each other, forming a metal reflective layer on the scattering centers, and forming a conductive substrate on the metal reflective layer And, it provides a vertical light emitting diode manufacturing method comprising the step of separating the sacrificial substrate.

According to the present invention, an active layer is formed by forming two or more insulating layers having different refractive indices in a metal reflective layer interposed between a conductive substrate and a semiconductor layer in a vertical light emitting diode to form a scattering center for forming a distributed bragg reflector (DBR). The light reflected from the light scattered by the scattering center is primarily reflected by the scattering center, and the light not reflected by the scattering center is secondly reflected by the metal reflecting layer, thereby improving light reflecting efficiency in the metal reflecting layer.

Description

Vertical light emitting diode having a scattering center in which a plurality of insulating layers are stacked and a method of manufacturing the same.

1 is a cross-sectional view for explaining a vertical light emitting diode according to the prior art.

2 is a cross-sectional view illustrating a vertical light emitting diode according to an embodiment of the present invention.

3 to 7 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical light emitting diode and a method of manufacturing the same, and more particularly, to a vertical light emitting diode having a scattering center in which a plurality of insulating layers are alternately stacked in a metal reflective layer, and a method of manufacturing the same.

In general, nitrides of Group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition energy band structure. It is attracting much attention as a substance. In particular, blue and green light emitting devices using gallium nitride (GaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

The nitride semiconductor layer of such a group III element, in particular GaN, is difficult to fabricate a homogeneous substrate capable of growing it, and thus, it is difficult to fabricate a homogeneous substrate capable of growing it. MBE) and other processes. As a hetero substrate, a sapphire substrate having a hexagonal structure is mainly used. However, since sapphire is an electrically insulator, it restricts the light emitting diode structure and is very stable mechanically and chemically, making it difficult to process such as cutting and shaping, and low thermal conductivity. Accordingly, in recent years, after the nitride semiconductor layers are grown on a dissimilar substrate such as sapphire, a technique of manufacturing a light emitting diode having a vertical structure by separating the dissimilar substrate has been studied.

1 is a cross-sectional view illustrating a vertical light emitting diode according to the prior art.

Referring to FIG. 1, the vertical light emitting diode includes a conductive substrate 31. Compound semiconductor layers including the first conductive semiconductor layer 15, the active layer 17, and the second conductive semiconductor layer 19 are positioned on the conductive substrate 31. In addition, an ohmic electrode 21, a metal reflection layer 23, a diffusion barrier layer 25, and a bonding layer 27 are interposed between the compound semiconductor layers and the conductive substrate 31.

 Compound semiconductor layers are generally grown on a sacrificial substrate (not shown), such as a sapphire substrate, using metalorganic chemical vapor deposition or the like. Thereafter, the ohmic electrode 21, the metal reflection layer 23, the diffusion barrier layer 25, and the junction metal layer 27 are formed on the compound semiconductor layers, and the conductive substrate 31 is attached thereto. Subsequently, the sacrificial substrate is separated from the compound semiconductor layers using a laser lift-off technique or the like, and the first conductivity type semiconductor layer 15 is exposed. Thereafter, an electrode pad 17 is formed on the exposed first conductive semiconductor layer 15. Accordingly, by adopting the conductive substrate 31 having excellent heat dissipation performance, the light emitting efficiency of the light emitting diode can be improved, and the light emitting diode of FIG. 1 having a vertical structure can be provided.

In general, the vertical light emitting diode adopts a metal reflection layer 23 to reflect light directed toward the conductive substrate 31 to improve luminous efficiency.

However, after the metal reflection layer 23 is formed on the ohmic electrode 21, heat treatment is performed at a temperature of 200 ° C. or higher for ohmic contact or bonding of the conductive substrate 31. At this time, the metal reflection layer 23 is oxidized during the heat treatment, there is a problem that the light reflectance is lowered to reduce the light output.

The technical problem to be achieved by the present invention is to compensate for the reduction in the light reflectivity of the metal reflective layer by heat treatment in the vertical light emitting diode to improve the luminous efficiency in the vertical light emitting diode.

According to an aspect of the present invention for achieving the above technical problem, the step of sequentially forming a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on the sacrificial substrate, the refractive index on the second conductive semiconductor layer Alternately stacking two or more different insulating layers, partially patterning the stacked insulating layers to form a plurality of scattering centers spaced apart from each other, and forming a metal reflective layer on the scattering centers; And forming a conductive substrate on the metal reflection layer, and separating the sacrificial substrate.

Preferably, the laminating step may be alternately laminated to the SiO ₂ layer and Si ₃ N ₄ layer.

Preferably, the laminating step may be laminated in a plurality of layers by repeatedly alternating two or more different insulating layers.

Preferably, in the forming of the scattering center, the stacked insulating layer may be etched into a matrix pattern of islands or a plurality of lines or reticulated patterns using photolithography.

According to another aspect of the present invention, in a vertical light emitting diode comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a metal interposed between the conductive substrate, the second conductive semiconductor layer and the conductive substrate. The present invention provides a vertical light emitting diode including a reflective layer and a plurality of scattering centers formed in the metal reflective layer and two or more insulating layers having different refractive indices and spaced apart from each other are alternately stacked.

Preferably, the plurality of scattering centers may be formed by alternately stacking an SiO ₂ layer and an Si ₃ N ₄ layer.

Preferably, the plurality of scattering centers may be stacked in a plurality of layers by repeatedly alternating two or more different insulating layers.

Preferably, the scattering center may be a matrix pattern of islands or a plurality of lines or a reticular pattern.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

2 is a cross-sectional view illustrating a vertical light emitting diode according to an embodiment of the present invention.

Referring to FIG. 2, compound semiconductor layers including a first conductive semiconductor layer 55, an active layer 57, and a second conductive semiconductor layer 59 are positioned on the conductive substrate 71. The conductive substrate 71 is a substrate such as Si, GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN or InGaN, but Al, Zn, Ag, W, Ti, Ni, Au, Mo, Pt, Pd, Cu, It may be a single metal of Cr or Fe or an alloy substrate thereof. On the other hand, the compound semiconductor layers are III-N series compound semiconductor layers, and the first conductivity type and the second conductivity type represent N type and P type, or P type and N type.

 An ohmic electrode 60 is interposed between the compound semiconductor layers and the conductive substrate 71. The ohmic electrode 60 is in ohmic contact with the second conductivity type semiconductor layer 59. The ohmic electrode 60 is preferably distributed over a wide surface of the second conductivity-type semiconductor layer 59 to distribute current, and the ohmic electrode 60 may be formed of Pt, Pd, Rh, or Ni. It may be formed of a metal material including at least one of.

A metal reflection layer 63 including a scattering center 61 is interposed between the ohmic electrode 60 and the conductive substrate 71.

The metal reflection layer 63 may be formed of a metal material having high reflectance, such as silver (Ag) or aluminum (Al), and may be formed of a metal material including at least one of them.

The scattering center 61 formed in the metal reflection layer 63 may be a pattern having various shapes such as a matrix pattern of islands, a plurality of lines or a reticular pattern.

The scattering center 61 is formed by alternately stacking two or more insulating layers having different refractive indices. For example, an SiO ₂ layer and an Si ₃ N ₄ layer may be alternately stacked.

The scattering center 61 is formed by growing the ohmic electrode 60, alternately stacking two or more insulating layers having different refractive indices into a plurality of layers, and then patterning etching the stacked insulating layers using photolithography. do. The insulating layers constituting the scattering center 224 are alternately stacked in the form of a reflective film. For example, the SiO ₂ layer and the Si ₃ N ₄ layer may be alternately alternately stacked in a plurality of layers.

As the scattering center 61 is formed by alternately stacking two or more insulating layers having different refractive indices into multiple layers, the light generated in the active layer 57 is conductive by performing a function of a distributed bragg reflector (DBR) to increase reflectance. As it proceeds to the substrate 71, it is primarily reflected by the scattering center 224, so that scattering occurs efficiently, thereby compensating for the light reflection of the metal reflective layer 63.

Distributed Bragg Reflectors (DBRs) are used in cases where high reflectivity is required in various light emitting devices including light emitting functions, light detection functions, light modulation functions, and the like.

Distributed Bragg Reflector (DBR) is a reflector reflecting light by alternately stacking two kinds of media having different refractive indices and using the difference in the refractive indices.

Meanwhile, the junction metal layer 67 may be interposed between the metal reflection layer 63 and the conductive substrate 71, and the diffusion barrier layer 65 may be interposed between the junction metal layer 67 and the metal reflection layer 63. The bonding metal layer 67 improves the adhesion between the conductive substrate 71 and the metal reflection layer 63 to prevent the conductive substrate 71 from being separated from the metal reflection layer 63, and the diffusion barrier layer 65 provides the bonding metal layer 67. Or metal elements are prevented from being diffused from the conductive substrate 71 to the metal reflection layer 63 to maintain the reflectivity of the metal reflection layer 63.

Meanwhile, the electrode pad 73 is positioned on the upper surface of the compound semiconductor layers to face the conductive substrate 71. The electrode pad 73 may be in ohmic contact with the first conductivity type semiconductor layer 55. Alternatively, an ohmic electrode (not shown) may be interposed between the electrode pad 73 and the compound semiconductor layers. In addition, extensions (not shown) extending from the electrode pad 73 may be located on the compound semiconductor layers. Extensions can be employed to spread out the current flowing into the compound semiconductor layers.

In the conventional vertical light emitting diode, the metal reflection layer (23 of FIG. 1) is oxidized at the time of heat treatment for bonding the conductive substrate using the junction metal layer, so that the light reflectance is lowered. On the contrary, according to the embodiment of the present invention, as light is scattered by the scattering center 61 formed in the metal reflection layer 63, the light reflectance of the metal reflection layer 63 may be compensated.

3 to 7 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode according to an embodiment of the present invention.

Referring to FIG. 3, compound semiconductor layers are formed on the sacrificial substrate 51. The sacrificial substrate 51 may be a sapphire substrate, but is not limited thereto and may be another hetero substrate. Meanwhile, the compound semiconductor layers include a first conductive semiconductor layer 55, an active layer 57, and a second conductive semiconductor layer 59. The compound semiconductor layers are III-N-based compound semiconductor layers, and may be grown by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). The first conductivity type and the second conductivity type represent N-type and P-type, or P-type and N-type.

Meanwhile, the buffer layer 53 may be formed before forming the compound semiconductor layers. The buffer layer 53 is adopted to mitigate lattice mismatch between the sacrificial substrate 51 and the compound semiconductor layers, and may generally be a gallium nitride-based material layer.

The ohmic electrode 60 is formed on the second conductive semiconductor layer 59.

The ohmic electrode 60 is deposited on the entire surface using a plating or deposition technique. The ohmic electrode 60 includes a material in ohmic contact with the second conductivity-type semiconductor layer 59. When the second conductivity-type semiconductor layer 59 is a P-type semiconductor, the ohmic electrode 60 is platinum (Pt). It may be formed of a material containing palladium (Pd), rhodium (Rh) or nickel (Ni). The ohmic electrode 60 is generally heat treated to be in ohmic contact with the second conductivity-type semiconductor layer 59, but the ohmic electrode is heat-treated by being formed of platinum (Pt), palladium (Pd), rhodium (Rh), or nickel (Ni). May be omitted.

Next, the scattering center 63 is formed on the upper surface of the ohmic electrode 60. In this embodiment, a SiO ₂ layer is laminated as the first insulating layer on the ohmic electrode 60 to form the scattering center 63. The thickness of the SiO ₂ layer to be laminated is preferably 10 GPa or more.

When the SiO ₂ layer is laminated on the ohmic electrode 60 as the first insulating layer, the Si ₃ N ₄ layer is laminated as the second insulating layer on the SiO ₂ layer. The thickness of the Si ₃ N ₄ layer to be laminated is preferably 10 GPa or more.

When the Si ₃ N ₄ layer is laminated as the _second insulating layer, SiO ₂ and Si ₃ N ₄ are alternately stacked as a plurality of layers as the insulating layer.

The number of alternating stacks of SiO ₂ and Si ₃ N ₄ forming the scattering center 61 may be determined in consideration of the thickness of each insulating layer.

After the SiO ₂ layer and the Si ₃ N ₄ layer are alternately stacked, the stacked insulating layers are patterned and etched using photolithography to form a scattering center 61 having a mesh pattern.

When the scattering center 61 is formed, a metal reflective layer 63 is formed on the scattering center 61. The metal reflection layer 63 may be entirely deposited to cover the scattering center 61 using plating or deposition techniques, and may be formed of a metal layer including Al or Ag.

Referring to FIG. 6, a conductive substrate 71 is formed on the metal reflection layer 63. The conductive substrate 60 is a substrate such as Si, GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN or InGaN, but Al, Zn, Ag, W, Ti, Ni, Au, Mo, Pt, Pd, Cu, It can be formed by attaching a single metal of Cr or Fe or an alloy substrate thereof onto the compound semiconductor layers. In this case, the conductive substrate 60 may be attached to the metal reflection layer 63 through the junction metal layer 67, and the diffusion barrier layer 65 may be formed on the metal reflection layer 63 before the junction metal layer 67 is formed. Can be. On the other hand, the conductive substrate 71 can be formed using a plating technique. That is, the conductive substrate 71 may be formed by plating a metal such as Cu or Ni on the metal reflection layer 63, and for improving the diffusion barrier layer 65 and / or the adhesive force for preventing the diffusion of metal elements. A junction metal layer 67 may be added.

Referring to FIG. 7, the sacrificial substrate 51 is separated from the compound semiconductor layers. The sacrificial substrate 51 may be separated by laser lift off (LLO) technology or other mechanical or chemical methods. At this time, the buffer layer 53 is also removed to expose the first conductivity-type semiconductor layer 55.

Subsequently, an electrode pad (73 in FIG. 2) is formed on the first conductive semiconductor layer 55. The electrode pad 73 is in ohmic contact with the first conductive semiconductor layer 55. In addition, while the electrode pad 73 is formed, extensions (not shown) extending from the electrode pad 73 may be formed together. Thus, the vertical light emitting diode of FIG. 2 is manufactured.

Meanwhile, before forming the electrode pad 73, an ohmic electrode (not shown) may be formed on the first conductive semiconductor layer 55. The ohmic electrode is in ohmic contact with the first conductivity type semiconductor layer 55, and the electrode pad 73 is electrically connected to the ohmic electrode.

The present invention is not limited to the above described embodiments, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention as defined in the appended claims.

For example, as an embodiment of the present invention, the scattering centers formed by alternately stacking a plurality of layers of SiO ₂ and Si ₃ N ₄ as insulating layers in the metal reflective layer and forming the scattering centers were formed.

However, in addition to SiO ₂ and Si ₃ N ₄ , the scattering center pattern may be formed using an insulating layer having different refractive indices as the insulating layer.

According to the present invention, an insulating layer having different refractive indices is stacked in a metal reflective layer interposed between a conductive substrate and a semiconductor layer in a vertical light emitting diode to form a scattering center for forming a distributed bragg reflector (DBR), thereby generating in an active layer. Thus, the light propagating toward the conductive substrate can be efficiently reflected.

Accordingly, light traveling toward the conductive substrate among the light generated by the active layer is primarily reflected by the scattering center formed in the metal reflective layer, and light not reflected by the scattering center is secondarily reflected by the metal reflective layer. The light reflection efficiency is improved in the reflective layer.

Claims (8)

Sequentially forming a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the sacrificial substrate; Alternately stacking two or more insulating layers having different refractive indices on the second conductive semiconductor layer; Partially patterning the stacked insulating layers to form a plurality of scattering centers spaced apart from each other; Forming a metal reflective layer on the scattering center; Forming a conductive substrate on the metal reflection layer; Vertical light emitting diode manufacturing method comprising the step of separating the sacrificial substrate. The method of claim 1, wherein the laminating step, A vertical light emitting diode manufacturing method of alternately stacking SiO ₂ layer and Si ₃ N ₄ layer. The method of claim 1, wherein the laminating step, A vertical light emitting diode manufacturing method of repeatedly stacking two or more different insulating layers in a plurality of layers. The method of claim 1, wherein the scattering center forming step, And fabricating the stacked insulating layer using a photolithography to etch a matrix pattern of islands or a plurality of lines or reticulated patterns. In the vertical light emitting diode comprising a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, A conductive substrate, A metal reflection layer interposed between the second conductive semiconductor layer and the conductive substrate; And a plurality of scattering centers formed in the metal reflective layer and having two or more insulating layers having different refractive indices spaced apart from each other and alternately stacked. The method of claim 5, wherein the plurality of scattering centers are A vertical light emitting diode in which an SiO ₂ layer and an Si ₃ N ₄ layer are alternately stacked. The method of claim 5, wherein the plurality of scattering centers are A light emitting device stacked in a plurality of layers by repeatedly alternating two or more different insulating layers. The method of claim 5, wherein the plurality of scattering centers are A vertical light emitting diode that is a matrix pattern of islands or a plurality of lines or reticular patterns.

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