KR20070069415A - Semiconductor test apparatus and test method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus and a test method thereof, and in detail, a test apparatus due to instantaneous overvoltage and overcurrent by turning off power after testing each test item in a control unit. And it is effective to prevent damage to the probe card, in the case of multi-site (multi-site test) to apply power only to the valid site and the other site has the effect of preventing damage to the test device and the probe card, further By preventing damage to the test equipment and probe cards, it also saves considerable time and money.

Description

Test device for the semiconductor and the testing method

1 is a diagram showing a test procedure of a semiconductor according to the prior art.

2 is a view showing a schematic configuration of a semiconductor test apparatus according to the present invention.

3A is a diagram illustrating a test method of a semiconductor test apparatus according to the prior art, and FIG. 3B is a diagram illustrating a test procedure according to an embodiment of the semiconductor test apparatus according to the present invention.

4 is a view showing a preferred embodiment by a semiconductor test method according to the present invention.

Description of the main parts of the drawing

10; Computer 20; Test system

22; Driver 24; Comparator

30; Tester 32; Test head

34; Load boat 36; Probe card

38; Probe 39; Probe station

40; Wafer 50; Control unit 100; Wafer Test Equipment

The present invention relates to a test device for a semiconductor and a test method thereof.

In general, semiconductor memory manufacturing processes go through wafer processing, testing, packaging, and reliability tests to complete a single memory product. A test method using a test apparatus for a semiconductor memory in a semiconductor manufacturing process will be described in detail with reference to FIG. 1.

1 is a diagram illustrating a procedure of a semiconductor memory test according to the prior art.

In the semiconductor manufacturing process, the wafer process is referred to as the pre-process (S1) and the test, packaging, and reliability test are referred to as the post-process (S2).

In addition, the wafer process S1 is a front end of the line (FEOL) S11 which is a process for processing oxidation and diffusion, and a back end of the which is a process of forming wiring on the surface thereof. line, BEOL) (S12).

On the other hand, the semiconductor memory test typically refers to a series of processes consisting of testing different items at various stages before and after packaging (S24) in the post-process (S2).

Therefore, the semiconductor memory test is largely divided into a wafer test S23 performed in a wafer state before packaging S24 and a package test S25 through S28 performed in a later package state. The semiconductor memory test will be described in detail step by step.

First, the pre-laser repair test S21 and the laser repair S22 will be described. The pre-laser test (S21) is a test performed in a wafer state before laser repair, and distinguishes between a chip that can be repaired and a chip that cannot be repaired by replacing a redundancy cell after screening a memory failure cell. Next, the laser repair (S22) is a step in which repairable faulty cells masked in the pre-laser test (S21) are turned into good dies by laser repair replacing a given spare cell.

Next, a wafer test S23 will be described.

The wafer test S23 is a step of testing the entire chip on the wafer after the laser repair S22 to test overall functions, operations, and the like after the laser repair S22. In this process, if it is determined to be a good die, the process proceeds to the next packaging (S24) process. However, if it is determined to be a bad die, ink is displayed on the wafer surface, which is called an ink die. It is completely removed so as not to lead to the process. This process is done automatically using an automatic wafer prober.

Next, packaging (S24) is a step of assembling a good memory die into a package for final production.

After the packaging (S24) is finished, a package test (S25 ~ S28) is performed to determine whether the product is defective or the characteristics of the memory in the package state. Package testing is typically performed with memory running at normal operating speeds. This is explained in more detail.

First, the pre-burn in test (S25) is a step of testing the entire packaged semiconductor memory with a memory test device, which is a process for screening out defects generated during the assembly process, which is tested by an automated system. Is done.

Next, the burn-in test S26 is a test performed in a condition where the temperature and voltage are slightly severe to detect an early defect in the memory while the semiconductor memory is packaged.

Next, the final test S27 is to test the entire memory according to the test item by an automatic handler to remove the memory determined as defective in the burn-in test S26 process.

Next, the reliability test (S28) extracts a certain number of samples from a good lot of memory lot selected in the final test (S27) process to confirm long-term reliability of temperature and voltage under more severe conditions. Test it under

Finally, the lot decision (S29) and shipping (S30) step is a step in which the lot determined that there is no problem in reliability during the reliability test (S28) is a step of receiving or shipping. Through the above process, one memory product is completed.

Hereinafter, a test apparatus in a semiconductor manufacturing process will be described.

The equipment used in the semiconductor manufacturing process corresponding to the test process is called a test apparatus. As described above, before moving to the packaging (S24) process from the wafer state, it is possible to determine whether the semiconductor wafer chip is unsuccessful and repair the wafer, and the test equipment used here is a test device for a Fab Line. The test equipment for classifying and testing the quantity before and after shipment of the product on the package is called the test apparatus for assembly.

If the test apparatus is classified by the semiconductor under test, it may be divided into a memory test apparatus, a logic test apparatus, and a linear and discontinuous test apparatus.

However, the test method of the conventional semiconductor memory test device and the logic test device does not have much damage to the test device and the probe card due to the change of voltage and current since the change of voltage and current is not so large during the test. . This is because conventional semiconductors are classified into analog signal semiconductors or digital signal semiconductors, so the voltage and current changes are not so large during the test.

Recently, however, a mixed signal device having a digital signal semiconductor and an analog signal semiconductor in a single chip is mainly used.

However, when testing such a mixed-signal semiconductor, voltage and current are often suddenly changed, and very high currents are often applied, so if a mistake is made, a problem may occur in the PMU (Precision Measurement Unit) of the test apparatus or a probe card. ) Probe or needle burned out.

In addition, in recent years, as the integration of memory increases, the test time becomes longer, and a multi-site test or multi-site test method is introduced to increase the test throughput per hour.

In a multisite test where multiple chips can be tested at the same time, however, when a site on a probe card contacts an invalid die at the edge of the wafer, a momentary high voltage, When the current is applied, the probe is subjected to a lot of stress, and when a certain limit is exceeded, a problem occurs that burns out.

In particular, if the problem occurs at least once, a problem arises in that a lot of time and huge costs are required to repair the test apparatus and the probe card.

 Therefore, an object of the present invention is to prevent damage to the test apparatus and the probe card by devising a test apparatus and a test method suitable for the characteristics of the semiconductor.

The semiconductor test apparatus according to the present invention for achieving the above object is to cut off the power to the tester after the first test when the tester for testing the semiconductor and at least two or more tests sequentially through the tester 2 is characterized in that it comprises a control unit for applying power to the tester for the test.

In addition, when multi-testing a plurality of semiconductors simultaneously, the controller may apply power to a tester for testing valid semiconductors among a plurality of selected semiconductors, and cut off power to a tester for testing invalid semiconductors.

In addition, the controller may limit at least one of a voltage and a current applied according to an item of the test.

In the semiconductor test method according to the present invention for achieving the above object, in the case of performing at least two or more tests on a semiconductor sequentially, performing a first test on the semiconductor, and after the first test Blocking and applying power to the semiconductor for a second test.

In addition, at least one of a voltage and a current applied to each test type may be limited.

The semiconductor test method according to the present invention for achieving the above object comprises the steps of selecting the semiconductor as a valid semiconductor and an invalid semiconductor when multi-testing a plurality of semiconductors at the same time, the tester for testing the valid semiconductor The tester for applying power and testing an invalid semiconductor is characterized in that it comprises the step of shutting off the power.

According to the present invention, by controlling the voltage and current applied to the semiconductor under test in the control unit of the semiconductor test device to protect the test device due to the instantaneous overvoltage, overcurrent, and prevent damage to the test device, considerable time and money wasted There is an advantage to prevent.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The semiconductor test apparatus according to the embodiment of the present invention may be divided into a wafer test apparatus, a package test apparatus, and a memory module test apparatus according to a test target.

Semiconductors to which the semiconductor test apparatus according to the embodiment of the present invention may be applied may include an analog signal semiconductor, a digital signal semiconductor, and a mixed signal semiconductor.

The wafer test apparatus, package test apparatus, and memory module test apparatus will be described below in order.

2 is a view showing a schematic configuration of a semiconductor test apparatus, in particular a wafer test apparatus (hereinafter referred to as a "wafer test apparatus") according to an embodiment of the present invention.

The wafer test apparatus 100 according to the embodiment of the present invention, when testing the tester 30 and at least two or more items (item) for testing a predetermined semiconductor, after the predetermined test is turned off (down) and the And a controller 50 configured to control the tester 30 to apply power to test another item. Hereinafter, the control unit 50 and the tester 30 will be described in order.

The controller 50 includes a computer 10 for instructing a predetermined test program for controlling the wafer test apparatus 100 and a test system 20 for executing a test program indicated by the computer 10. It may include.

The computer 10 may include a central processing unit (CPU), a keyboard, and a monitor, and serves to indicate a predetermined test program for controlling the test apparatus 100.

Next, the test system 20 includes a power supply (not shown), a driver 22, a comparator 24, a PMU (Precision Measurement Unit) (not shown), a clamp ( Clamp (not shown), the hardware of such a test system 20 is controlled by the computer 10.

The comparator 24 is a device used for a functional test and senses a logic 0 or logic 1 level value from the wafer 40 under test. The functional test is to test whether the wafer 40 properly performs logical arithmetic functions, and input data is supplied to the wafer 40. The output data is read from wafer 40 to perform the test.

On the other hand, the comparator 24 may be built in the test head 32 of the tester 30 to be described later.

The PMU (Precision Measurement Unit or Parametric Measurement Unit) measures a current by applying a voltage or measures a voltage by applying a current.

The clamp is hardware that limits the amount of voltage or current supplied by the test system 20 during the test, and the test operator, the test apparatus 100, and the wafer 40 by the clamp. Serves to protect it.

Next, a tester 30 that tests a given wafer 40 in accordance with a test program performed by the test system 20 will be described.

The tester 30 should provide the correct voltage and current to the wafer 40 at an appropriate time, and output the response of the wafer 40 to each test item on the screen of the tester 30. Then, each test result is compared with a predefined limit to determine the positive and negative (P / F).

The tester 30 may include a test head 32, a load board 34, a probe card 36, a probe 38, and a probe station 39.

The test head 32 supplies an input signal to the wafer 40 and receives an output signal.

The load board 34 serves to connect the tester 30 and the wafer 40.

The probe 38 refers to a mechanism that makes direct contact with a pad on a die because the test is performed on a semiconductor wafer. The probe 38 may be used by adjusting a plurality of thin long needle-shaped pins to match the pad spacing.

The probe card 36 refers to a board on which the probe 38 is mounted. The probe card 36 contacts the pad of the die to be tested with an epoxy 38 fixed on the PCB to test each die on the wafer 40 and then dies the electrical signal of the test system 20. It is a key device that connects each signal wiring of the test and each pad on the wafer in a chip unit so that the wafer 40 can be tested. Usually one probe card 36 may be equipped with a probe 38 so that at least 16 dies can be contacted simultaneously.

The probe station 39 is a device for coupling with the tester 30, the main function of which automatically transfers the wafer 40 to the tester 30, auto-aligns the probe 38 and the pad, It performs the test by sequentially probing several dies, provides the temperature environment (-10 to + 100 ° C) necessary for the test, and unloads after the test is completed to sort out good and bad.

As shown in FIG. 2, when each pin of the probe 38 and the test system 20 are connected, the computer 10 operates a test program to measure data, process measured data, and collect each unit to test the system. (20) is comprehensively controlled. The driver 22 and the comparator 24 generate a desired signal or check the function operation by comparing with expected data.

Hereinafter, a characteristic test method of the semiconductor test apparatus according to the present invention will be described with reference to the drawings.

3A is a diagram illustrating a test method of a conventional semiconductor test apparatus, and FIG. 3B is a diagram illustrating a test procedure according to an embodiment of the semiconductor test apparatus according to the present invention. 3 may be applied to both a wafer tester, a package tester, and a semiconductor module tester.

3A and 3B show an open test and a short test, and the test is performed in proper contact with the pin of the probe card 36 and the semiconductor memory (except a pad in the wafer test). It is tested to see if it is done and which pin is shorted to another pin or power supply. A short may occur when pads are not normally formed on an invalid chip, and the chip 38 is in contact with the probe 38 although the probe 38 of the probe card 36 is not directly shorted. The presence of a metal layer on the pad portion of the pad may cause unwanted shorts. Therefore, an invalid chip (insulating layer, etc.) may skip the test process by the open test / short test. In addition, the open test / short test may detect not only the open / short of the semiconductor memory but also the open / short of the invisible process inside the semiconductor memory.

However, as illustrated in FIG. 3A, when a test of several items is required in one semiconductor device, the test for each item is continuously performed without shutting off the power. As a result, when a sudden change in current or voltage occurs due to a difference in current and voltage according to a test item, a problem occurs that damages not only the semiconductor being tested but also the semiconductor test apparatus.

Therefore, in the present invention, as shown in Fig. 3b, when the test of each test item is finished, the power is turned off for initialization. As a result, there is an effect of preventing the problem of damage to not only the semiconductor being tested but also the semiconductor test apparatus by preventing sudden changes in current or voltage due to a difference in current and voltage according to each item.

Next, Figure 4 is a view showing another embodiment by a semiconductor test method according to the present invention.

Recently, as the degree of integration of semiconductor memory increases, a multi-site test method has been widely introduced. The multi-site test may also be applied to the present invention. For example, if the channel of the semiconductor test apparatus is 512, and the number of pins of the semiconductor memory to be tested is 128 or less, the test may be performed by configuring up to four sites.

According to the test method of the semiconductor test apparatus according to the present invention, as shown in Figure 4, when performing a multi-site test that can test the chips of several semiconductor wafers 200 at a time, the edge of the semiconductor wafer 200 Turn off the power of the invalid invalid die (Dummy die) 120 in the (edge) portion, and apply only the valid test die (110). As a result, when a site of the probe card contacts an invalid invalid die 120 at the edge portion of the semiconductor wafer 200, a high voltage and current are instantaneously applied to the invalid die 120. Probe 130 is subjected to a lot of stress and the problem of burning over a certain limit is prevented.

Next, another embodiment of a semiconductor test method according to the present invention will be described.

Conventional test equipment was simply made of a function of supplying only a predetermined voltage and current, but the present invention is characterized in that it is changed to a function that can be adjusted more finely. By doing so, the voltage and current required for each test item are controlled in advance, thereby preventing the sudden change of the voltage and current for each item in the semiconductor test apparatus in advance. This function can be performed by a clamp, hardware that limits the amount of voltage or current supplied by the test system during the test.

Next, the test apparatus according to the embodiment of the present invention can be applied to the package test in the memory test. This will be described in detail below.

Package inspection apparatus according to an embodiment of the present invention is similar in configuration to the wafer inspection apparatus 100 described above.

On the other hand, in the package inspection apparatus according to an embodiment of the present invention the equipment corresponding to the probe station 39 of the wafer inspection apparatus 100 is called a test handler (not shown).

The basic function of the test handler is to create a temperature and environment suitable for testing a semiconductor memory in a package test process, and to automatically transfer the memory to a location to be tested for electrical testing.

The test handler may be classified into various types according to its purpose, and may be classified into vertical and horizontal test handlers according to the memory transfer method.

The vertical test handler includes a tray loader, a preheating zone, an input shuttle, a test site, an output shuttle and a tray unloader. You can do this, and there can be one to four test sites.

In addition, the semiconductor test apparatus according to an embodiment of the present invention may be applied to a memory module test apparatus. This will be described in detail below.

Recently, with the rapid development of packaging technology, memory modules are being shipped that can be used in the form of modules instead of mounting the memory directly on the PCB and inserted into the memory sockets of the motherboard.

The memory module package applicable to the memory module test apparatus according to an embodiment of the present invention includes a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a rambus in-line memory module (RIMM), There may be a j-lead chip carrier (JLCC).

The test handler of the memory module inspection apparatus according to an exemplary embodiment of the present invention carries a loader for supplying a module to be tested from the outside, transports the module from a tray containing the module to a place for testing, and simultaneously picks up and transfers several modules. It may include a gripper, a test site where the module is plugged into a socket electrically connected to the tester, and an unloader classified and shipped as a shipping tray or a defective tray according to the test result. Such a memory module test handler can multi test 1 to 16 memory modules.

As described above, according to the semiconductor test apparatus and the test method thereof, after the test of each test item is completed, the controller cuts off the power to provide an instantaneous overvoltage, This prevents damage to the test equipment and the probe card due to overcurrent.

In addition, according to an embodiment of the present invention, when the multi-site test to the control unit is applied to power only the site (test) and other sites to cut off the power to prevent damage to the test device and the probe card It works.

In addition, according to an embodiment of the present invention by setting a predetermined limit value for each test item to a function for supplying the voltage and current for the test item to the control unit to more stably control the application of voltage and current to the test device and probe card It is effective to prevent damage.

In addition, according to an embodiment of the present invention, by preventing the damage to the test apparatus and the probe card by the above method, there is also an effect of preventing significant time and money waste.

Claims (6)

A tester for testing semiconductors, In the case where at least two or more tests are sequentially performed through the tester, the semiconductor test unit may include a control unit which cuts power to the tester after the first test and applies power to the tester for the second test. Device. The method of claim 1, The control unit applies power to a tester for testing valid semiconductors among a plurality of selected semiconductors when multi-testing a plurality of semiconductors simultaneously, and cuts off power to a tester for testing invalid semiconductors. The method according to claim 1 or 2, The control unit limits the at least one of the voltage and current applied according to the type (item) of the test. In the case where at least two or more tests are sequentially performed on a semiconductor, Performing a first test on the semiconductor; Disconnecting power after the first test; And applying power to the semiconductor for a second test. The method of claim 4, wherein And limiting at least one of a voltage and a current applied according to each test type. In the case of multi-testing a plurality of semiconductors at the same time, Selecting the semiconductor as a valid semiconductor and an invalid semiconductor; Applying a power to a tester for testing the valid semiconductor and cutting off the power to the tester for testing the invalid semiconductor.

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