KR20060023489A - Method of forming gate pattern of semiconductor device - Google Patents

Abstract

A method of forming a gate pattern of a semiconductor device is provided. The method includes forming a gate structure including a first conductive film pattern, an inter-gate dielectric film pattern, and a second conductive film pattern on a semiconductor substrate on which a tunnel oxide film is formed. A low temperature selective oxidation process is performed on the resultant having the gate structure to form a leakage preventing insulating layer covering sidewalls of the first conductive layer pattern and the second conductive layer pattern. A spacer is formed to cover sidewalls of the gate structure having the leakage preventing insulating layer. In one embodiment, the low temperature selective oxidation process may be a plasma radical oxidation process performed at a temperature of 600 ° C or less.

Flash, reoxidation, leakage current, buzz big

Description

Method of forming gate pattern of semiconductor device

1 to 4 are cross-sectional views illustrating a gate pattern forming method of a flash memory device according to an exemplary embodiment of the present invention.

5 to 10 are cross-sectional views illustrating a gate pattern forming method of a flash memory device according to another exemplary embodiment of the present invention.

Description of the main parts of the drawing

100 semiconductor substrate 102 tunnel oxide film

104: first conductive film pattern 106: inter-gate insulating film pattern

108: second conductive film pattern 110: metal film pattern

112: capping film pattern 114: gate structure

118: leakage prevention insulating film 120: spacer

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate pattern of a flash memory device.

Flash memory devices are nonvolatile memory devices that can electrically dissipate or program information. Recently, flash memory devices are widely used as memory devices of electronic products such as computers and digital cameras. The unit cell gate pattern of the flash memory device includes two gates, a floating gate used as a charge storage layer and a control gate for controlling input and output signals. The floating gate is spaced apart from the semiconductor substrate by a tunnel oxide film, and the floating gate and the control gate are electrically insulated from each other by an inter-gate dielectric layer interposed therebetween. In this case, the inter-gate insulating film insulates the floating gate from the control gate so that the floating gate can serve as a charge storage layer.

Generally, the floating gate and the control gate are made of a polysilicon film. In addition, the inter-gate insulating film may be formed of a silicon oxide film / silicon nitride film / silicon oxide film (silicon oxide layer / silicon nitride layer / silicon oxide layer). However, as the integration degree of the flash memory device increases, the demand for a low resistance gate pattern and an inter-gate insulating film that can replace the ONO film are increasing. Accordingly, in order to implement a low resistance gate pattern, a metal gate is stacked on the polysilicon layer to form a control gate. As the metal film, a tungsten film, a titanium film or a tantalum film having a low specific resistance and a high melting point is used. In addition, research is being conducted to replace the ONO film used as the inter-gate insulating film with a high-k dielectric layer.

Meanwhile, in the process of forming the gate pattern of the semiconductor device, dry etching such as plasma etching or reactive ion etching (RIE) is generally used. However, when the gate pattern is formed using the dry etching, the edge of the gate oxide layer under the gate pattern may be etched. The etching damage affects the dielectric breakdown voltage of the gate oxide layer and thus acts as a factor that hinders the reliability of the device. Therefore, after the gate pattern is formed to heal the etching damage of the gate oxide film, an additional oxidation process called a reoxidation process is performed. An example of such a reoxidation process is disclosed in US Pat. No. 6,372,618.

During the process of forming the gate pattern of the flash memory device, the reoxidation process is performed to heal etch damage of the tunnel oxide film. The reoxidation process is performed at a high temperature of about 850 ° C. or higher, in which case an oxidant penetrates through an interface between the inter-gate insulating film and the floating gate and an interface between the inter-gate insulating film and the control gate. Bird's beaks are formed on both sides of the inter-gate insulating film. When the thickness of the inter-gate insulating layer increases due to the buzz big, the cell characteristic distribution of the flash memory device may increase. In addition, when the high dielectric film is used as the inter-gate insulating film as described above, the floating gate and the control gate may be contaminated by metal atoms diffused from the high dielectric film during the reoxidation process.

In order to solve these problems, a method of performing a reoxidation process after forming a silicon nitride film spacer covering the sidewall of the gate pattern may be attempted. However, in this case, a leakage current may occur between the floating gate and the insulating gate along an interface between the silicon nitride film spacer and the gate pattern.

The technical problem to be achieved by the present invention is to form a reliable gate pattern by suppressing the phenomenon that the thickness of the inter-gate insulating film is increased by the Buzz Big during the gate reoxidation process, and prevent the leakage current between the polysilicon gates.

In order to achieve the above technical problem, the present invention provides a method of forming a gate pattern of a semiconductor device having a leakage barrier insulating layer.

According to an aspect of the present invention, a method of forming a gate pattern of the semiconductor device includes forming a gate structure including a first conductive layer pattern, an inter-gate dielectric layer pattern, and a second conductive layer pattern on a semiconductor substrate on which a tunnel oxide layer is formed. do. A low temperature selective oxidation process is performed on the resultant having the gate structure to form a leakage preventing insulating layer covering sidewalls of the first conductive layer pattern and the second conductive layer pattern. A spacer is formed to cover sidewalls of the gate structure having the leakage preventing insulating layer.

In some embodiments, the first conductive layer pattern and the second conductive layer pattern may be formed of a polysilicon layer.

In example embodiments, the gate structure may further include a metal layer pattern stacked on the second conductive layer pattern. In this case, the metal film pattern may include a tungsten film pattern.

In still other embodiments, the inter-gate dielectric layer pattern may be formed of an ONO layer or a high dielectric layer. In this case, the high-k dielectric film is at least one film selected from the group consisting of aluminum oxide film (AlO), hafnium oxide film (HfO), hafnium silicon oxide film (HfSiO), hafnium aluminum oxide film (HfAlO), and tantalum oxide film (TaO). It may be a laminated film by a combination of the two.

In yet other embodiments, the low temperature selective oxidation process may be carried out at a temperature of less than 600 ℃. The low temperature selective oxidation process is preferably a radical oxidation process using hydrogen radicals and oxygen radicals contained in the plasma.

In still other embodiments, the leakage preventing insulating layer may be formed to have a thickness of about 5 kPa to about 100 kPa.

In some embodiments, sidewalls of the first conductive layer pattern, the inter-gate dielectric layer pattern, and the second conductive layer pattern may be selectively etched to reduce their widths before performing the low temperature selective oxidation process. have.

In still other embodiments, after the spacer is formed, an additional oxidation process may be performed on the resultant product having the spacer. In this case, the additional oxidation process may be a radical oxidation process using plasma.

According to another aspect of the present invention, the method includes forming a first conductive film line on a semiconductor substrate on which a tunnel oxide film is formed. An inter-gate insulating film and a second conductive film are formed on the semiconductor substrate having the first conductive film line. The second conductive film and the inter-gate insulating film are patterned to expose the first conductive film line, thereby forming a preliminary gate structure including an inter-gate insulating film pattern and a second conductive film pattern and crossing the first conductive film line. do. A low temperature selective oxidation process is performed on the resultant having the preliminary gate structure to form a leakage preventing insulating layer covering the exposed regions of the first conductive layer line and the sidewalls of the second conductive layer pattern. A spacer is formed to cover sidewalls of the preliminary gate structure. The first conductive film line is patterned to form a first conductive film pattern overlapping the lower portion of the preliminary gate structure and the spacer. Further oxidation of the resultant having the first conductive layer pattern is performed.

In some embodiments, the first conductive layer pattern and the second conductive layer pattern may be formed of a polysilicon layer.

In other embodiments, the method may further include forming a metal film on the second conductive film. In this case, the metal film may include a tungsten film and is patterned together with the second conductive film and the inter-gate insulating film.

In still other embodiments, the inter-gate dielectric layer may be formed of an ONO layer or a high dielectric layer. In this case, the high-k dielectric film is at least one film selected from the group consisting of aluminum oxide film (AlO), hafnium oxide film (HfO), hafnium silicon oxide film (HfSiO), hafnium aluminum oxide film (HfAlO), and tantalum oxide film (TaO). It may be a laminated film by a combination of the two.

In yet other embodiments, the low temperature selective oxidation process may be carried out at a temperature of less than 600 ℃. The low temperature selective oxidation process is preferably a radical oxidation process using hydrogen radicals and oxygen radicals contained in the plasma.

In still other embodiments, the leakage preventing insulating layer may be formed to have a thickness of about 5 kPa to about 100 kPa.

In still other embodiments, before performing the low temperature selective oxidation process, sidewalls of the second conductive layer pattern and the inter-gate dielectric layer pattern, and the exposed regions of the first conductive layer line may be selectively etched. The width of the preliminary gate structure may be reduced.

In yet other embodiments, the additional oxidation process may be a radical oxidation process using plasma.

In another embodiment, after the additional oxidation process, a spacer covering sidewalls of the spacer and the first conductive layer pattern may be formed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1 to 4 are cross-sectional views illustrating a gate pattern forming method of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a tunnel oxide film 102 is formed on a semiconductor substrate 100. The tunnel oxide layer 102 may be a thermal oxide layer. Although not shown in the drawings, an isolation layer defining an active region is formed on the semiconductor substrate 100, and the tunnel oxide layer 102 is formed to cover the active region. The gate structure 114 is formed on the semiconductor substrate 100 on which the tunnel oxide film 102 is formed. The gate structure 114 may include a first conductive layer pattern 104, an inter-gate dielectric layer pattern 106, and a second conductive layer pattern 108 that are sequentially stacked on the tunnel oxide layer 102. In addition, the gate structure 114 may further include a metal layer pattern 110 and a capping layer pattern 112 that are sequentially stacked on the second conductive layer pattern 108.

The first conductive layer pattern 104 and the second conductive layer pattern 108 may be formed of a polysilicon layer. The inter-gate dielectric layer pattern 106 may be formed of an ONO layer or a high dielectric layer. In this case, the high-k dielectric film is at least one film selected from the group consisting of aluminum oxide film (AlO), hafnium oxide film (HfO), hafnium silicon oxide film (HfSiO), hafnium aluminum oxide film (HfAlO), and tantalum oxide film (TaO). It can be made of a laminated film by a combination of the two. The metal film pattern 110 may include a tungsten film, preferably, a tungsten nitride film and a tungsten laminate film. The capping layer pattern 112 may be formed of a silicon nitride layer. The first conductive film pattern 104 is provided as a floating gate of the flash memory device, and the second conductive film pattern 108 and the metal film pattern 110 are provided as a control gate of the flash memory device.

Referring to FIG. 2, after forming the gate structure 114, sidewalls of the first conductive layer pattern 104, the inter-gate dielectric layer pattern 106, and the second conductive layer pattern 108 are selectively formed. A so-called undercut process can be performed which selectively reduces the width by etching. The undercut process may be wet etching using an etchant capable of selectively removing the first conductive layer pattern 104, the inter-gate dielectric layer pattern 106, and the second conductive layer pattern 108. For example, when the first conductive layer pattern 104 and the second conductive layer pattern 108 are formed of a polysilicon layer, and the inter-gate dielectric layer pattern 106 is formed of an ONO layer, hydrofluoric acid (HF) A solution containing) may be used as an etchant. As a result of performing the undercut process, the first conductive layer pattern 104, the inter-gate dielectric layer pattern 106, and the second conductive layer pattern 108 are formed in the metal layer pattern 110 as shown in FIG. 2. ) And a reduced width compared to the capping layer pattern 112. Meanwhile, the undercut process may be optionally performed, and may be omitted in some cases.

Referring to FIG. 3, after performing the undercut process, a low temperature selective oxidation process 116 on the resultant product having the gate structure 114 is performed. In the present invention, the low temperature selective oxidation process 116 means an oxidation process performed at a temperature of 600 ℃ or less. In addition, the low temperature selective oxidation process 116 is a selective oxidation process performed under the condition that the oxide film is not formed on the exposed sidewall of the metal film pattern 110. In particular, when the metal film pattern 110 includes a tungsten film as described above, a low temperature selective oxidation process is required to prevent the exposed sidewall of the tungsten film from being oxidized. For this purpose, the low temperature selective oxidation process 116 is preferably a radical oxidation process using hydrogen radicals and active oxygen radicals contained in the plasma. As a result of performing the low temperature selective oxidation process 116, a leakage preventing insulating layer 118 covering sidewalls of the first conductive layer pattern 104 and the second conductive layer pattern 108 is formed. The leakage preventing insulating layer 118 may be a silicon oxide layer. In this case, the leakage preventing insulating layer 118 is an appropriate thickness to prevent the width of the gate structure 114 from excessively increasing, and is preferably formed to have a thickness of about 5 kPa to about 100 kPa. In addition, when the undercut process is performed as described above, it is possible to prevent the width of the gate structure 114 from being increased by the leakage preventing insulating film 118 in advance so that a subsequent interlayer insulating film can be easily formed. have. Since the low-temperature selective oxidation process 116 is performed at a temperature of 600 ° C. or less, an increase in the thickness of the inter-gate insulating layer 106 may be suppressed by Buzzbee while the leakage preventing layer 118 is formed.

Referring to FIG. 4, an insulating film for spacers conformally covering the gate structure 114 having the leakage preventing insulating film 118 is formed on the semiconductor substrate 100. The spacer insulating film may be formed of a silicon nitride film, and may be formed to a thickness of about 10 GPa to about 100 GPa. Thereafter, the spacer insulating layer is etched back to form a spacer 120 covering the sidewall of the gate structure 114 having the leakage preventing insulating layer 118. The spacer 120 together with the gate structure 114 forms a gate pattern of a flash memory device. The leakage preventing insulating layer 118 is provided as a control gate and the first conductive layer pattern 104 provided as a floating gate along their interface when the spacer 120 is in direct contact with the gate structure 114. It serves to prevent the leakage current from occurring between the second conductive film patterns 106. Thereafter, an additional oxidation process 122 may be performed on the resultant product having the spacers 120. The further oxidation process 122 may be called a gate reoxidation process. The additional oxidation process 122 is performed to heal the etching damage applied to the tunnel oxide layer 102 in the process of forming the spacer 120. In this case, the additional oxidation process 122 may be performed with a wider process margin than the low temperature selective oxidation process 116. That is, since the spacer 120 prevents oxidation of the metal layer pattern 110 and buzz beak of the inter-gate insulating layer 106, in a dry oxidation process using oxygen gas and a heat treatment furnace of oxygen and water vapor atmospheres. The wet oxidation process performed and the radical oxidation process using plasma can be applied without limitation. However, the additional oxidation step 122 is a radical oxidation step performed at 600 ° C. or lower like the low temperature selective oxidation step 116 in order to prevent excessive buzz big from occurring at the side of the tunnel oxide film 102. desirable.

5 to 10 are cross-sectional views illustrating a gate pattern forming method of a flash memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 5, a tunnel oxide film 302 is formed on the semiconductor substrate 300. The tunnel oxide layer 302 may be a thermal oxide layer. As illustrated in FIG. 1, the tunnel oxide layer 302 is formed to cover an active region defined by an isolation layer. The first conductive film line 304 is formed on the semiconductor substrate on which the tunnel oxide film 302 is formed. The first conductive layer line 304 may be formed by forming a polysilicon layer on the tunnel oxide layer 302 and patterning the polysilicon layer by performing a photolithography and etching process. In this case, the first conductive layer line 304 may be formed to have a line shape covering the active region. Thereafter, an inter-gate dielectric film 306, a second conductive film 308, a metal film 310, and a capping film 312 are sequentially formed on the semiconductor substrate having the first conductive film line 304. The inter-gate dielectric layer 306 may be formed of an ONO layer or a high dielectric layer. In this case, the high-k dielectric film is at least one film selected from the group consisting of aluminum oxide film (AlO), hafnium oxide film (HfO), hafnium silicon oxide film (HfSiO), hafnium aluminum oxide film (HfAlO), and tantalum oxide film (TaO). It can be formed as a laminated film by a combination of the two. The second conductive layer 308 may be formed of a polysilicon layer. In addition, the metal film 310 may be formed of a laminated film of a tungsten nitride film and a tungsten film. The capping layer 312 may be formed of a silicon nitride layer.

Referring to FIG. 6, the capping layer 312, the metal layer 310, the second conductive layer 308 and the first conductive layer line 304 may be exposed by performing a conventional photo and etching process. The inter-gate insulating film 306 is patterned. As a result, the preliminary gate structure 314 including the inter-gate insulating film pattern 306 ′, the second conductive film pattern 308 ′, the metal film pattern 310 ′, and the capping film pattern 312 ′ is formed. The preliminary gate structure 314 is formed to cross the first conductive film line 304 below. In this case, as illustrated in FIG. 6, an upper portion of the first conductive layer line 304 may be etched to a predetermined thickness.

Referring to FIG. 7, sidewalls of the second conductive layer pattern 308 and the inter-gate dielectric layer pattern 306 and exposed regions of the first conductive layer line 304 may be selectively etched to reduce their widths. A reducing undercut process can be performed. In this process, the upper region of the first conductive film line 304 may be etched, so that the first conductive film line 304 may have a further reduced thickness. Meanwhile, the undercut process may be optionally performed, and may be omitted in some cases.

Referring to FIG. 8, after performing the undercut process, a low temperature selective oxidation process 316 on the resultant product having the gate structure 314 is performed. The low temperature selective oxidation process 316 is preferably a radical oxidation process performed at a temperature of 600 ° C or less. As a result, a leakage preventing insulating layer 318 is formed to cover exposed regions of the first conductive layer line 304 and sidewalls of the second conductive layer pattern 308 '. The leakage preventing insulating layer 318 may be formed to have a thickness of about 5 kPa to about 100 kPa. In addition, since the detailed description of the low temperature selective oxidation process 316 has been described with reference to FIG. 3, it will be omitted below.

Referring to FIG. 9, a silicon nitride film conformally covering the resultant formed with the leakage preventing insulating film 318 is formed. The silicon nitride film may be formed to a thickness of about 10 GPa to about 100 GPa. Thereafter, the silicon nitride layer is etched back to form a spacer 320 covering the sidewall of the preliminary gate structure 314 having the leakage preventing insulating layer 318. Next, the leakage preventing insulating layer 318 and the first conductive layer line 304 (FIG. 8) are anisotropically etched using the capping layer pattern 312 ′ and the spacer 320 as an etching mask. As a result, a first conductive layer pattern 304 ′ overlapping the preliminary gate structure 314 and the spacer 320 is formed. The first conductive layer pattern 304 ′ forms a gate structure 314 ′ together with the preliminary gate structure 314.

Referring to FIG. 10, an additional oxidation process 322 is performed on the resultant product having the spacer 320. The further oxidation process 322 may be called a gate reoxidation process. The additional oxidation process 322 may be performed to heal the etch damage applied to the tunnel oxide layer 302 during anisotropic etching to form the first conductive layer pattern 304 ′. As a result, sidewall oxide layer 324 is formed to cover exposed sidewalls of the first conductive layer pattern 304 ′. The sidewall oxide layer 324 may be a silicon oxide layer. The additional oxidation process 322 is preferably a radical oxidation process performed at 600 ° C. or lower like the low temperature selective oxidation process 316 in order to prevent excessive buzz big from occurring at the side of the tunnel oxide film 302. . Subsequently, although not shown in the drawing, a process of forming an additional spacer covering the spacer 320 and the sidewall oxide layer 324 may be further performed. In this case, the additional spacer may be formed of a silicon nitride film.

As described above, according to the present invention, a leakage preventing insulating layer covering sidewalls of the polysilicon gates is formed through a low temperature selective oxidation process. Subsequently, by forming a spacer and performing a gate reoxidation process, it is possible to suppress a phenomenon in which the thickness of the inter-gate insulating layer is increased by Buzzvik. In addition, a leakage preventing insulating layer may be formed between the spacer and the polysilicon gates to prevent leakage current from occurring through an interface between the spacer and the polysilicon gates. Furthermore, the process margin of the gate reoxidation process may be improved by forming a leakage preventing insulating layer and a spacer which sequentially cover the sidewalls of the gate structure and performing a gate reoxidation process.

Claims (25)

Forming a gate structure including a first conductive layer pattern, an inter-gate dielectric layer pattern, and a second conductive layer pattern on the semiconductor substrate on which the tunnel oxide layer is formed, Performing a low temperature selective oxidation process on the resultant having the gate structure to form a leakage preventing insulating layer covering sidewalls of the first conductive pattern and the second conductive pattern; Forming a spacer covering a sidewall of the gate structure having the leakage preventing insulating layer. The method of claim 1, And the first conductive film pattern and the second conductive film pattern are formed of a polysilicon film. The method of claim 1, The gate structure may further include a metal layer pattern stacked on the second conductive layer pattern. The method of claim 3, wherein And the metal film pattern comprises a tungsten film. The method of claim 1, And the gate-to-gate dielectric layer pattern is formed of an ONO layer or a high dielectric layer. The method of claim 5, wherein The high-k dielectric layer may be formed of one or a combination of at least two selected from the group consisting of aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), and tantan oxide (TaO). The method of forming a gate pattern of a semiconductor device, characterized in that the laminated film. The method of claim 1, The low temperature selective oxidation process is a gate pattern forming method of a semiconductor device, characterized in that carried out at a temperature of less than 600 ℃. The method of claim 7, wherein The low temperature selective oxidation process is a gate pattern forming method of a semiconductor device, characterized in that the radical oxidation process using hydrogen radicals and oxygen radicals contained in the plasma. The method of claim 1, And the leakage preventing insulating layer is formed to have a thickness of about 5 GPa to about 100 GPa. The method of claim 1, And the spacer is formed of a silicon nitride film. The method of claim 1, Prior to performing the low temperature selective oxidation process, the gate pattern of the semiconductor device may further include selectively etching sidewalls of the first conductive layer pattern, the inter-gate dielectric layer pattern, and the second conductive layer pattern to reduce their widths. Formation method. The method of claim 1, After the formation of the spacers, further comprising performing an additional oxidation process on the resultant product having the spacers. The method of claim 12, The additional oxidation process is a gate pattern forming method of a semiconductor device, characterized in that the radical oxidation process using a plasma. Forming a first conductive film line on the semiconductor substrate on which the tunnel oxide film is formed, An inter-gate insulating film and a second conductive film are formed on the semiconductor substrate having the first conductive film line, The second conductive film and the inter-gate insulating film are patterned to expose the first conductive film line, thereby forming a preliminary gate structure including an inter-gate insulating film pattern and a second conductive film pattern and crossing the first conductive film line. and, Performing a low temperature selective oxidation process on the resultant having the preliminary gate structure to form a leakage preventing insulating layer covering exposed areas of the first conductive layer line and sidewalls of the second conductive layer pattern, Forming a spacer covering a sidewall of the preliminary gate structure, Patterning the first conductive layer line to form a first conductive layer pattern overlapping the lower portion of the preliminary gate structure and the spacer; A method of forming a gate pattern of a semiconductor device comprising performing an additional oxidation process on the resultant having the first conductive film pattern. The method of claim 14, And the first conductive film pattern and the second conductive film pattern are formed of a polysilicon film. The method of claim 14, Forming a metal film on the second conductive film, wherein the metal film is patterned together with the second conductive film and the inter-gate insulating film. The method of claim 16, And said metal film comprises a tungsten film. The method of claim 14, And the gate-to-gate dielectric layer is formed of an ONO layer or a high dielectric layer. The method of claim 18, The high-k dielectric layer may be formed of one or a combination of at least two selected from the group consisting of aluminum oxide (AlO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), and tantan oxide (TaO). The method of forming a gate pattern of a semiconductor device, characterized in that the laminated film. The method of claim 14, The low temperature selective oxidation process is a gate pattern forming method of a semiconductor device, characterized in that carried out at a temperature of less than 600 ℃. The method of claim 20, The low temperature selective oxidation process is a gate pattern forming method of a semiconductor device, characterized in that the radical oxidation process using hydrogen radicals and oxygen radicals contained in the plasma. The method of claim 14, And the leakage preventing insulating layer is formed to have a thickness of about 5 GPa to about 100 GPa. The method of claim 14, And the spacer is formed of a silicon nitride film. The method of claim 14, Prior to performing the low temperature selective oxidation process, sidewalls of the second conductive layer pattern and the inter-gate dielectric layer pattern, and exposed regions of the first conductive layer line may be selectively etched to reduce the width of the preliminary gate structure. The method of forming a gate pattern of a semiconductor device further comprising. The method of claim 14, The additional oxidation process is a gate pattern forming method of a semiconductor device, characterized in that the radical oxidation process using a plasma.

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