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KR20040001909A - Method for forming gate electrode of semiconductor device - Google Patents

Method for forming gate electrode of semiconductor device Download PDF

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Publication number
KR20040001909A
KR20040001909A KR1020020037243A KR20020037243A KR20040001909A KR 20040001909 A KR20040001909 A KR 20040001909A KR 1020020037243 A KR1020020037243 A KR 1020020037243A KR 20020037243 A KR20020037243 A KR 20020037243A KR 20040001909 A KR20040001909 A KR 20040001909A
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forming
film
gate electrode
conductive film
pattern
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KR1020020037243A
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이해정
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주식회사 하이닉스반도체
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Publication of KR20040001909A publication Critical patent/KR20040001909A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자 제조방법에 관한 것으로, 특히 완충산화막 형성에 따른 텅스텐막의 이상 산화를 방지하기에 적합한 반도체소자의 게이트전극 형성방법을 제공하기 위한 것으로, 이를 위해 본 발명은, 실리콘을 함유하는 기판 상에 게이트절연막용 절연막과 실리콘을 함유하는 게이트전극용 제1전도막과 제2전도막 및 하드마스크용 절연막을 적층하는 단계; 상기 하드마스크 상에 게이트전극 패턴 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 상기 하드마스크용 절연막과 상기 제2전도막과 제1전도막 및 상기 절연막을 차례로 식각하여 게이트절연막/제1전도막패턴/제2전도막패턴/하드마스크의 적층 구조를 갖는 게이트전극 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 및 상기 게이트절연막의 식각 손상을 보상하기 위해 플라즈마를 이용한 선택적 산화공정을 통해 제1전도막패턴과 상기 제2전도막패턴 및 상기 기판 표면을 따라 완충산화막을 형성하는 단계를 포함하는 반도체소자의 게이트전극 형성방법을 제공한다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to provide a method for forming a gate electrode of a semiconductor device suitable for preventing abnormal oxidation of a tungsten film due to the formation of a buffer oxide film. Stacking an insulating film for a gate insulating film and a first conductive film for a gate electrode, a second conductive film, and an insulating film for a hard mask on the substrate; Forming a photoresist pattern for forming a gate electrode pattern on the hard mask; Etching the photoresist pattern as an etch mask, the hard mask insulating film, the second conductive film, the first conductive film, and the insulating film are sequentially etched to stack a gate insulating film, a first conductive film pattern, a second conductive film pattern, and a hard mask. Forming a gate electrode pattern having a structure; Removing the photoresist pattern; And forming a buffer oxide film along the first conductive film pattern, the second conductive film pattern, and the surface of the substrate through a selective oxidation process using plasma to compensate for etch damage of the gate insulating film. Provided is an electrode forming method.

Description

반도체소자의 게이트전극 형성방법{Method for forming gate electrode of semiconductor device}Method for forming gate electrode of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자의 게이트전극 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode of a semiconductor device.

반도체 장치에 고속의 동작 속도가 요구됨에 따라 게이트, 드레인(Drain) 또는 소오스(Source)에 접촉하는 전극으로 보다 높은 전도도를 가지는 물질이 이용되고 있다.As a high speed of operation is required for semiconductor devices, a material having higher conductivity is used as an electrode contacting a gate, a drain, or a source.

예를 들어, 미합중국 특허 5,814,537호(Method of forming transistor electrodes from directionally depositedsilicide, Jer-shen Maa, etc., 1998/9/29.) 또는 미합중국 특허 5,194,403호(Method for the making of the electrodemetalization of a transistors, Sylvain Delage, etc., 1993/4/16)에서와 같이 실리사이드 또는 금속 등의 재질을 게이트 또는 전극으로 이용하고 있다. 또한, 고속의 동작 속도를 위해서, 미합중국 특허 5,804,499호(Prevention of abnormalWSiX oxidation by in-situ amorphous silicon deposition, Christine Dehm, etc., 1998/9/8.)에서는 텅스텐 실리사이드(WSix)를 게이트로 이용하고 있다. 또한, 텅스텐 실리사이드의 산화를 방지하기 위해서 비정질 실리콘(Amorphoussilicon)으로 텅스텐 실리사이드를 보호하는 것을 기재하고 있다.For example, US Pat. No. 5,814,537 (Method of forming transistor electrodes from directionally depositedsilicide, Jer-shen Maa, etc., 1998/9/29.) Or US Pat. No. 5,194,403 (Method for the making of the electrodemetalization of a transistors, As in Sylvain Delage, etc., 1993/4/16), a material such as silicide or metal is used as a gate or an electrode. In addition, for high speed of operation, US Pat. No. 5,804,499 (Prevention of abnormal WSiX oxidation by in-situ amorphous silicon deposition, Christine Dehm, etc., 1998/9/8.) Uses tungsten silicide (WSix) as a gate. have. It also describes protecting tungsten silicide with amorphous silicon in order to prevent oxidation of tungsten silicide.

한편, 게이트를 형성하기 위해서는 반도체 기판 상에 게이트산화막 및 도전층을 적층한 후, 도전층을 요구되는 스케일(Scale)로 패터닝하는 공정이 필수적이다. 이러한 패터닝 공정(패턴 형성 공정)에서 하부의 게이트산화막은 손상(Damage)을 입게된다. 특히, 게이트산화막의 에지(Edge) 부분 즉, 패터닝된 도전층의 측벽에 인접하는 부위에 이러한 손상은 집중될 수 있다. 이러한 손상은 트랜지스터의 특성 저하를 유발할 수 있으므로, 열처리 등을 통하여 회복(Curing)시키는 공정을수반한다.In order to form a gate, a process of stacking a gate oxide film and a conductive layer on a semiconductor substrate and then patterning the conductive layer to a required scale is essential. In this patterning process (pattern forming process), the lower gate oxide film is damaged. In particular, such damage may be concentrated in the edge portion of the gate oxide layer, that is, the portion adjacent to the sidewall of the patterned conductive layer. Such damage may cause deterioration of transistor characteristics, and thus involves a process of recovering through heat treatment or the like.

도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 게이트전극 형성공정을 도시한 단면도로서, 이를 참조하여 상세히 후술한다.1A to 1D are cross-sectional views illustrating a gate electrode forming process of a semiconductor device according to the related art, which will be described later in detail.

먼저 도 1a에 도시된 바와 같이, 반도체소자를 이루기 위한 여러 요소가 형성된 기판(10) 상에 산화막계열의 게이트절연막(11a)과 게이트전극의 전도막으로 폴리실리콘막(12a)과 텅스텐막(13a) 그리고 게이트전극 하드마스크용 질화막(14a)을 차례로 적층한 후, 질화막(14a) 상에 게이트전극 패턴 형성을 위한 포토레지스트 패턴(15)을 형성한다.First, as shown in FIG. 1A, the polysilicon film 12a and the tungsten film 13a are formed on the substrate 10 on which various elements for forming a semiconductor device are formed, as the conductive film of the gate insulating film 11a and the gate electrode. Next, the nitride film 14a for the gate electrode hard mask is sequentially stacked, and the photoresist pattern 15 for forming the gate electrode pattern is formed on the nitride film 14a.

이어서 도 1b에 도시된 바와 같이, 포토레지스트 패턴(15)을 식각마스크로 한 선택적 식각 공정으로 질화막(14a)과 텅스텐막(13a)과 폴리실리콘막(12a) 및 산화막(11a)을 차례로 식각하여 게이트절연막(11b)과 폴리실리콘막(12b)과 텅스텐막(13b)이 적층된 게이트전극용 전도막과 하드마스크(14b)가 적층된 구조의 게이트전극 패턴을 형성한다. 계속해서, 포토레지스트 패턴(15)을 제거한다.Subsequently, as shown in FIG. 1B, the nitride film 14a, the tungsten film 13a, the polysilicon film 12a, and the oxide film 11a are sequentially etched by a selective etching process using the photoresist pattern 15 as an etching mask. A gate electrode pattern having a structure in which the gate insulating film 11b, the polysilicon film 12b, the tungsten film 13b, and the conductive film for the gate electrode and the hard mask 14b are stacked is formed. Subsequently, the photoresist pattern 15 is removed.

한편, 전술한 패턴 형성을 위한 식각 공정은 플라즈마를 이용한 건식 식각으로서 이때, 하부의 게이트절연막(11b) 또한 상기 건식 식각 방법에 의해서 침식되어 손상된다.On the other hand, the etching process for forming the pattern is a dry etching using a plasma, at this time, the lower gate insulating film 11b is also eroded and damaged by the dry etching method.

또한, 도면에 도시되지는 않았지만, 텅스텐막(13a)과 폴리실리콘막(12a) 식각시 소정량의 폴리머가 발생하여 포토레지스트 및 식각된 폴리실리콘막(12b)과 텅스텐막(13b) 표면에 잔류하게 된다.Although not shown in the drawings, a predetermined amount of polymer is generated during the etching of the tungsten film 13a and the polysilicon film 12a and remains on the surface of the photoresist and the etched polysilicon film 12b and the tungsten film 13b. Done.

따라서, 묽은 불산용액을 사용하여 폴리머(도시하지 않음)를 습식제거한다.Thus, a thin hydrofluoric acid solution is used to wet remove the polymer (not shown).

한편, 전술한 게이트절연막(11b)의 손상을 회복시키기 위해서 도 1c에 도시된 바와 같이, 산화 분위기의 열처리를 수행하면 폴리실리콘막(12b) 측벽 표면이 산화되어 완충산화막(16)이 형성된다. 이에 따라, 손상된 게이트절연막(11b)의 손상, 특히, 패터닝된 폴리실리콘막(12b)의 측벽과 접하는 에지 부위의 손상이 회복된다.Meanwhile, as shown in FIG. 1C, in order to recover the damage of the gate insulating film 11b described above, when the heat treatment in an oxidizing atmosphere is performed, the sidewall surface of the polysilicon film 12b is oxidized to form the buffer oxide film 16. As a result, damage to the damaged gate insulating film 11b, in particular, damage to the edge portion in contact with the sidewall of the patterned polysilicon film 12b is recovered.

전술한 산화 분위기의 열처리는 통상적인 선택적 산화(Selective oxidation) 공정으로서, 질화막을 주로 이용하는 하드마스크(14b)에서는 질화막의 특성상 산화가 일어나지 않는 것을 이용하여 실리콘을 포함하는 폴리실리콘막(12b)과 텅스텐막(13b) 에서만 선택적으로 산화가 발생하도록 열처리를 통해 형성하는 것으로, 후속 질화막계열의 스페이서와 기판(10)과의 스트레스를 완화시켜 반도체소자의 리프레쉬 특성을 향상시키는 역할을 한다.The above-mentioned heat treatment in an oxidizing atmosphere is a conventional selective oxidation process. In the hard mask 14b mainly using a nitride film, the silicon-containing polysilicon film 12b and tungsten are used in that the oxidation does not occur due to the characteristics of the nitride film. It is formed by heat treatment to selectively generate oxidation only in the film 13b, and serves to improve the refresh characteristics of the semiconductor device by relieving stress between the spacer of the subsequent nitride film series and the substrate 10.

도 1d는 전술한 바와 같이 게이트전극 패턴이 형성된 프로파일을 따라 질화막 등의 얇은 스페이서(17)를 형성한 것이다.1D is a thin spacer 17 such as a nitride film formed along the profile in which the gate electrode pattern is formed as described above.

스페이서(17)는 후속 자기정렬콘택(Self Align Contact; 이하 SAC라 함) 공정시 층간절연막인 산화막과의 식각선택비를 갖도록 하여 SAC 식각 프로파일을 얻을 수 있도록 하며, 하드마스크(14b)의 손실을 방지하기 위해 형성한다.The spacer 17 has an etch selectivity with an oxide film, which is an interlayer insulating film, in a subsequent self-aligned contact (SAC) process, so as to obtain an SAC etch profile, and to reduce the loss of the hard mask 14b. To prevent form.

한편, 전술한 완충산화막 형성시 500℃ 이상의 온도에서 텅스텐막의 비정상 산화(18)가 발생할 가능성이 크다는 문제점이 있다.On the other hand, there is a problem that abnormal oxidation 18 of the tungsten film is likely to occur at a temperature of 500 ° C. or higher when the above-mentioned buffer oxide film is formed.

상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 완충산화막 형성에 따른 텅스텐막의 이상 산화를 방지하기에 적합한 반도체소자의 게이트전극 형성방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device suitable for preventing abnormal oxidation of the tungsten film according to the buffer oxide film formation.

도 1a 내지 도 1d는 종래기술에 따른 게이트전극 형성 공정을 도시한 단면도.1A to 1D are cross-sectional views showing a gate electrode forming process according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 게이트전극 형성 공정을 도시한 단면도.2A to 2D are cross-sectional views illustrating a gate electrode forming process according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 기판21b : 게이트절연막20: substrate 21b: gate insulating film

22b : 제1전도막패턴23b : 제2전도막패턴22b: first conductive film pattern 23b: second conductive film pattern

24b : 하드마스크26 : 완충산화막24b: hard mask 26: buffer oxide film

27 : 스페이서27: spacer

상기와 같은 문제점을 해결하기 위해 본 발명은, 실리콘을 함유하는 기판 상에 게이트절연막용 절연막과 실리콘을 함유하는 게이트전극용 제1전도막과 제2전도막 및 하드마스크용 절연막을 적층하는 단계; 상기 하드마스크 상에 게이트전극 패턴 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 상기 하드마스크용 절연막과 상기 제2전도막과 제1전도막 및 상기 절연막을 차례로 식각하여 게이트절연막/제1전도막패턴/제2전도막패턴/하드마스크의 적층 구조를 갖는 게이트전극 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 및 상기 게이트절연막의 식각 손상을 보상하기 위해 플라즈마를 이용한 선택적 산화공정을 통해 제1전도막패턴과 상기 제2전도막패턴 및 상기 기판 표면을 따라 완충산화막을 형성하는 단계를 포함하는 반도체소자의 게이트전극 형성방법을 제공한다.In order to solve the above problems, the present invention comprises the steps of: laminating an insulating film for a gate insulating film, a first conductive film for a gate electrode containing silicon and a second conductive film and an insulating film for a hard mask on a substrate containing silicon; Forming a photoresist pattern for forming a gate electrode pattern on the hard mask; Etching the photoresist pattern as an etch mask, the hard mask insulating film, the second conductive film, the first conductive film, and the insulating film are sequentially etched to stack a gate insulating film, a first conductive film pattern, a second conductive film pattern, and a hard mask. Forming a gate electrode pattern having a structure; Removing the photoresist pattern; And forming a buffer oxide film along the first conductive film pattern, the second conductive film pattern, and the surface of the substrate through a selective oxidation process using plasma to compensate for etch damage of the gate insulating film. Provided is an electrode forming method.

본 발명은 텅스텐 등의 전도막과 폴리실리콘이 적층된 게이트전극 패터닝 후, 식각에 의한 게이트절연막의 데미지를 보상하고, 질화막 스페이서와의 기판과의 스트레스를 완화시키기 위한 완충산화막 형성 공정시 플라즈마를 이용한 저온공정으로 실시하여 텅스텐 등 전도막의 이상 산화를 방지하는 것을 특징으로 한다.According to the present invention, after a gate electrode patterning in which a conductive film such as tungsten and polysilicon are laminated, plasma is used in a buffer oxide film forming process to compensate for damage of the gate insulating film by etching and to relieve stress from the substrate with the nitride spacer. The low temperature process is used to prevent abnormal oxidation of the conductive film such as tungsten.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도 2a 내지 도 2d를 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to enable those skilled in the art to more easily implement the present invention.

도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체소자의 게이트전극 형성 공정을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a gate electrode forming process of a semiconductor device according to an embodiment of the present invention.

도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 게이트전극 형성공정을 도시한 단면도로서, 이를 참조하여 상세히 후술한다.2A to 2D are cross-sectional views illustrating a gate electrode forming process of a semiconductor device according to the present invention, which will be described later in detail.

먼저 도 2a에 도시된 바와 같이, 반도체소자를 이루기 위한 여러 요소가 형성된 기판(20) 상에 산화막계열의 게이트절연막(21a)과 게이트전극의 전도막으로 폴리실리콘막(22a)과 텅스텐막(23a) 그리고 게이트전극 하드마스크용 질화막(24a)을 차례로 적층한 후, 질화막(24a) 상에 게이트전극 패턴 형성을 위한 포토레지스트 패턴(25)을 형성한다.First, as shown in FIG. 2A, the polysilicon film 22a and the tungsten film 23a are formed on the substrate 20 on which various elements for forming a semiconductor device are formed, as the conductive film of the gate insulating film 21a and the gate electrode. Next, the nitride film 24a for the gate electrode hard mask is sequentially stacked, and then the photoresist pattern 25 for forming the gate electrode pattern is formed on the nitride film 24a.

이어서 도 2b에 도시된 바와 같이, 포토레지스트 패턴(25)을 식각마스크로 한 선택적 식각 공정으로 질화막(24a)과 텅스텐막(23a)과 폴리실리콘막(22a) 및 게이트절연막(21a)을 차례로 식각하여 게이트절연막(21b)과 폴리실리콘막(22b)과 텅스텐막(23b)이 적층된 게이트전극용 전도막과 하드마스크(24b)가 적층된 구조의 게이트전극 패턴을 형성한다. 계속해서, 포토레지스트 패턴(25)을 제거한다.Subsequently, as shown in FIG. 2B, the nitride film 24a, the tungsten film 23a, the polysilicon film 22a, and the gate insulating film 21a are sequentially etched by a selective etching process using the photoresist pattern 25 as an etching mask. As a result, a gate electrode pattern having a structure in which the gate electrode conductive film in which the gate insulating film 21b, the polysilicon film 22b and the tungsten film 23b are stacked, and the hard mask 24b are stacked is formed. Subsequently, the photoresist pattern 25 is removed.

한편, 전술한 패턴 형성을 위한 식각 공정은 플라즈마를 이용한 건식 식각으로서 이때, 하부의 게이트절연막(21b) 또한 상기 건식 식각 방법에 의해서 침식되어 손상된다.On the other hand, the etching process for forming the pattern is a dry etching using a plasma, at this time, the lower gate insulating film 21b is also eroded and damaged by the dry etching method.

또한, 도면에 도시되지는 않았지만, 텅스텐막(23a)과 폴리실리콘막(22a) 식각시 소정량의 폴리머가 발생하여 포토레지스트 및 식각된 폴리실리콘막(22b)과 텅스텐막(23b) 표면에 잔류하게 된다.Although not shown in the drawings, a predetermined amount of polymer is generated when the tungsten film 23a and the polysilicon film 22a are etched to remain on the surface of the photoresist and the etched polysilicon film 22b and the tungsten film 23b. Done.

따라서, 묽은 불산용액을 사용하여 폴리머(도시하지 않음)를 습식제거한다.Thus, a thin hydrofluoric acid solution is used to wet remove the polymer (not shown).

한편, 전술한 게이트절연막(21b)의 손상을 회복시키기 위해서 도 2c에 도시된 바와 같이, 플라즈마를 이용한 선택적 산화 공정을 통해 폴리실리콘막(22b) 텅스텐막(23b)의 측벽 표면과 기판(20)이 산화되어 완충산화막(26)이 형성된다. 이에 따라, 손상된 게이트절연막(21b)의 손상, 특히, 패터닝된 폴리실리콘막(22b)의 측벽과 접하는 에지 부위의 손상이 회복된다.Meanwhile, to recover the damage of the gate insulating film 21b described above, as shown in FIG. 2C, the sidewall surface of the tungsten film 23b and the substrate 20 of the polysilicon film 22b are subjected to a selective oxidation process using plasma. This oxidation causes a buffer oxide film 26 to be formed. As a result, damage to the damaged gate insulating film 21b, in particular, damage to the edge portion in contact with the sidewall of the patterned polysilicon film 22b is recovered.

선택적 산화 공정에서, 본 발명은 10mTorr ∼ 1Torr의 압력 및 200℃ ∼ 400℃의 온도 하에서 실시하므로, 종래의 500℃ 이상의 온도에서 실시하던 공정에 의헤 텅스텐막(23b) 에서 발생하던 이상 산화를 방지할 수 있다.In the selective oxidation process, the present invention is carried out under a pressure of 10 mTorr to 1 Torr and a temperature of 200 ° C to 400 ° C, thereby preventing abnormal oxidation that has occurred in the tungsten film 23b by a process performed at a conventional temperature of 500 ° C or more. Can be.

이 때, O2가스만을 포함하거나 O2가스에 He, Ne, Ar 또는 Xe 등의 비활성가스 또는 실란(SiH4)가스를 포함하는 플라즈마를 이용고, 마이크로파(Microwave), ECR(Electron Cyclotron Resonance) 또는 ICP(Inductive Coupled Plasma) 등의 방식을 이용한 장비를 이용한다.At this time, and it includes only the O 2 gas or a plasma of the O 2 gas containing the inert gas, or silane (SiH 4) gas, such as He, Ne, Ar or Xe, microwave (Microwave), ECR (Electron Cyclotron Resonance) Or equipment using a method such as inductive coupled plasma (ICP) is used.

한편, 전술한 묽은 불산용액을 이용한 습식세정이 아닌 건식세정을 이용할수도 있는 바, 이 경우에는 완충산화막(26)을 형성할 마이크로파, ECR 또는 ICP 장비로 옮긴 후, O2와 불소(F)계 가스를 포함하는 플라즈마를 이용하여 세정한 후, 인-시튜(In-situ) 공정으로 완충산화막(26) 형성 공정을 실시한다.On the other hand, dry cleaning may be used instead of wet cleaning using the above-described diluted hydrofluoric acid solution. In this case, after transferring to microwave, ECR or ICP equipment to form the buffer oxide film 26, O 2 and fluorine (F) -based After washing with a plasma containing gas, a buffer oxide film 26 is formed by an in-situ process.

전술한 선택적 산화 공정은 질화막을 주로 이용하는 하드마스크(24b)에서는 질화막의 특성상 산화가 일어나지 않는 것을 이용하여 실리콘을 포함하는 폴리실리콘막(22b)과 텅스텐막(23b) 및 기판(20) 에서만 선택적으로 산화가 발생하도록 하여 완충산화막(26)을 형성하는 것으로, 후속 질화막계열의 스페이서와 기판(20)과의 열팽창률 차이에 의한 물리적 스트레스를 완화시켜 반도체소자의 리프레쉬 특성을 향상시키는 역할을 한다.The selective oxidation process described above is selectively performed only on the polysilicon film 22b, tungsten film 23b, and the substrate 20 containing silicon, by which the oxidation does not occur in the hard mask 24b mainly using the nitride film. The oxidation of the buffer layer 26 is performed to form a buffer oxide layer 26. The buffer oxide layer 26 serves to improve the refresh characteristics of the semiconductor device by relieving physical stress caused by the difference in thermal expansion between the spacer of the nitride layer series and the substrate 20. FIG.

도 2d는 전술한 바와 같이 게이트전극 패턴이 형성된 프로파일을 따라 질화막 등의 얇은 스페이서(27)를 형성한 것이다.2D is a thin spacer 27 such as a nitride film formed along the profile in which the gate electrode pattern is formed as described above.

스페이서(27)는 후속 SAC 공정시 층간절연막인 산화막과의 식각선택비를 갖도록 하여 SAC 식각 프로파일을 얻을 수 있도록 하며, 하드마스크(24b)의 손실을 방지하기 위한 것이다.The spacer 27 may have an etching selectivity with an oxide film, which is an interlayer insulating film, in a subsequent SAC process to obtain an SAC etching profile, and to prevent loss of the hard mask 24b.

전술한 바와 같이 이루어지는 본 발명은. 기판과 스페이서 사이에 완충산화막을 형성하여 스트레스를 완화시켜 누설전류 특성을 향상시킴은 물론, 게이트전극 패턴 형성에 따른 게이트절연막의 식각 데미지를 완충산화막을 통해 완화시키면서, 저온 공정을 통해 완충산화막을 형성할 수 있어 텅스텐의 이상 산화를 방지할 수있음을 실시예를 통해 알아 보았다.The present invention made as described above. A buffer oxide film is formed between the substrate and the spacer to relieve stress to improve leakage current characteristics, and to reduce the etching damage of the gate insulating film due to the formation of the gate electrode pattern through the buffer oxide film, thereby forming a buffer oxide film through a low temperature process. It can be seen through the examples that it is possible to prevent abnormal oxidation of tungsten.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은, 게이트절연막 식각 보상 및 리프레쉬 특성 향상을 위해 형성하는 완충산화막 형성시 게이트 전극으로 사용되는 텅스텐막의 이상 산화를 방지할 수 있어, 궁극적으로 반도체소자의 수율과 특성 향상을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above can prevent abnormal oxidation of the tungsten film used as the gate electrode when forming the buffer oxide film formed to improve the gate insulation film etching compensation and refresh characteristics, and ultimately improve the yield and characteristics of the semiconductor device. You can expect an excellent effect.

Claims (8)

실리콘을 함유하는 기판 상에 게이트절연막용 절연막과 실리콘을 함유하는 게이트전극용 제1전도막과 제2전도막 및 하드마스크용 절연막을 적층하는 단계;Stacking an insulating film for a gate insulating film, a first conductive film for a gate electrode containing silicon, a second conductive film and an insulating film for a hard mask on a substrate containing silicon; 상기 하드마스크 상에 게이트전극 패턴 형성을 위한 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern for forming a gate electrode pattern on the hard mask; 상기 포토레지스트 패턴을 식각마스크로 상기 하드마스크용 절연막과 상기 제2전도막과 제1전도막 및 상기 절연막을 차례로 식각하여 게이트절연막/제1전도막패턴/제2전도막패턴/하드마스크의 적층 구조를 갖는 게이트전극 패턴을 형성하는 단계;Etching the photoresist pattern as an etch mask, the hard mask insulating film, the second conductive film, the first conductive film, and the insulating film are sequentially etched to stack a gate insulating film, a first conductive film pattern, a second conductive film pattern, and a hard mask. Forming a gate electrode pattern having a structure; 상기 포토레지스트 패턴을 제거하는 단계; 및Removing the photoresist pattern; And 상기 게이트절연막의 식각 손상을 보상하기 위해 플라즈마를 이용한 선택적 산화공정을 통해 제1전도막패턴과 상기 제2전도막패턴 및 상기 기판 표면을 따라 완충산화막을 형성하는 단계Forming a buffer oxide film along the first conductive film pattern, the second conductive film pattern, and the substrate surface through a selective oxidation process using plasma to compensate for the etching damage of the gate insulating film; 를 포함하는 반도체소자의 게이트전극 형성방법.Gate electrode forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 완충산화막을 형성하는 단계는,Forming the buffer oxide film, 10mTorr 내지 1Torr의 압력 및 200℃ 내지 400℃의 온도 하에서 실시하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.A method of forming a gate electrode of a semiconductor device, characterized in that carried out under a pressure of 10mTorr to 1Torr and a temperature of 200 ℃ to 400 ℃. 제 2 항에 있어서,The method of claim 2, 상기 완충산화막을 형성하는 단계는,Forming the buffer oxide film, O2가스만을 포함하거나 O2가스에 비활성가스 또는 실란가스를 포함하는 플라즈마를 이용하여 마이크로파, ECR 또는 ICP 중 어느 하나의 방식을 이용하는 장비에서 실시하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.Including only the O 2 gas or a plasma comprising an inert gas or a silane gas to O 2 gas microwave, ECR, or the gate electrode forming method of a semiconductor device, characterized in that for performing the equipment using any of the methods of the ICP. 제 1 항에 있어서,The method of claim 1, 상기 포토레지스트 패턴을 제거 후, 상기 식각에 따른 잔류물을 제거하기 위해 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.And removing the photoresist pattern, followed by cleaning to remove residues due to the etching. 제 4 항에 있어서,The method of claim 4, wherein 상기 세정하는 단계에서 묽은 불산용액을 사용하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.The method of forming a gate electrode of a semiconductor device, characterized in that to use a dilute hydrofluoric acid solution in the cleaning step. 제 4 항에 있어서,The method of claim 4, wherein 상기 세정하는 단계에서 O2및 F계 가스의 플라즈마를 사용하며, 이 때 마이크로파, ECR 또는 ICP 중 어느 하나의 방식을 이용하는 장비에서 상기 완충산화막을 형성하는 단계와 인-시튜로 실시하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.In the cleaning step using a plasma of O 2 and F-based gas, at this time, the step of forming the buffer oxide film in the equipment using any one method of microwave, ECR or ICP and in-situ A method of forming a gate electrode of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 제1전도막은 폴리실리콘을 포함하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.The first conductive film is a method of forming a gate electrode of a semiconductor device, characterized in that it comprises polysilicon. 제 1 항에 있어서,The method of claim 1, 상기 제2전도막은 텅스텐을 포함하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.The second conductive film is a gate electrode forming method of a semiconductor device characterized in that it comprises tungsten.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100615585B1 (en) * 2004-09-09 2006-08-25 삼성전자주식회사 Gate pattern formation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100615585B1 (en) * 2004-09-09 2006-08-25 삼성전자주식회사 Gate pattern formation method of semiconductor device

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