KR20060018730A - Method for manufacturing of array substrate and a array substrate thereof - Google Patents

Abstract

 Provided are a method of manufacturing an array substrate and an array substrate thereof to prevent the risk of static electricity. The array substrate has a plurality of data wires, an electrostatic dispersion resistor, and a first array inspection unit. The data lines are formed in the first direction, and the electrostatic dissipation resistor connects the adjacent first data line and the second data line to dissipate static electricity introduced from the outside. The array inspecting unit applies the test signal to the data lines to perform array inspection. Accordingly, by forming and distributing an electrostatic dissipation resistor between the data lines, it is possible to prevent the risk of static electricity flowing from the outside.

Static Dissipation Resistor, Data Wiring, 2G2D

Description

A manufacturing method of an array substrate and an array substrate thereof {METHOD FOR MANUFACTURING OF ARRAY SUBSTRATE AND A ARRAY SUBSTRATE THEREOF}

1 is a schematic plan view of a mother substrate according to an embodiment of the present invention.

FIG. 2 is an enlarged view illustrating a portion of the mother substrate of FIG. 1. FIG.

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

4A to 4D are process diagrams for describing a method of manufacturing an array substrate.

5 is an enlarged partial view of a portion of a mother substrate according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

200: mother substrate 100: array substrate

220: first array inspection unit 211: first static dispersion wiring

221,222: first array test pad 223,224: first array test wiring

250: electrostatic dispersion resistance

The present invention relates to a method for manufacturing an array substrate and an array substrate thereof, and more particularly, to a method for manufacturing an array substrate and an array substrate thereof for preventing the risk of static electricity.

In general, a liquid crystal display panel includes an array substrate, an upper substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the upper substrate. The array substrate has a pixel area and a signal application area.

The pixel area may include a data line extending in a first direction, a scan line extending in a second direction and orthogonal to the data line, and a pixel electrode connected to the scan line and the data line. And a first driving chip pad on which a driving chip for applying a signal is mounted, and a second driving chip pad on which a driving chip for applying a scan signal to the scan wiring is mounted.

The array substrate is formed of a plurality of display cells on a mother substrate, and at the shortest end of the data lines, an electrostatic dispersion line for dispersing static electricity from the outside is formed. The static electricity distribution wiring is configured to open the static electricity distribution wiring and the data wirings through a separate open process during array inspection (2G2D) in which the data wirings are bundled into one parallel wiring. Perform the process. After such an open process, the data lines have a problem of being exposed to static electricity flowing from the outside as they are electrically floating.

 Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a method of manufacturing an array substrate for preventing the risk of static electricity.

Another object of the present invention is to provide the array substrate.

Data lines formed in a first direction, scan lines formed in a second direction, a first current electrode are connected to the data line, and a control electrode is provided. A method of manufacturing an array substrate including a switching element connected to a scan line, the method comprising: (a) a channel layer of an electrostatic dissipation resistor formed at an end of the data lines and connecting an adjacent first data line and a second data line; Forming a channel layer of the switching element; (b) first and second current electrodes of the electrostatic dispersion resistor connecting the data lines, the first data line and the second data line to a second metal layer, respectively; Forming a two current electrode; (c) forming a passivation layer on the first and second current electrodes of the electrostatic dispersion resistor and on the first and second current electrodes of the switching element; (d) removing a portion of the passivation layer to expose a first hole for separating the channel layer of the electrostatic dispersion resistor in response to the odd-numbered data line and the even-numbered data line, and exposing a second current electrode of the switching element; Forming a second hole; And (e) forming a pixel electrode connected to the second current electrode of the switching element through the second hole.                     

According to another aspect of the present invention, an array substrate includes a plurality of data lines formed in a first direction, and connecting adjacent first data lines and second data lines to prevent static electricity from outside. And a first array inspection unit formed in a second direction to apply the test signal to the data lines.

And a first static electricity distributing wire which is formed in a second direction on the outside of the data wires to disperse static electricity introduced from the outside, wherein one of the first data wire and the second data wire is one of the first static electricity distributing wires. It is connected to, and the other is characterized in that separated from the first electrostatic dispersion wiring.

According to the method of manufacturing the array substrate and the array substrate thereof, it is possible to prevent the static electricity flowing from the outside by forming and interconnecting the electrostatic dispersion resistors between the data lines.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic plan view of a mother board according to a first embodiment of the present invention.

Referring to FIG. 1, the mother substrate 200 includes a plurality of array substrates 100, first and second electrostatic scattering bars 211 and 212, first and second array inspection units 220 and 230, and cut lines. 270, and a plurality of electrostatic dispersion resistors (not shown) are formed between the first electrostatic dispersion wiring 211 and the first array inspection unit 220.

The array substrate 100 includes a pixel unit 110 and a first V / I inspection unit 120 and a second V / I inspection unit 130 outside the pixel unit 110.

The pixel unit 110 includes a plurality of data lines formed in a first direction, a plurality of scan lines formed in a second direction, a switching element TFT connected to the data lines and the scan line, and the switching element ( A first electrode (or pixel electrode) and a storage capacitor CST of the liquid crystal capacitor CLC connected to the TFT are included.

The first V / I inspection unit 120 includes a first V / I pad 121, a first V / I wiring 123, and a plurality of first driving chip pads 125. The first driving chip pad 125 is a pad for mounting the driving chip and is a set of data wires grouped by a predetermined unit. The first V / I pad 121 and the first V / I wiring 123 are separately formed for each of the first driving chip pads 125. The first V / I pad 121 has three pads grouped by 3n-2, 3n-1, 3n (where n = 1, 2, 3, ...) th wiring in accordance with the 3D method.

The second V / I inspection unit 130 includes a second V / I pad 131, a second V / I wiring 133, and a plurality of second driving chip pads 135. The second driving chip pad 135 is a pad on which the driving chip is mounted and is a set of grouped scan lines in a predetermined unit. The second V / I pad 131 and the second V / I wiring 133 are formed for each driving chip pad, respectively, and the second V / I pad 131 is 2n-1, 2n according to the 2G method (here, natural numbers where n = 1, 2, 3, ...

The first electrostatic scattering bar 211 distributes external static electricity directly into the plurality of data wires formed in the first direction on the array substrate 100. The first static electricity distribution wiring 211 is a single wiring formed in a second direction that bundles the plurality of data wires in parallel at the outermost portion of the first array inspecting unit 220 (1D method). Meanwhile, in order to facilitate 2G2D array inspection, the first array inspection wirings 223 and 224 and the first electrostatic dispersion wiring 211 are opened through an open process.

The electrostatic dissipation resistor (not shown) is formed between the plurality of data lines electrically floating through the open process. Hereinafter, a detailed description will be given with reference to FIGS. 2 to 4D.

The second static electricity distribution line 212 prevents external static electricity from directly flowing into the plurality of scan lines formed in the second direction on the array substrate 100. The second static electricity distribution wiring 212 is a single wiring formed in a first direction to bundle the plurality of scan wirings in parallel at the outermost portion of the second array inspection unit 230 (1G method). In order to facilitate the 2G2D array inspection, the second array inspection wiring 233 and 234 and the second electrostatic dispersion wiring 212 are opened through an open process.

The first array inspector 220 receives a test signal that inspects an electrical operation state of a plurality of data lines formed on the array substrate 100. The first array inspection unit 220 includes first array inspection pads 221 and 222 and first array inspection wires 223 and 224.

The first array test pads 221 and 222 include pads 221 for applying a first test signal to odd-numbered data lines and pads 222 for applying a second test signal to even-numbered data lines in a 2D manner. The first array test wirings 223 and 224 also include a wiring 223 connected to an odd-numbered data line and a wiring 224 connected to an even-numbered data line.

The second array inspection unit 230 is applied with a test signal for inspecting an electrical operation state of the plurality of scan lines formed on the array substrate 100. The second array tester 230 includes second array test pads 231 and 232 and second array test wirings 233 and 234.

The second array test pads 231 and 232 include a pad 231 for applying the first test signal to the odd-numbered scan line and a pad 232 for applying the second test signal to the even-numbered scan line according to the 2G method. The second array test wirings 233 and 234 also include a wiring 233 connected to the odd-numbered scan wiring and a wiring 234 connected to the even-numbered scan wiring.

FIG. 2 is an enlarged view illustrating a portion of the mother substrate of FIG. 1. FIG.

1 and 2, the mother substrate 200 includes a first region IR and a second region PR. A first array inspection interface unit is formed in the first region IR to which a test signal for inspecting an electrical operation state of a plurality of data lines formed in a first direction is formed, and the plurality of regions are formed in the second region PR. A pixel portion including switching elements 170 connected to the data lines of the pixel and pixel electrodes 190 connected to the switching elements 170 is formed.

In detail, the first array test interface unit includes a first electrostatic dispersion wire 211, first array test pads 221 and 223, first array test wires 222 and 224, and an electrostatic dispersion resistor 250.                     

The first static electricity distribution wiring 211 is a single wiring having a second direction for connecting the plurality of data lines DL1, DL2,... DLm having the first direction in parallel. The first static electricity distribution wiring 211 blocks external static electricity from being directly applied to the data lines DL1, DL2,... DLm.

The first array test pad includes a first pad 221 and a second pad 222 in a 2D manner. The first pad 221 is supplied with a first test signal applied to odd-numbered data lines DL1, DL3,... The second pad 222 is supplied with a second test signal applied to even-numbered data lines DL2, DL4,...

The first array test wiring includes a first wiring 223 and a second wiring 224 according to the 2D method. The first wire 223 applies the first test signal applied from the first pad 221 to the odd-numbered data wires DL1, DL3,... Through the first contact point 227. The second wire 224 applies a second test signal applied from the second pad 222 to the even-numbered data wires DL2, DL4,... Through the second contact point 226, respectively. The first contact point 227 electrically contacts the first wire 223 and the odd-numbered data wires DL1, DL3,... The second contact point 226 electrically contacts the second wire 224 and the even-numbered data wires DL2, DL4,...

The static electricity dissipation resistor 250 is configured to disperse static electricity flowing into the data lines after the opening process between the first static electricity distributing line 211 and the plurality of data data lines DL. , DL3, ..) and even-numbered data lines DL2, DL4, .. are connected. As a result, the static electricity flowing into the odd-numbered data wires is distributed to the even-numbered data wires, and the static electricity flowing into the even-numbered data wires is distributed to the odd-numbered data wires.

In addition, the electrostatic dispersion resistor 250 formed between the odd-numbered data lines DL1, DL3,... And the even-numbered data lines DL2, DL4 ... Thus, during the 2G2D array inspection process, the test signal applied to the odd-numbered data lines DL1, DL3,... Can be prevented from being applied to the even data lines DL2, DL4 ... Can be.

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

2 and 3, a gate metal layer is formed on the transparent substrate 200, and the gate metal layer includes a first wiring 221, a second wiring 222, and a gate electrode of the switching element 170. 171 is formed. A gate insulating layer 282 is formed on the gate metal layer.

The channel layer 251 of the electrostatic dispersion resistor 250 is formed on the gate insulating layer 282, and the channel layer 173 is formed on the gate electrode 171. The channel layers 251 and 173 are formed of the active layers 251a and 173a and the ohmic contacts 251b and 173b.

The source and drain metal layers may include a first static electricity distribution line 211 and a plurality of data lines DL, odd-numbered data lines DL1, DL3, .., and even-numbered data lines DL2, DL4, .. The source and drain electrodes 254 of the electrostatic dispersion resistor 250 and the source and drain electrodes 174 of the switching element 170 are formed. A passivation layer 284 is formed on the source and drain metal layers, and an insulating layer 286 is formed on the passivation layer 284. Of course, the insulating layer 286 may not be formed.

The second contact point 226 is formed to connect the second interconnection 222 formed of the gate metal layer and the even-numbered data interconnects DL2, DL4,... Formed of the source and drain metal layers to each other. The second contact point 226 includes a contact hole EC1 exposing the second wire 222 and a contact hole EC2 exposing the even-numbered data wire DL4. The contact hole 176 exposes the drain electrode 174 of the switching element 170. When forming the contact holes, a separation hole 256 is formed to separate the channel layer 251 of the electrostatic dispersion resistor 250 to electrically connect the odd-numbered data line DL3 and the even-numbered data line DL4. To separate.

As the transparent electrode layer 190 is formed, the second wiring 222 and the even-numbered data wiring DL4 are electrically connected by the transparent electrode layer 190 through the contact holes EC1 and EC2. In addition, the transparent electrode layer 190 and the drain electrode 174 of the switching element 170 are electrically connected through the contact hole 176.

4A through 4D are process diagrams for describing a method of manufacturing the array substrate of FIG. 3.

Referring to FIG. 4A, a gate metal layer is formed by depositing aluminum (Al), copper (Cu), or the like on the transparent substrate 200 by sputtering or the like. The gate metal layer is patterned by a photolithography process to form the first wiring 221, the second wiring 222, and the gate electrode 171 of the switching element 170 on the transparent substrate 200.                     

Thereafter, the gate insulating layer 282 is deposited to cover the gate metal layer formed on the transparent substrate 200. The gate insulating layer 282 is formed of an insulating material such as silicon nitride or silicon oxide.

Referring to FIG. 4B, active layers 251a and 173a and ohmic contacts 251b and 173b are sequentially deposited on the gate insulating layer 282.

A portion of the active layers 251a and 173a and the ohmic contacts 251b and 173b corresponding to the electrostatic dispersion resistor 250 formed between the odd-numbered data line DL3 and the even-numbered data line DL4 and a switching element ( Patterning is performed by a photolithography process so that only the portion corresponding to the gate electrode 171 of the 170 remains. Here, the photolithographic process includes photoresist coating, photoresist patterning, exposure, development, etching using etchant, and the like.

Thereafter, the source and drain metal layers are deposited to cover the ohmic contacts 251b and 173b, and photoresist exposure and development are performed to form a photoresist pattern (not shown). The source and drain metal layers are etched using the photoresist pattern (not shown) as a mask.

As a result, the source and drain metal layers may be disposed on the first static electricity distribution line 211, the plurality of data lines DL, the odd data lines DL3, and the even data lines DL4. The source and drain electrodes 254 of 250 and the source and drain electrodes 174 of the switching element 170 are formed. Thereafter, the switching element 170 forms the channel layer 173 by etching the exposed ohmic contact layer 173b using the source and drain electrodes 174 as a mask.

Referring to FIG. 4C, a passivation layer 284 is formed on the source and drain metal layers, and an insulating layer 286 is formed on the passivation layer 284. Of course, the insulating layer 286 may not be formed. Thereafter, contact holes are formed in the passivation layer 284 and the insulating layer 286 by a photolithographic process.

Referring to FIG. 4D, isolation for separating the active layer 251a and the ohmic contact layer 251b to separate the static dispersion resistor 250 from the odd-numbered data line DL3 and the even-numbered data line DL4. The hole 256 is formed. As a result, the static electricity dissipation resistor 250 connecting between the odd-numbered data line DL3 and the even-numbered data line DL4 is substantially in an electrically separated state. This prevents a leakage current between the odd data line DL3 and the even data line DL4.

In addition, the contact hole EC1 exposes the second wiring 222 formed of the gate metal layer, and the contact hole EC2 exposes the even-numbered data wiring DL4 formed of the source and drain metal layers. In addition, the contact hole 176 exposes the drain electrode 174 of the switching element 170.

Thereafter, the transparent electrode layer 190, which is a transparent conductive material, is deposited on the insulating layer 286 to be patterned. Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO) or Indium-Tin-Zinc-Oxide as the transparent conductive material Is deposited and patterned. Of course, when the insulating layer 286 is not formed, the transparent electrode layer 190 is formed on the passivation layer 284.                     

Therefore, the second wiring 222 and the even-numbered data wiring DL4 are electrically connected to each other by the contact point 226 by the transparent electrode layer 190. In addition, the contact hole 176 is electrically connected to the drain electrode 174 and the transparent electrode layer (or pixel electrode) 190 of the switching element 170.

5 is an enlarged partial view of a portion of a mother substrate according to another embodiment of the present invention. Referring to FIG. 5, the same members shown in the mother substrate for display panel according to the exemplary embodiment shown in FIG. 2 will be described with the same reference numerals.

As illustrated, the mother substrate includes a pixel portion including an array inspection interface, switching elements 170 connected to a plurality of data wires, and pixel electrodes 190 connected to the switching elements 170. Is formed. In detail, the first array test interface unit includes an electrostatic dispersion wire 211, first array test pads 221 and 223, first array test wires 222 and 224, and an electrostatic dispersion resistor 250.

The first static electricity distribution wiring 211 is a single wiring in which a second direction is formed with respect to the plurality of data wires DL1, DL2,... DLm having the first direction. The first static electricity distribution line 211 is connected to any one of the odd-numbered data lines and the even-numbered data lines, and has a structure separated from the other. As shown, odd-numbered data lines are connected to the first static electricity distribution line 211 and even-numbered data lines are separated from the second static electricity distribution line 211.

The first array test pad includes a first pad 221 and a second pad 222 in a 2D manner. The first pad 221 is supplied with a first test signal applied to odd-numbered data lines DL1, DL3,... The second pad 222 is supplied with a second test signal applied to even-numbered data lines DL2, DL4,...

The first array test wiring includes a first wiring 223 and a second wiring 224 according to the 2D method. The first wire 223 applies the first test signal applied from the first pad 221 to the odd-numbered data wires DL1, DL3,... Through the first contact point 227. The second wire 224 applies a second test signal applied from the second pad 222 to the even-numbered data wires DL2, DL4,... Through the second contact point 226, respectively. The first contact point 227 electrically contacts the first wire 223 and the odd-numbered data wires DL1, DL3,... The second contact point 226 electrically contacts the second wire 224 and the even-numbered data wires DL2, DL4,...

The static electricity dissipation resistor 250 is formed at an end portion of the data lines DL. That is, it is formed so as to connect between the odd-numbered data lines DL1, DL3,... And the even-numbered data lines DL2, DL4 ... That is, the static dispersion resistor 250 is formed between odd-numbered data wires connected to the first static electricity distribution line 211 and even-numbered data wires not connected to the first static electricity distribution line 211.

As a result, the static electricity flowing into the even-numbered data line can be separated into the odd-numbered data line, thereby preventing the risk of static electricity.

In addition, the electrostatic dispersion resistor 250 is mechanically connected to the odd-numbered data line and the even-numbered data line, but is electrically disconnected. Therefore, during the 2G2D array inspection process, it is possible to facilitate the array inspection by preventing the test signal applied to the odd-numbered data lines DL1, DL3, .. from being applied to the even-numbered data lines DL2, DL4, .. Can be.

In addition, in the above embodiment, the case where the static dispersion resistor is formed between the odd-numbered data lines and the even-numbered data wires is taken as an example, but it is natural that the static dispersion resistors may be formed between adjacent data lines. For example, static electricity is distributed between adjacent data lines in this manner between the first data line DL1 and the second data line DL2, between the second data line DL2 and the third data line DL3. The resistors are formed to have mechanically interconnected and electrically separated structures.

As a result, it is possible to overcome the risk of static electricity by dispersing static electricity flowing into the plurality of data wires which are substantially in a floating state. In addition, 2G2D inspection can be facilitated by separating electrically adjacent data wires.

As described above, according to the present invention, an electrostatic dispersion resistor is formed between the plurality of data wires in the electrically floating state to inject static electricity flowing from the outside. As a result, a plurality of data lines can be solved from the risk of static electricity.

In addition, since the static electricity dissipation resistor is electrically disconnected from the plurality of data lines, leakage current between the connected data lines can be prevented. Thereby, the 2G2D inspection process can be facilitated.                     

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (9)

A method of manufacturing an array substrate including data lines formed in a first direction, scan lines formed in a second direction, and a switching element having a first current electrode connected to the data line and a control electrode connected to the scan line. in, (a) forming a channel layer of an electrostatic dissipation resistor formed at an end of the data lines to connect an adjacent first data line and a second data line, and a channel layer of the switching element; (b) first and second current electrodes of the electrostatic dispersion resistor connecting the data lines, the first data line and the second data line to a second metal layer, respectively; Forming a two current electrode; (c) forming a passivation layer on the first and second current electrodes of the electrostatic dispersion resistor and on the first and second current electrodes of the switching element; (d) exposing a first hole for removing a portion of the passivation layer to separate the channel layer of the electrostatic dispersion resistor in response to the first data line and the second data line, and a second current electrode of the switching element. Forming a second hole to make; And (e) forming a pixel electrode connected to the second current electrode of the switching element through the second hole. The method of claim 1, Forming a control electrode of the switching element, a first test wire for applying a first test signal to the odd-numbered data wires, and a second test wire for applying a second test signal to even-numbered data wires; The method of manufacturing an array substrate further comprising. The method of claim 1, wherein in step (b), Formed in the second direction on the outside of the data lines to form a static electricity distribution wiring for dispersing the static electricity flowing from the outside, Any one of the first data line and the second data line is connected to the electrostatic dispersion line, and the other is separated from the electrostatic dispersion line. The method of claim 1, wherein in step (d), Forming a first contact hole connecting the odd-numbered data line and the first test line, and forming a second contact hole connecting the even-numbered data line and the second test line. Manufacturing method. The method of claim 4, wherein in step (e), The odd-numbered data line and the first test line are connected through the first contact hole and the second contact hole using a transparent electrode layer, and the even-numbered data line and the second test line are connected to each other. The manufacturing method of an array substrate. A plurality of data wires formed in a first direction; An electrostatic dispersion resistor configured to disperse static electricity introduced from the outside by connecting adjacent first data lines and second data lines; And And a first array inspection unit configured to apply a test signal to the data lines to inspect the data lines. The apparatus of claim 6, further comprising: a first static electricity dispersing wire formed in a second direction on the outside of the data wires to disperse static electricity introduced from the outside; And one of the first data line and the second data line is connected to the first electrostatic dispersion line, and the other is separated from the first electrostatic dispersion line. The method of claim 7, wherein the odd-numbered data lines are connected to the first electrostatic dispersion line, and even-numbered data lines are separated from the first electrostatic line. And the static electricity dissipation resistor is formed between the odd-numbered data lines and the ends of the even-numbered data lines to dissipate static electricity flowing into the even-numbered data lines. The method of claim 6, A plurality of scan wires formed in a second direction; A second static electricity distribution line formed in the first direction on the outer side of the scan lines to disperse static electricity introduced from the outside; And And a second array inspection unit formed in the first direction to apply a test signal to the scan lines.

Images