KR100490040B1 - Liquid crystal display device with two or more shorting bars and method for manufacturing same - Google Patents

Abstract

A vertical gate shorting bar connecting a plurality of gate lines and a plurality of gate lines in a horizontal direction is formed on the transparent insulating substrate, and a gate insulating film is formed on the entire surface of the gate line and the gate shorting bar. A plurality of data lines are formed in the vertical direction on the gate insulating layer so as to intersect the gate lines, and the portion where the gate lines and the data lines intersect is a pixel area. A horizontal data shorting bar is formed to connect the data lines as one outside the pixel area, and a first auxiliary shorting bar is formed inside the gate shorting bar on the gate insulating layer, and is electrically connected to the odd-numbered gate lines. A second auxiliary shorting bar electrically connected to the gate line is formed in parallel with the first auxiliary shorting bar.

Description

Liquid crystal display device having two or more shorting bars and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having two or more shorting bars, and a method of manufacturing the same, and more particularly, to a liquid crystal display device having a shorting bar structure that is easy to detect pixel defects and short defects. It relates to a manufacturing method.

In general, the shorting bar serves to discharge static electricity generated during a process of the liquid crystal display, and may be used to inspect a thin film transistor array after the process is completed.

Next, a liquid crystal display according to the related art will be described in detail with reference to the accompanying drawings.

1 is a schematic view illustrating a thin film transistor substrate for a liquid crystal display device having a shorting bar according to the related art, FIG. 2 is an enlarged view of a portion A of FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2. to be.

Gate lines G1, G2, G3,... Are formed on the substrate 1 in the horizontal direction, and gate pads 10 are formed at the ends of the gate lines G1, G2, G3,... The gate shorting bar 20 binds the gate lines G1, G2, G3,... To the outside of the gate pad 10. The gate insulating film 15 is covered on the gate lines G1, G2, G3,... On the top, data lines D1, D2, D3, D4, ... are formed in the vertical direction, and at each end of each data line D1, D2, D3, D4, .... 30 is formed, and the data shorting bar 40 binds the data lines D1, D2, D3, D4,... Outside the pad 30. In this case, the gate shorting bar 40 and the data shorting bar 20 are connected to each other by a resistor R.

In the screen display area of the liquid crystal display device, the pixel area PX is formed by the intersection of the data lines D1, D2, D3, D4,... And the gate lines G1, G2, G3,... Is formed, and each thin film transistor TFT is formed in each pixel area PX to receive the scan signals from the gate lines G1, G2, G3,... D3, D4, ....) serves to switch the image signal.

2 and 3, the gate lines 5 including the gate lines G1, G2, and G3 and the gate pads 10 and the gate shorting bars 20 may be disposed on the same surface on the substrate 1. It is formed and covered with the gate insulating film 15 and the protective film 25 thereon. Static electricity generated in the substrate during the manufacturing process of the liquid crystal display device is discharged through the gate shorting bar 20, and the gate shorting bar 20 is cut based on the cutting line L after all processes.

When the voltage Va for array inspection is applied to both ends of the shorting bars 20 and 40, the gate lines G1, G2, G3,..., And the data lines D1, D2, D3, D4,. ... and the same voltage Va is applied to the thin film transistors TFT in the pixel region PX, respectively. Accordingly, the pixel area PX appears dark due to the voltage applied to the data lines D1, D2, D3, D4,... However, the pixel region PX in which the gate lines G1, G2, G3, ..., or the data lines D1, D2, D3, D4, ... are defective in disconnection or defective in the thin film transistor in the pixel. ) Appears bright so that a defect in the pixel region PX can be detected.

However, when a short defect S1 in which two or more gate lines or two or more data lines D2 and D3 are connected to each other occurs, a short is applied because the same voltage of Va is applied to the two data lines D2 and D3. No change due to the defect S1 is detected. That is, the short failure S1 cannot be detected by using the structure formed by one gate shorting bar 20 and one data shorting bar 40.

In order to compensate for this disadvantage, dividing the shorting bar 40 into two or more increases the detection power, but may cause damage to the substrate due to static electricity during the process.

An object of the present invention is to implement a thin film transistor substrate having a shorting bar which is easy to detect shorting defects and which is not susceptible to static electricity.

In the liquid crystal display substrate according to the present invention for solving this problem, a plurality of gate lines are formed in parallel to each other, and two tester shorting bars are formed to alternately connect the gate lines. In addition, a main shorting bar that connects all the gate lines into one is formed outside the shorting bar.

In this case, the gate line and the tester shorting bar may be connected to each other by a conductive connection pattern.

A plurality of data lines are formed perpendicular to the gate line, and three tester shorting bars may be alternately connected to three consecutive data lines, which may also be connected by a conductive connection pattern. .

In addition, since the date line is connected to the main shorting bar at the outside of the shorting bar, it is preferable that the date line is connected to the gate line as one.

In the method of manufacturing the liquid crystal display device, the conductive connection pattern is formed in the step of forming the transparent pixel electrode.

After the transparent conductive connection pattern is formed, a portion of the gate line and the data line inside the main shorting bar may be removed.

In such a liquid crystal display substrate and a method of manufacturing the same, two or more gate auxiliary shorting bars or data auxiliary shorting bars are formed and separated from the gate shorting bar and the data shorting bar after the process is completed. Defect detection is also easy.

Next, a liquid crystal display substrate and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, a liquid crystal display substrate and a method of manufacturing the same will be described with reference to FIG. 4.

FIG. 4 is a schematic view showing wirings in a thin film transistor substrate for a liquid crystal display device having a shorting bar according to an exemplary embodiment of the present invention, and showing wirings of the liquid crystal display device in a state where an antistatic pattern and a pattern for inspecting a substrate failure are not removed. Doing.

Gate lines G1, G2, G3, G4, ... are formed in the horizontal direction, and at the ends of the gate lines G1, G2, G3, G4, ..., the gate pads 110, 120, 130, 140, ...) are formed. Further, data lines D1, D2, D3, D4, ... are formed in the vertical direction with gate lines G1, G2, G3, G4, ..., and an insulating film (not shown) interposed therebetween. Data pads 510, 520, 530, 540, ... are formed at one end of the data lines D1, D2, D3, D4, ....

In the screen display area A inside the gate pads 110, 120, 130, 140, ..., and the data pads 510, 520, 530, 540, ..., the data lines D1, D2, D3, A pixel region PX is formed by a portion where D4,... And the gate lines G1, G2, G3, G4,... Intersect each other, and each pixel region PX is a thin film transistor. (TFT) are formed one by one to receive scan signals from the gate lines G1, G2, G3, G4, ..., and to receive image signals from the data lines D1, D2, D3, D4, .... It plays a role of switching.

The static electricity generated in the process of forming such wires causes defects in the thin film transistor TFT or the wirings G1, G2, ...; D1, D2, ... in the pixel region PX. And the data shorting bars 200 and 400 are formed as follows.

The gate shorting bar 200 in the vertical direction, which is formed of a metal for gate wiring outside the gate pads 110, 120, 130, 140,... Are connected to the gate extensions 101, 102, 103, 104,... Outside the data pads 510, 520, 530, 540, ..., the data shorting bar 400 is formed in a horizontal direction with a metal for data wiring. The data pads 510, 520, 530, 540, ... Data extensions 501, 502, 503, 504, ... that extend from. The gate shorting bar 200 and the data shorting bar 400 are connected to each other. Electrostatics generated in the substrate are discharged by the shorting bars 200 and 400 having such a structure.

The gate and data shorting bars 200 and 400 are cut along the cutting line L1 after all the wiring processes of the substrate are completed to remove the antistatic pattern.

Thereafter, array inspection in the image display area of the substrate is performed.

In this case, the auxiliary lines 410, 420; 210, 220, and 230 formed inside the gate and the data shorting bars 200 and 400 are inspected, and the auxiliary lines 410, 420; 210, 220, 230) is as follows.

Two auxiliary lines 410 and 420 are formed between the gate shorting bar 200 and the gate pads 110, 120, 130, 140,... As metals for data wiring such as chromium (Cr) and molybdenum (Mo). It is formed parallel to the gate shorting bar 200, and three auxiliary lines 210, 220, and 230 are formed between the data shorting bar 400 and the data pads 510, 520, 530, 540,... A gate wiring metal such as (Al) is formed in parallel to the data shorting bar 400. In this case, the gate lines G1, G2, G3, G4,... Alternately are formed in the two auxiliary lines 410 and 420 formed in parallel with the gate shorting bar 200, that is, the first and second auxiliary lines. Data lines D1, D2, D3, and D4 connected to the three auxiliary lines 210, 220, and 230, that is, the third, fourth, and fifth auxiliary lines that are connected to and parallel to the data shorting bar 400. , ...) are alternately connected.

Accordingly, different signals are applied to the even-numbered gate lines G2, G4, ... and the odd-numbered gate lines G1, G3, ... using the first and second auxiliary lines 410 and 420, respectively. The data lines D1, D2, D3, D4,... Are divided into R, G, and B signals by using the third, fourth, and fifth auxiliary lines 210, 220, and 230. The defects in the board can be inspected more accurately.

5A and 5B, the principle of inspecting a defect in a substrate will be described.

FIG. 5A is a graph illustrating a gate voltage application state for inspecting an array of a liquid crystal display, and FIG. 5B is a graph showing a change in gate voltage when a short defect exists between gate lines in the liquid crystal display.

As shown in FIG. 5A, V _odd , which has the same deviation with respect to the common voltage V _com at odd gate lines G1, G3,..., And even gate lines G2, G4 _{,. Apply} a voltage of V _even .

As shown in FIG. 5B, when the short S2 exists between the two gate lines G2 and G3, the voltage V _even applied to the second gate line G2 transitions to an increasing direction, and the third The voltage V _odd applied to the gate line G3 transitions in the decreasing direction and converges to V _com .

Therefore, the potential difference is detected as 0 between the two gate lines G2 and G3 where the short S2 is generated.

The same applies to the data line. Different signals are applied to the data lines alternately connected to the third, fourth, and fifth auxiliary lines. When the short S3 exists between the data lines D2, D3, and D4, the potential difference is not detected between the data lines D2, D3, and D4 where the applied voltage converges to one value and the short S3 occurs. .

After the inspection of the array is completed, the substrate failure inspection pattern is removed by cutting the substrate along the cutting line L2 inside the auxiliary lines 410 and 420 (210, 220 and 230).

Thereby, the drive board for liquid crystal display devices is completed.

6 to 10, the gate shorting bar 200, the first and second auxiliary lines 410 and 420, the data shorting bar 400, and the third, fourth and fifth auxiliary lines 210. , 220, 230).

6 and 7 are enlarged views according to the first and second embodiments of the portion B of FIG. 4, that is, the gate shorting bar portion, and FIG. 8 is a cross-sectional view of the line VIII-VIII 'of FIG. A diagram illustrating a connection form between a bar and an auxiliary line.

Gate pads 110, 120, 130,... Are formed on the substrate 1, and gate shorting bars having gate extensions 101, 102, 103,... 200). The gate insulating layer 150 is formed thereon, and the first and second auxiliary lines 410 and 420 are disposed on the gate insulating layer 150 in parallel with the gate shorting bar 200. ...) And the gate shorting bar 200, and a passivation layer 250 is formed thereon.

A connection pattern formed of a material such as a transparent pixel electrode (not shown) on a portion where the gate extension portions 101, 103,..., Overlap with the first auxiliary line 210 or the second auxiliary line 220. 310 and 320 are formed. The connection patterns 310 and 320 may have openings a formed in the passivation layer 250 on the first auxiliary line 210 and openings formed in the gate insulating layer 150 and the passivation layer 250 on the gate extension 101. The opening c and the gate extension 102 which are in contact with the first auxiliary line 210 and the gate extension 101 through the (b), respectively, and are formed in the passivation layer 250 on the second auxiliary line 220. The second auxiliary line 220 and the gate extension 102 are in contact with each other through the opening d formed in the upper gate insulating layer 150 and the passivation layer 250. That is, the gate extension parts 101 and 102 are electrically connected to the first and second auxiliary lines 210 and 220, respectively.

As described above, the gate shorting bar 200 is removed from the inside of the gate shorting bar 200 along the cutting line L1 before the array inspection, and after the inspection, the gate pads 110, 120, 130) The manufacture of the substrate is finished by cutting the cutting line L2 located outside.

In the second embodiment shown in FIG. 7, the process of removing the gate shorting bar 200 is unnecessary.

In the second embodiment, the connection form of the first and second auxiliary lines 410 and 420 and the gate connection portions 101, 102, 103,... Is the same as that of the first embodiment, but the gate shorting bar 200 is used. The gate extension portions 101, 102, 103,..., And the gate insulating layer 150 and the passivation layer 250 between the first auxiliary line 410 and the first auxiliary line 410 are removed. 103,... Are separated from the gate shorting bar 200. In this case, the gate extensions 101, 102, 103,... And the gate shorting bar 200 are separated at the end of the manufacturing process of the substrate, which will be described in detail later.

As such, in the second embodiment, since the gate shorting bar 200 and the auxiliary lines 410 and 420 are separated from each other, the process of cutting the gate shorting bar 200 before the array inspection is not necessary.

After the inspection, the auxiliary lines 410 and 420 are removed by cutting along the cutting line L2 as in the previous embodiment.

FIG. 9 is an enlarged view of a portion C of FIG. 4, that is, a data shorting bar, and FIG. 10 is a cross-sectional view taken along line XX 'of FIG. 9, and illustrates a connection form between a data shorting bar and third, fourth and fifth auxiliary lines. The figure shown.

Third, fourth, and fifth auxiliary lines 210, 220, and 230 are formed on the substrate 1 in the horizontal direction with the same metal as the gate wirings, and the gate insulating layer 150 is stacked thereon. Data lines D1, D2, D3, D4,..., Data pads 510, 520, 530, 540,..., Data pads 510, 520, 530, 540 on the gate insulating layer 150. Data extension portions 501, 502, 503, 504,..., Which are portions extending from ..), and data wirings 55 such as a data shorting bar 400 connected thereto are formed. The passivation layer 250 is formed thereon.

Openings f, h, and j in the passivation layer 250 on the data extension portions 501, 502, 503,..., Intersecting the third, fourth, and fifth auxiliary lines 210, 220, 230. Are respectively formed, and the openings g and the openings are formed in the gate insulating layer 150 and the protective insulating layer 250 on the third, fourth, and fifth auxiliary lines 210, 220, 230,. i, k) are formed, respectively. The connection patterns 301, 302, and 303 formed on the passivation layer 250 have third, fourth, and fifth auxiliary lines 210 and 220 through the openings f, h, j; g, i, and k, respectively. 230 and alternating data connections 501, 502, 503,...

In addition, as in the case of the gate shorting bar 200, an opening 1 through which the data extension parts 501, 502, 503,..., And a portion of the passivation layer 250 are formed is formed inside the data shorting bar 400. Thus, the data extensions 501, 502, 503, 504,... May be separate from the data shorting bar 400, in which case it is not necessary to cut the data shorting bar 400 for array inspection.

As such, the data extension units 501, 502, 503,..., Which are connected to the data lines D1, D2, D3,..., Are alternately connected to the three auxiliary lines 210, 220, 230, respectively. Therefore, different signals may be applied to the third, fourth, and fifth auxiliary lines 210, 220, and 230 to inspect pixel defects and short defects of the thin film transistor substrate.

When a short signal S3 occurs in two or more data lines D2, D3, and D4, when different signals are applied to the data lines D2, D3, and D4, voltage fluctuations due to the shorted portion S3 are applied. This is easily detected.

In this embodiment, three separate auxiliary lines 210, 220, and 230 are provided, but it is also possible to form two or three or more auxiliary shorting bars.

Next, a method of manufacturing a liquid crystal display device having a shorting bar structure according to an exemplary embodiment of the present invention will be described with reference to FIGS. 11A to 11F and 12A to 12F.

11A to 11F are cross-sectional views taken along line VIII-VIII 'of FIG. 7 and according to the process sequence, and FIGS. 12A to 12F are cross-sectional views taken along line X-X' of FIG. 9 according to the process sequence.

A metal layer 50 for gate wiring is formed on the transparent insulating substrate 1, and the gate lines G1, G2, G3, G4,..., The gate pads 100, 110, 120,... Patterning the gate wiring 50 including the bar 200, the gate extensions 101, 102, 103,..., And the first, second and third auxiliary lines 210, 220, 230, and the like. Subsequently, the gate insulating layer 150, an amorphous silicon film (not shown), and an n ⁺ amorphous silicon film (not shown) are sequentially stacked, and the above two layers are photo-etched to form a pattern in the pixel PX.

Next, the metal layer 55 for data wiring is formed, and the data lines D1, D2, D3, D4, ..., the source-drain electrodes (not shown), the data pads 500, 510, 520, 530, Data wiring including the data shorting bar 400, the data extension parts 501, 502, 503, 504, and the first and second gate auxiliary shorting bars 410 and 420. Pattern 55). Next, the n ⁺ amorphous silicon film is etched using the data line 55 as a mask.

After the protective layer 250 is stacked thereon, the contact hole exposing the gate pads 110, 120,..., And the data pads 510, 520, 530,... e; l) and contact holes exposing the first to fifth auxiliary lines 410, 410; 210, 220, 230, gate and data extensions 101, 102, ...; 501, 502, 503, ... (a, b, c, d, e, f, g, h, i, j, k) are formed.

Thereafter, an ITO material is stacked and etched to form pixel electrodes (not shown) in the pixel region PX. In this process, the ITO connection patterns 310, 320, 301, 302, and 303 are also formed. The ITO connection patterns 310 and 320 are connected to the first auxiliary line 410 and the second auxiliary line 420 and the gate extensions 101, 102,... By the contact holes a, b, c, and d. And the other connection patterns 301, 302, and 303 are connected to the third, fourth, and fifth auxiliary lines 210, 220, and 230 through the contact holes f, g, h, i, j, and k, respectively. Are alternately connected to the data extensions 501, 504, 502,...

Finally, the gate shorting bar 200 and the gate extensions 101, 102, 103,... Are separated between the first auxiliary line 410 and the gate shorting bar 200, and the data shorting bar 400. And the data extension units 501, 502, 503,... Are separated between the third auxiliary line 210 and the data shorting bar 400.

As described above, the gate extension portions 101, 102, 103,... And the third gate extension portions positioned between the first auxiliary line 410 and the gate shorting bar 200 in the etching of the passivation layer 250 may be formed as described above. Exposing the data extensions 501, 502, 503,... Positioned between the auxiliary line 210 and the data shorting bar 400, and forming the connection patterns 301, 302, 303; 310, 320. The gate extension portions 101, 102, 103,... And the data extension portions 101, 102, 103,..., Exposed later are etched and removed. Alternatively, after forming the connection patterns 301, 302, 303; 310, 320, the gate shorting bar 200 and the data shorting bar 400 are cut along the cutting line L1 before the defect inspection of the substrate is performed. It is also possible to separate.

As described above, by forming two or more gate auxiliary shorting bars or data auxiliary shorting bars, respectively, and separating from the gate shorting bar and the data shorting bar after the process is completed, it is also easy to detect short defects in the substrate without being susceptible to static electricity. .

1 is a view showing a thin film transistor substrate for a liquid crystal display device having a shorting bar structure according to the related art.

2 is an enlarged plan view of a portion A of FIG. 1;

3 is a cross-sectional view taken along line III-III ′ of FIG. 2,

4 is a view showing a thin film transistor substrate for a liquid crystal display device having a shorting bar according to the present invention;

FIG. 5A is a graph illustrating a voltage application state for array inspection of the liquid crystal display of FIG. 4.

5B is a graph illustrating a voltage fluctuation state when a short defect exists in the liquid crystal display;

6 is an enlarged plan view illustrating a portion B of FIG. 4;

FIG. 7 is another plan view showing an enlarged portion B of FIG. 4;

FIG. 8 is a cross-sectional view taken along line VIII-VIII ′ of FIG. 7;

9 is an enlarged plan view illustrating a portion C of FIG. 4;

FIG. 10 is a cross-sectional view taken along line X-X 'of FIG. 9;

11A to 11F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention, in the order of the process of the gate shorting bar.

12A to 12F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention, in the order of their processes, centering on a data shorting bar.

Claims (29)

A plurality of first wires parallel to each other, A plurality of second wirings formed in parallel with the first wirings; A first shorting bar connected with the first wire, A second shorting bar connected with the second wire, And a main shorting bar formed outside the first and second shorting bars and connected to the first and second wirings, the main shorting bar being wider than the first and second wirings. In claim 1, The first wiring and the second wiring are gate lines to which scan signals are applied. In claim 1, And the first wiring and the second wiring are data lines to which an image signal is applied. In claim 1, And the first wiring and the second wiring are alternately arranged. Transparent insulation substrate, A plurality of gate lines formed in the horizontal direction on the substrate, A gate insulating film covering the gate line and having a first opening exposing the gate line, A plurality of data lines formed in the vertical direction on the gate insulating film so as to intersect the gate lines; A first auxiliary shorting bar formed vertically on the gate insulating film, A second auxiliary shorting bar formed in parallel with the first auxiliary shorting bar on the gate insulating layer; A passivation layer formed on the data line and the first and second auxiliary shorting bars, a second opening on the first opening, and a third and fourth openings on the first and second auxiliary shorting bars, respectively; A first connection pattern formed on the passivation layer and connected to the gate line and the first auxiliary shorting bar through the first and second openings and the third opening, respectively; A second connection pattern formed on the passivation layer and connected to the gate line and the second auxiliary shorting bar which are not connected to the first connection pattern through the first and second openings and the fourth opening. Liquid crystal display substrate. In claim 5, And third, fourth, and fifth auxiliary shorting bars formed on the substrate in parallel to each other in the horizontal direction, and third, fourth, and fifth connection patterns formed on the passivation layer. The fourth and fifth connection patterns electrically connect the data lines and the third, fourth and fifth auxiliary shorting bars, respectively. In claim 6, The passivation layer has a fifth opening that exposes a data line, the gate insulating layer, and the passivation layer have sixth, seventh, and eighth openings that expose the third, fourth, and fifth auxiliary shorting bars, respectively. Fourth and fifth patterns are connected to different data lines through the fifth opening, and are respectively connected to the third, fourth and fifth auxiliary shorting bars through the sixth, seventh and eighth openings. Display substrate. In claim 5, And a gate shorting bar formed on the substrate and connected to the gate line. In claim 8, And a data shorting bar formed on the gate insulating layer and connected to the data line. In claim 9, And the data shorting bar is electrically connected to the gate shorting bar. In claim 5, And a gate shorting bar disposed outside the first and second auxiliary shorting bars and formed on the substrate in a vertical direction and separated from the gate line. In claim 11, And a data shorting bar disposed outside the third, fourth and fifth auxiliary shorting bars and formed on the gate insulating film in a horizontal direction and separated from the data lines. In claim 12, And the data shorting bar is electrically connected to the gate shorting bar. Transparent insulation substrate, A plurality of gate lines formed in the horizontal direction on the substrate, A first auxiliary shorting bar formed on the substrate in a horizontal direction; A second auxiliary shorting bar formed on the substrate in parallel with the first auxiliary shorting bar; A gate insulating film covering the gate line and the first and second auxiliary shorting bars and having first and second openings respectively exposing the first and second auxiliary shorting bars; A plurality of data lines formed in the vertical direction on the gate insulating film so as to intersect the gate lines; A passivation layer formed on the data line and the first and second auxiliary shorting bars and having a third and fourth openings on the first and second openings, respectively, and a fifth opening on the data line; A first connection pattern formed on the passivation layer and connected to the data line and the first auxiliary shorting bar through the first and third openings and the fifth opening; A second connection pattern formed on the passivation layer and connected to the data line and the second auxiliary shorting bar which are not connected to the first connection pattern through the second and fourth openings and the fifth opening. Liquid crystal display substrate. The method of claim 14, And a gate shorting bar formed on the substrate and connected to the gate line. The method of claim 15, And a data shorting bar formed on the gate insulating layer and connected to the data line. The method of claim 16, And the data shorting bar is electrically connected to the gate shorting bar. The method of claim 14, And a data shorting bar disposed outside the first and second auxiliary shorting bars and formed on the gate insulating layer in a horizontal direction and separated from the data lines. The method of claim 18, And a gate shorting bar formed on the substrate in a vertical direction and separated from the gate line. The method of claim 19, And the gate shorting bar is electrically connected to the data shorting bar. Laminating a metal layer, Patterning the metal layer to form a gate line; Forming a gate insulating film on the gate line; Forming first and second auxiliary shorting bars and data lines on the gate insulating layer to test the gate lines; Laminating a protective film, Etching the passivation layer and the gate insulating layer to form first openings and second and third openings exposing the gate line and the first and second auxiliary shorting bars, respectively; Depositing a transparent conductive layer, A first connection pattern connected to the gate line and the first shorting bar through the first and second openings by patterning the transparent conductive layer, and a connection to the gate line and the second shorting bar through first and third openings. Forming a second connection pattern and a pixel electrode; And removing the first and second auxiliary shorting bars after detecting the short failure. The method of claim 21, Patterning the metal layer to form an antistatic shorting bar connected to the gate line. The method of claim 22, And removing the connection between the antistatic shorting bar and the gate line after forming the connection pattern. Forming first, second and third auxiliary shorting bars for testing the gate lines and the data lines on the substrate, Forming a gate insulating film, Stacking a metal layer on the gate insulating film, Patterning the metal layer to form a data line; Laminating a protective film, Etching the passivation layer and the gate insulating layer to form first openings and second, third and fourth openings exposing the data line and the first, second and third auxiliary shorting bars; Depositing a transparent conductive layer, Patterning the transparent conductive layer to form a connection pattern and a pixel electrode connected to the data line and the first to third auxiliary shorting bars through the first and second to fourth openings, respectively; And removing the first to third auxiliary shorting bars after detecting the short failure. The method of claim 24, And patterning the metal layer to form an antistatic shorting bar connected to the data line. The method of claim 25, And removing the connection of the antistatic shorting bar and the data line after the forming of the connection pattern. A plurality of gate lines and data lines on the substrate, an antistatic main shorting bar connected to the gate lines and the data lines, first and second auxiliary shorting bars for gate testing alternately connected to the gate lines, and alternately with the data lines, respectively. Forming wires such as third and fourth auxiliary shorting bars for data testing connected thereto; Separating the main shorting bar from the gate and data line; Detecting a failure of the data line and the gate line by applying a voltage to the first and second auxiliary shorting bars and the third and fourth auxiliary shorting bars; And removing the first, second, third and fourth auxiliary shorting bars after the defect detection step. The method of claim 27, And applying different voltages to the first auxiliary shorting bar and the second auxiliary shorting bar. The method of claim 27, And applying different voltages to the third auxiliary shorting bar and the fourth auxiliary shorting bar.

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