KR20050105578A - A substrate of liquid crystal display device and method of fabricating of the same - Google Patents

Abstract

The present invention relates to a drive circuit-integrated liquid crystal display device array substrate using a polycrystalline silicon thin film transistor as a drive element and a switching element, and a method of manufacturing the same.

The present invention is characterized in that the manufacturing of the array substrate for the liquid crystal display device integrated with the driving circuit can be made by the seven mask process that was produced by the nine mask process.

Therefore, there is an advantage that can reduce the process cost while reducing the process time by simplifying the process.

In addition, by simplifying the process, there is an advantage that can reduce the probability of failure during the process.

Description

A substrate of liquid crystal display device and method of fabricating of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device with a driving circuit including a polycrystalline silicon thin film transistor and a manufacturing method thereof.

In general, a liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate, and displays an image by using a difference in refractive index of light according to the anisotropy of the liquid crystal. It is a display device.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because it is possible to use low-temperature insulating substrates because of low temperature processing.

However, since hydrogenated amorphous silicon has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, they are changed to a quasi-stable state when irradiated with light or applied with an electric field, and used as a thin film transistor device. It is difficult to use as a driving circuit due to poor stability and low electrical characteristics (low field effect mobility: 0.1 to 1.0 cm2 / V · s).

On the other hand, since polysilicon has a higher field effect mobility than amorphous silicon, a driving circuit can be made on a substrate.If the driving circuit is directly made on a substrate using polysilicon, the mounting becomes very simple and the liquid crystal panel is more compact. There is an advantage that can be produced.

1 is a schematic diagram of an array substrate for a liquid crystal display device integrated with a general driving circuit unit.

As illustrated, the insulating substrate 10 may be largely defined as a display unit D1 and a non-display unit D2, and a plurality of pixels P are arranged in a matrix form on the display unit D1, and a switching element for each pixel. T and the pixel electrode 78 connected thereto are configured.

In addition, a gate line GL extending along one side of the pixel P and a data line DL perpendicular to the gate line GL are formed.

The non-display part D2 includes driving circuit parts DP and GP, and the driving circuit parts DP and GP are located on one side of the substrate 10 to apply a signal to the gate line GL. GP and a data driving circuit part DP positioned on the other side of the substrate 10 that is not parallel thereto and applying a signal to the data line DL.

In addition, the gate and data driving circuit units GP and DP are connected to an external signal input terminal OL.

The gate and data driving circuit units GP and DP control an internal signal input through the external signal input terminal OL therein and control the display to the pixel unit P through the gate and data lines GL and DL, respectively. Apparatus for supplying signals and data signals.

Accordingly, the gate and data driver circuits GP and DP are configured as thin film transistors having a complementary metal-oxide semiconductor (CMOS) structure that is an inverter to properly output an input signal.

The CMOS is a semiconductor technology used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS uses extra electrons (n-type semiconductor) and negatively charged holes (p-type semiconductor) charged with negative electricity. It is used as a complementary method for forming a conductor and forming a current gate by effective electrical control of the two kinds of semiconductors.

In the related art, a polycrystalline thin film transistor is used as the CMOS device and the switching device.

2 is an enlarged plan view illustrating a configuration of a single pixel of a conventional array substrate including a polycrystalline thin film transistor.

As illustrated, a gate line GL extending in one direction on the substrate 10 and a data line DL defining a pixel region P by crossing each other perpendicularly.

At the intersection of the gate line GL and the data line DL, an active layer 18 formed of polysilicon, a gate electrode 34 formed on the active layer 18, and the active layer 18 The thin film transistor T including the source electrode 70 and the drain electrode 72 in contact with each other is configured.

In the pixel region P, a pixel electrode 78 in contact with the drain electrode 72 is formed.

In addition, a storage capacitor C _ST is formed in the pixel region P. The storage wiring 36 that intersects the pixel region P is used as a second electrode, and is disposed below the second electrode and doped with impurities. The used polycrystalline pattern 20 as a first electrode.

3A and 3B, the cross-sectional structure of the above-described CMOS element of the driving circuit unit and the cross-sectional structure of the pixel region including the switching element will be described.

 3A and 3B are cross-sectional views of a driving circuit portion CMOS structure thin film transistor and a pixel region including a switching element, respectively. (A and B are cross-sectional views of a CMOS element in which n-type and p-type thin film transistors are combined. C is a cross-sectional view of the switching element and the pixel region.)

As shown in FIGS. 3A and 3B, a buffer layer 12 is formed on the insulating substrate 10, and the driving circuit regions A and B and the switching region C of the substrate 10 are formed. A CMOS device (a combination of an n-type thin film transistor and a p-type thin film transistor) and an n-type thin film transistor are positioned, and in the pixel region P, a pixel electrode 78 and a storage capacitor C _ST contacting the n-type thin film transistor are disposed. It is composed.

The cross-sectional structure of each area described above will be described below.

As illustrated, the first active pattern 14, the second active pattern 16, and the third active pattern 18 are formed in each of the regions A, B, and C on the buffer layer 12.

The first and third active patterns 14, 16, and 18 are patterns of polysilicon layers, and each of the first and third active patterns 14, 16, and 18 may be defined as a first active region V1 and a second active region V2.

In this case, the third active pattern 18 includes an extension part 20 extending to the pixel area P. FIG.

A gate insulating layer 22 is disposed on an entire surface of the substrate 10 including the first to third active patterns 14, 16, and 18, and each of the active patterns 14, 16, and 18 is disposed on the gate insulating layer 22. The first, second, and third gate electrodes 30, 32, and 34 are respectively configured to correspond to the first active region V1 of.

At the same time, the storage wiring 36 crossing the pixel region P is formed.

The storage wiring 36 is positioned above the extension 20 of the third active pattern 18. At this time, the storage wiring 36 is the first electrode, and the storage wiring 36 is removed. The storage capacitor C _ST which uses two electrodes is comprised.

An interlayer insulating film 48 is formed on the entire surface of the substrate 10 including the first to third gate electrodes 30, 32, 34 and the storage wiring 36, and the interlayer insulating film 48 and a gate below the interlayer insulating film 48 are formed. First source and drain electrodes 62 and 64 and second source and drain contacts the second active regions V2 of the active patterns 14, 16, and 18 exposed by etching the insulating layer 28. Electrodes 66 and 68 and third source and drain electrodes 70 and 72 are configured.

In the above-described configuration, the first active pattern of the driving circuit regions A and B, the switching region C, and the second active region V2 of the third active patterns 14 and 18 are connected to the gate electrodes 30 and 34. N-ions doped LDD (Lightly Doped Drain) region (F) adjacent to both sides and the region except the LDD region is composed of an ohmic contact region doped with n + ions.

The LDD region F is configured to disperse hot carriers. Since the LDD region has a low doping concentration, the LDD region F prevents an increase in the leakage current I _off , thereby preventing the increase of the on-state current. It prevents the loss.

In the pixel region P, a pixel electrode 78 connected to the drain electrode 72 of the switching region C is formed.

The n-type thin film transistors in the switching region C and the n-type and p-type thin film transistors constituting the CMOS elements in the driving circuit regions A and B are constructed in the same process on a single substrate.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device including a driving circuit according to the related art including the aforementioned polycrystalline silicon thin film transistor will be described.

4A and 4B are cross-sectional views illustrating a first mask process, FIGS. 5A and 5B are cross-sectional views illustrating a second mask process, and FIGS. 6A and 6B are views illustrating a third mask process, and FIGS. 7A and 7B. 8A and 8B are cross-sectional views illustrating a fifth mask process, FIGS. 9A and 9B show a sixth mask process, and FIGS. 10A and 10B show a seventh mask process. 11A and 11B are views illustrating an eighth mask process, and FIGS. 12A and 12B are cross-sectional views illustrating a ninth mask process.

(At this time, 4b, 5b, 6b, 7b, 8b, 9b, 10b, 11b, and 12b are cross-sectional views taken along the line II-II of FIG. 2.)

As shown in the drawing, a pixel region including driving circuit regions A and B consisting of N regions A and P regions B, a switching region C, and a storage region ST is formed on the substrate 10. P is defined and silicon oxide (SiO ₂ is deposited to form a buffer layer 12).

The first active pattern 14 and the second active patterned by the first mask process on the driving circuit regions (N region A, P region B) and the switching region C on the buffer layer 12. The pattern 16 and the third active pattern 18 are formed.

The first to third active patterns 14, 16, and 18 are formed of polycrystalline silicon layers, and for convenience, each pattern includes a second active region located at both sides of the first active region V1 and the first active region V1. It is defined as (V2).

In addition, the LDD region F is defined at both sides of the first active region V1 of the N region and the switching regions A and C. FIG.

In this case, the third active pattern 18 includes an extension part 20 extending to the storage area ST.

5A and 5B illustrate a second mask process step, wherein a photoresist is applied to the entire surface of the substrate 10 on which the active patterns 14, 16, and 18 are formed. By patterning the first, second, and third photosensitive patterns 22, 24, and 26 covering the first to third active patterns 14, 16, and 18 of the driving regions A and B and the switching region C, respectively. ). In this case, the extension of the third active pattern 18, that is, the polycrystalline silicon pattern 20, is exposed.

Next, a process of doping n + or p + impurity ions to the exposed surface of the polycrystalline silicon pattern 20 is performed.

The polycrystalline silicon pattern 20 doped with impurities may serve as a first electrode of the storage capacitor.

6A and 6B are cross-sectional views illustrating a third mask process. As illustrated, silicon nitride (SiN _X ) and oxide of the substrate 10 having the first to third active patterns 14, 16, and 18 are formed. A gate insulating film 28 is formed by depositing one selected from the group of inorganic insulating materials including silicon (SiO ₂ ).

Aluminum (Al) and aluminum alloy (AlNd) are deposited on the entire surface of the substrate 10 on which the gate insulating layer 28 is formed, and patterned using a third mask process to form the first to third active patterns 14, 16, and 18. Gate electrodes 30, 32, and 34 are formed respectively corresponding to the first active regions V1 of the "

At the same time, the storage wiring 36 is formed on the storage region ST in the pixel region P, that is, on the polycrystalline silicon pattern 20 doped with the impurity ions.

In this case, a storage capacitor C _ST having the polycrystalline silicon pattern 20 as the first electrode and the upper storage wiring 36 as the second electrode is configured.

Next, a process of doping n-ion (low concentration n-type impurity ion doping) is performed on the entire surface of the substrate 10 on which the gate electrodes 30, 32, and 34 are formed.

In the above-described doping process, the surfaces of the first to third active patterns 14, 16, and 18 exposed to the periphery of the gate electrodes 30, 32, and 34 are doped with n-ions.

7A and 7B illustrate a fourth mask process, wherein a photoresist is formed on the entire surface of the substrate 10 subjected to n-ion doping on the exposed surfaces of the first to third active patterns 14, 16, and 18. (photoresist) and then patterned by a fourth mask process to cover the first photoresist pattern 38, which covers the LDD region F defined in the N region A of the driving regions A and B, and P The second photoresist pattern 40 covering the region B and the third photoresist pattern 42 covering the LDD region F of the switching region C are formed.

At this time, the second active regions V2 of the first and third active patterns 14 and 18 of the N region A and the switching region C are exposed.

Next, a process of doping n + ions (high concentration n-type ions) is performed on the entire surface of the substrate 10 on which the photosensitive patterns 38, 40, and 42 are formed.

In this case, n + ions are doped on the exposed active pattern 14 of the N region A and the exposed active pattern 18 of the switching region C, and this portion is an ohmic contact layer. function as a contact layer.

Next, a process of removing the first to third photoresist patterns 38, 40, and 42 is performed.

8A and 8B illustrate a fifth mask process. As shown in FIG. 8A and FIG. 8B, a photoresist is applied to the entire surface of the substrate 10 subjected to the process of doping the n + impurity ions, and then patterned using a fifth mask process. The first photoresist pattern 44 and the second photoresist pattern 46 covering the N region A and the switching region C are formed.

Next, a process of doping p + impurity ions (high concentration p + impurity ions) is performed on the entire surface of the substrate 10 on which the first and second photoresist patterns 44 and 46 are formed. The surface of the exposed second active pattern 16 (in detail, the second active region) is doped with p + ions.

The region doped with p + ions also serves as an ohmic contact layer.

9A and 9B are diagrams illustrating a sixth mask process. As illustrated, silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 10 subjected to the p + ion doping process, and the interlayer insulating film 48 is illustrated. The first contact hole 50 and the second contact hole exposing the second active region (the region doped with V 2, n + ions) of the N-type region A are formed by patterning by a sixth mask process. 52 and a third contact hole 54 and a fourth contact hole 56 exposing the second active region V2 (p + ion doped region) of the P-type region B, The fifth contact hole 58 and the sixth contact hole 60 exposing the second active region V2 (the region doped with n + ions) of the switching region C are formed.

10A and 10B illustrate a seventh mask process, and as shown in FIG. 10A, a selected one of the conductive metal groups as described above is deposited on the entire surface of the substrate 10 on which the interlayer insulating layer 48 is formed. Patterned in a seven-mask process, the source electrode 62, 66, 70 and the drain electrode 64 in contact with each of the exposed second active regions V2 of the first to third active patterns 14, 16 and 18. , 68,72).

11A and 11B illustrate an eighth mask process, and as shown, an inorganic insulating material on the entire surface of the substrate 10 on which the source and drain electrodes 62, 66, 70/64, 68, and 72 are formed. Is deposited to form a protective film 74.

Next, the passivation layer 74 is patterned by an eighth mask process to form a drain contact hole 76 exposing the drain electrode 72 of the switching region C.

12A and 12B illustrate a ninth mask process. Indium-tin-oxide (ITO) is deposited and patterned on the entire surface of the substrate 10 on which the passivation layer 74 is formed to expose the exposed drain electrode 72. ) And the pixel electrode 78 positioned in the pixel region P is formed.

Through the above-described process, a conventional array substrate for a liquid crystal display device including a CMOS element and a switching element composed of a polycrystalline thin film transistor in a driving region and a switching region can be manufactured.

However, the manufacturing method of the array substrate for a liquid crystal display device according to the related art belongs to a very large number of processes, and when such a large number of processes increases, the probability of defects in manufacturing a liquid crystal display device is increased, and process time delay and process cost are increased. It becomes a problem to increase the yield of the product.

An object of the present invention is to solve the above problems, and proposes a method of manufacturing an array substrate by lowering the conventional 9 mask process to 7 mask processes.

An object of the present invention is to reduce the number of processes to significantly reduce the probability of failure, shorten the process time and reduce the process cost.

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes: a substrate including a pixel region and a driving region including a switching region; A CMOS device comprising a combination of an n-type polycrystalline thin film transistor and a p-type polycrystalline thin film transistor in the driving region; A polycrystalline thin film transistor configured in the switching region; A gate wiring formed on one side of the pixel region and a data wiring formed on the other side of the pixel region perpendicular to the pixel region; A pixel electrode connected to the polycrystalline thin film transistor of the switching region and positioned in the pixel region; The storage wiring includes an insulating layer disposed under the pixel electrode.

The polycrystalline thin film transistor is composed of a gate electrode, an active layer (polycrystalline silicon layer), a source electrode and a drain electrode, and the polycrystalline thin film transistor of the switching region is composed of an n-type polycrystalline thin film transistor.

A storage capacitor comprising the storage wiring as the first electrode and the pixel electrode of the portion overlapping with the second electrode as the second electrode is configured.

The pixel electrode is made of a transparent material.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: defining a substrate as a pixel region and a driving region including a switching region; A first mask process step of forming first and second active patterns in the driving region and a third active pattern in the switching region; A second mask process step of forming a gate electrode with a gate insulating film interposed therebetween on a portion of the first, second, and third active patterns; Doping n-ions (low concentration of n-type impurity ions) to surfaces of the first, second and third active patterns where the gate electrode is not located; A first photosensitive pattern and a second photosensitive pattern covering a gate electrode on the first and third active patterns, a portion of an n-ion doped region surrounding the first and third active patterns, and a third photosensitive pattern completely covering the second active pattern. Forming a third mask process step; Doping n + ions (high concentration of n-type impurity ions) to surfaces of the first and third active patterns exposed to the periphery of the first and second photosensitive patterns; A fourth mask process step of forming a transparent pixel electrode in said pixel region; A fifth interlayer insulating film formed over the substrate on which the pixel electrode is formed and patterned to expose n + doped regions of the first and third active patterns and to expose n-ion doped regions of the second active pattern; A mask processing step; Performing a process of doping p + ions to the substrate on which the interlayer insulating film is formed, thereby forming the exposed n-doped region as a p + doped region; A first source electrode and a second drain electrode in contact with the n + region of the exposed first active pattern, a second source electrode and a second drain electrode in contact with the p + region of the exposed second active pattern, and the exposure And a sixth mask process step of forming a third source electrode and a third drain electrode in contact with the n + region of the third active pattern.

Further forming a signal input pad formed on the outer side of the substrate during the same process as forming the source and drain electrodes in contact with the first to third active patterns and the gate electrodes of the first to third active patterns. A seventh mask process step of forming a protective film on the entire surface of the substrate on which the first to third source electrodes and the first to third drain electrodes are formed and patterning the semiconductor substrate to expose a signal input pad formed on the outer side of the substrate; It includes.

The concentration of the n + ion is characterized in that 2.5 to 3 times the concentration of the p + ion.

The interlayer insulating layer is formed by sequentially stacking an oxide layer (silicon oxide layer) and a nitride layer (silicon nitride layer), and doping the p + ion, followed by a hydrogenation process, thereby performing surface defects of the first to third active patterns. To proceed further to remove the step.

In the fifth mask process, the side surface of the gate electrode positioned in the second active pattern is formed so that the second source and drain electrodes contacting the second active pattern are formed to be spaced apart from the exposed gate electrode. Characterized in that.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device with integrated driving circuit according to an embodiment of the present invention will be described.

Example

Hereinafter, a configuration of an array substrate for a polycrystalline liquid crystal display device according to the present invention will be described with reference to the drawings.

13 is an enlarged plan view of one pixel of the array substrate for a polycrystalline liquid crystal display according to the present invention.

As illustrated, the gate line GL extending in one direction on the substrate 100 and the data line DL defining the pixel region P by perpendicularly crossing the gate line GL.

At the intersection of the gate line GL and the data line DL, an active layer (active pattern) 108 formed of polysilicon, a gate electrode 116 formed on the active layer 108, and the active layer ( A thin film transistor T including a source electrode 150 and a drain electrode 152 in contact with 108 is configured.

The pixel region P includes a transparent pixel electrode 124 in contact with the drain electrode 152.

In addition, a storage capacitor C _ST is formed in the pixel region P. The storage wiring 118 crossing the pixel region P is used as a first electrode, and a pixel formed on the first electrode. A part of the electrode 124 is used as the second electrode.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device with integrated driving circuit according to the present invention will be described with reference to the above-described plan view.

14A and 14B are cross-sectional views illustrating a first mask process, FIGS. 15A and 15B are cross-sectional views illustrating a second mask process, and FIGS. 16A and 16B illustrate a third mask process, and FIGS. 17A and 17B. Is a cross-sectional view showing a fourth mask process, FIGS. 18A and 18B are cross-sectional views showing a fifth mask process, FIGS. 19A and 19B show a sixth mask process, and FIGS. 20A and 20B show a seventh mask process. It is a diagram showing.

14A and 14B are diagrams illustrating a first mask process, and drive circuit regions A and B, a switching region C, and storage, each of which includes N regions A and P regions B, on a substrate 100. The pixel region P including the region ST is defined, and a silicon insulating material (silicon nitride (SiN _X ) or silicon oxide (SiO ₂ )) is deposited to form a buffer layer 102.

The first active pattern 104 and the second active patterned by the first mask process on the switching region C and the driving circuit region N region B and P region C on the buffer layer 102. The pattern 106 and the third active pattern 108 are formed.

The first to third active patterns 104, 106 and 108 are formed of polycrystalline silicon, and for convenience, each pattern is defined as a second active region V2 positioned at both sides of the first active region V1 and the first active region V1. do.

In addition, the LDD region F is defined at both sides of the N region A of the driving region and the first active region V1 of the switching region C.

15A and 15B illustrate a second mask process step. An inorganic insulating layer including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 100 on which the active patterns 104, 106, and 108 are formed. The gate insulating layer 110 is formed by depositing one selected from the group of materials.

A conductive metal including aluminum (Al), aluminum alloy (AlNd), copper (Cu), molybdenum (Mo), tungsten (W), and chromium (Cr) on the entire surface of the substrate 100 on which the gate insulating layer 110 is formed. One selected from the group is deposited and patterned by a second mask process to form gate electrodes 112, 114, and 116, respectively, corresponding to the first active regions V1 of the first to third active patterns 104, 106, and 108.

At the same time, the storage wiring 118 is formed on the storage area ST in the pixel area P.

A process of doping n-ions (low concentration n-type impurity ions) is performed on the entire surface of the substrate 100 on which the gate electrodes 112, 114, and 116 and the storage wiring 118 are formed.

In this manner, the n-ions are doped on the surfaces of the first to third active patterns 104, 106 and 108 exposed to the periphery of the gate electrodes 112, 114 and 116.

16A and 16B illustrate a third mask process, in which a photoresist is deposited on the entire surface of the substrate 100 subjected to the n-doping process and patterned using a third mask process to form the first active pattern 104. ), A first photosensitive pattern E1 covering the gate electrode 112 and the LDD region, a second photosensitive pattern E2 covering the second active pattern 106, and a gate of the third active pattern 108. A third photosensitive pattern E3 covering the electrode 116 and the LDD region F is formed.

Next, n + corresponding to the first active pattern 104 exposed to the periphery of the first to third photosensitive patterns E1, E2, and E3 and the second active region V2 of the third active pattern 108. The process of doping ion (high concentration n-type impurity ion) is performed.

In this manner, n-ions are doped in the LDD region F and n + ions are doped in the second active region V2 in the first active pattern 104 and the second active pattern 106. .

At this time, the region V2 doped with n + ions functions as an ohmic contact layer.

17A and 17B illustrate a fourth mask process, wherein one or more materials selected from the group of inorganic insulating materials described above are deposited on the entire surface of the substrate 100 subjected to the process of doping n + ions. Thus, the first interlayer insulating film 120 is formed.

Next, one selected from a transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the entire surface of the substrate 100 on which the first interlayer insulating layer 120 is formed. By patterning, the transparent pixel electrode 124 positioned in the pixel region P is formed.

As described above, by forming the pixel electrode 124, the storage wiring 118 formed in the pixel region P is used as the first electrode, and the storage is formed using the pixel electrode on the first electrode as the second electrode. Capacitor C _ST may be configured.

18A and 18B illustrate an oxide film layer D1 on which silicon nitride (SiN _X ) is deposited on the entire surface of the substrate 100 on which the pixel electrode 124 is formed, as illustrated in a fifth mask process. A nitride film layer D2 on which silicon oxide (SiO ₂ ) is deposited is formed.

The oxide layer D1 and the nitride layer D2 become the second interlayer insulating layer 126.

The second interlayer insulating layer 126 is patterned by a fifth mask process so that the first contact hole 128 and the second contact hole 130 exposing the second active region V2 of the first active pattern 104. ), A third contact hole 132 and a fourth contact hole 134 exposing the second active region V2 of the second active pattern 106, and forming the third active pattern 108. The fifth contact hole 136 and the sixth contact hole 138 exposing the second active region V2 of FIG.

At the same time, a seventh contact hole 140 exposing the pixel electrode 126 adjacent to the third active pattern 108 is formed.

Next, a process of doping p + ions on the entire surface of the substrate 100 on which the plurality of contact holes 128, 130, 132, 134, 136, 138 and 140 are formed is performed.

At this time, the doping concentration of the p + ions is to be (1/3) to (1 / 2.5) times the doping concentration of the n + ions.

Only in this way, the second active region V2 corresponding to the first active pattern 104 and the third active pattern 108 may have an n-type characteristic even when p + ions are doped.

Next, in order to remove defects on the surfaces of the active patterns 104, 106 and 108 doped with impurities, a process of hydrogenating the substrate 100 on which the nitride layer D2 is formed is performed.

In this case, it is common to form a silicon nitride film containing hydrogen in the uppermost layer of the substrate before the hydrogenation process, and when the thickness of the nitride film becomes thick, the parasitic cap capacitance between the upper and lower electrodes increases, so as to reduce this, the lower part of the silicon nitride film is reduced. Will form a silicon oxide film having a low dielectric constant.

19A and 19B illustrate a sixth mask process, indium-tin-oxide (ITO) and indium-zink on the entire surface of the substrate 100 on which the second interlayer insulating layer 126 including the plurality of contact holes is formed. A first one spaced apart from the second active region V2 of the first active pattern 104 by depositing and patterning one selected from a transparent conductive metal compound group including an oxide (IZO) by a sixth mask process. The source electrode 142 and the first drain electrode 144 are formed, and the second source electrode 146 and the second drain electrode spaced apart from each other while being in contact with the second active region V2 of the second active pattern 106. 148 and a third source electrode 150 and a third drain electrode 152 spaced apart from each other while contacting the second active region V2 of the third active pattern 108.

In this case, the third drain electrode 152 is configured to be in contact with the pixel electrode 124 at the same time.

In this process, a CMOS device including n-type and p-type thin film transistors may be formed in the driving regions A and B, and an n-type thin film transistor may be formed in the switching region C.

20A and 20B illustrate a seventh mask process, and as illustrated, benzocyclobutene (BCB) and benzocyclobutene (BCB) are formed on the entire surface of the substrate 100 on which the plurality of source electrodes 142, 146, 150 and the drain electrodes 144, 148, 152 are formed. A protective film 154 is formed by depositing a selected one of a group of organic insulating materials including an acrylic resin and patterned by a seventh mask process to surround the substrate 100 instead of the pixel area P. A process of exposing the pad portion (signal input end) is performed by etching a portion of the display area.

In addition, a portion of the interlayer insulating layer 126 and the passivation layer 154 of the pixel region P may be removed to open the pixel region.

Although not shown, the pad part is manufactured during the process of forming the gate electrode or the source and drain electrodes, and serves to transfer an external signal to the CMOS device.

Through the above-described process, it is possible to manufacture an array substrate for a driving circuit-integrated liquid crystal display device according to the present invention.

The manufacturing method of the array substrate for the driving circuit-integrated polycrystal liquid crystal display device according to the present invention has the following effects since the two mask processes can be reduced as compared with the conventional method.

First, since the process is reduced, there is an effect that can significantly reduce the probability of failure that can occur during the process.

Second, the process time can be shortened, and the process cost can be lowered.

Third, there is an effect of improving the yield by the first and second effects.

1 is a plan view schematically showing a general liquid crystal panel integrated with a driving circuit unit;

2 is an enlarged plan view showing one single pixel area of an array substrate;

3A and 3B are cross-sectional views of a switching element formed in a pixel region of a conventional array substrate for a liquid crystal display device and a CMOS element formed in a driving circuit region,

4A and 4B are cross-sectional views illustrating a first mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

5A and 5B are cross-sectional views illustrating a second mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

6A and 6B are cross-sectional views illustrating a third mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

7A and 7B are cross-sectional views illustrating a fourth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

8A and 8B are cross-sectional views illustrating a fifth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

9A and 9B are cross-sectional views illustrating a sixth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

10A and 10B are cross-sectional views illustrating a seventh mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

11A and 11B are cross-sectional views illustrating an eighth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

12A and 12B are cross-sectional views illustrating a ninth mask process step of a manufacturing process of a conventional array substrate for a liquid crystal display device;

13 is an enlarged plan view showing a single pixel of an array substrate for a liquid crystal display device according to the present invention;

14A and 14B are cross-sectional views illustrating a first mask process step in a manufacturing process of an array substrate for a liquid crystal display device according to the present invention;

15A and 15B are cross-sectional views illustrating a second mask process step of a manufacturing process of an array substrate for a liquid crystal display device according to the present invention;

16A and 16B are cross-sectional views illustrating a third mask process step of a manufacturing process of an array substrate for a liquid crystal display device according to the present invention;

17A and 17B are cross-sectional views illustrating a fourth mask process step of a manufacturing process of an array substrate for a liquid crystal display device according to the present invention;

18A and 18B are cross-sectional views illustrating a fifth mask process step of a manufacturing process of an array substrate for a liquid crystal display device according to the present invention;

19A and 19B are cross-sectional views illustrating a sixth mask process step of a manufacturing process of an array substrate for a liquid crystal display device according to the present invention;

20A and 20B are cross-sectional views illustrating a seventh mask process step of a manufacturing process of an array substrate for a liquid crystal display according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: substrate GL: gate wiring

DL: data wiring 108: active pattern

116: gate electrode 118: storage wiring

124: pixel electrode 150: source electrode

152: drain electrode

Claims (14)

A substrate in which a pixel region including a switching region and a driving region are defined; A CMOS device comprising a combination of an n-type polycrystalline thin film transistor and a p-type polycrystalline thin film transistor in the driving region; A polycrystalline thin film transistor configured in the switching region; A gate wiring formed on one side of the pixel region and a data wiring formed on the other side of the pixel region perpendicular to the pixel region; A pixel electrode connected to the polycrystalline thin film transistor of the switching region and positioned in the pixel region; A storage wiring formed with an insulating film disposed under the pixel electrode Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the polycrystalline thin film transistor comprises a gate electrode, an active layer (polycrystalline silicon layer), a source electrode and a drain electrode. The method of claim 1, And the polycrystalline thin film transistor in the switching region is an n-type polycrystalline thin film transistor. The method of claim 1, And a storage capacitor comprising the storage wiring as a first electrode and a pixel electrode in a portion overlapping the second electrode. The method of claim 1, And the pixel electrode is made of a transparent material. Defining a substrate as a pixel region and a driving region including a switching region; A first mask process step of forming first and second active patterns in the driving region and a third active pattern in the switching region; A second mask process step of forming a gate electrode with a gate insulating film interposed therebetween on a portion of the first, second, and third active patterns; Doping n-ions (low concentration of n-type impurity ions) to surfaces of the first, second and third active patterns where the gate electrode is not located; A first photosensitive pattern and a second photosensitive pattern covering a gate electrode on the first and third active patterns, a portion of an n-ion doped region surrounding the first and third active patterns, and a third photosensitive pattern completely covering the second active pattern. Forming a third mask process step; Doping n + ions (high concentration of n-type impurity ions) to surfaces of the first and third active patterns exposed to the periphery of the first and second photosensitive patterns; A fourth mask process step of forming a transparent pixel electrode in said pixel region; A fifth interlayer insulating film formed over the substrate on which the pixel electrode is formed and patterned to expose n + doped regions of the first and third active patterns and to expose n-ion doped regions of the second active pattern; A mask processing step; Performing a process of doping p + ions to the substrate on which the interlayer insulating film is formed, thereby forming the exposed n-doped region as a p + doped region; A first source electrode and a second drain electrode in contact with the n + region of the exposed first active pattern, a second source electrode and a second drain electrode in contact with the p + region of the exposed second active pattern, and the exposure A sixth mask process step of forming a third source electrode and a third drain electrode in contact with the n + region of the third active pattern Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 6, Further forming a signal input pad formed on the outer side of the substrate during the same process as forming the source and drain electrodes in contact with the first to third active patterns and the gate electrodes of the first to third active patterns. Array substrate manufacturing method for a liquid crystal display comprising a. The method of claim 7, wherein And forming a protective film on the entire surface of the substrate on which the first to third source electrodes and the first to third drain electrodes are formed, and patterning the same, to expose a signal input pad formed on the outer side of the substrate. Method of manufacturing array substrate for liquid crystal display device. The method of claim 6, The concentration of the n + ions is 2.5 times or more of the p + ion concentration of the liquid crystal display array substrate manufacturing method The method of claim 6, And the first to third active patterns are formed by patterning a polycrystalline silicon layer. The method of claim 6, And wherein the interlayer insulating film is formed by sequentially stacking an oxide film layer (silicon oxide layer) and a nitride film layer (silicon nitride layer). The method of claim 6, And doping the p + ions, and then performing a hydrogenation process to remove surface defects of the first to third active patterns. The method of claim 6, And forming a side surface of the gate electrode positioned on the second active pattern in the fifth mask process. The method of claim 13, And a second source and a drain electrode in contact with the second active pattern are spaced apart from the exposed gate electrode.