KR20050002005A - Method for fabricating semiconductor device capable of forming storage node contact hole and insulating spacer of bit line - Google Patents

Abstract

PURPOSE: A semiconductor device fabricating method for simultaneously forming a storage node contact hole and a bitline insulation layer spacer is provided to decrease the number of processes by performing a tilted etch process in etching an interlayer dielectric for forming a storage node contact hole and by forming an insulation layer spacer on the sidewall of a bitline. CONSTITUTION: A bitline(22) is formed on a semiconductor substrate(20). A hard mask is formed on the bitline. An interlayer dielectric is formed on the resultant structure having the hard mask. The interlayer dielectric is selectively etched to form a storage node contact hole exposing the semiconductor substrate while the interlayer dielectric is left on the sidewall of the bitline to form an insulation layer spacer(24A).

Description

A method for fabricating a semiconductor device for simultaneously forming a storage node contact hole and a bit line insulating layer spacer {Method for fabricating semiconductor device capable of forming storage node contact hole and insulating spacer of bit line}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for simultaneously forming a storage node contact hole and a bit line insulating spacer.

As semiconductor devices become more integrated and faster, securing a contact process margin is an urgent problem, and a device having a high signal transmission speed is required for rapid processing of information. A contact hole is formed to electrically connect the lower conductive layer and the upper conductive layer, and the landing plug contact (LPC) is formed in order to fill the contact hole well by reducing the size of the contact hole according to the high integration of the device. The method of forming is applied. In addition, in order to implement a high speed device, a conductive layer applied to a semiconductor device such as a word line, a bit line, a capacitor, a metal wiring, or the like is formed using a metal having excellent electrical conductivity. On the other hand, as semiconductor devices are highly integrated and the aspect ratio of contact holes increases, the alignment margin of the mask process decreases, thereby preventing self-aligned contact etching to prevent contact failure. SAC) is applied.

Hereinafter, a semiconductor device manufacturing method according to the related art will be described with reference to FIGS. 1A and 1B.

FIG. 1A shows a first interlayer insulating film 11 covering a lower structure formed on a semiconductor substrate 10, a bit line 12 on a first interlayer insulating film 11, and then the bit line 12. It is shown that the nitride film hard mask 13 is formed on the () and the nitride film spacer 13 is formed on the sidewall of the bit line 12.

FIG. 1B selectively removes an interlayer insulating layer on the semiconductor substrate 10 by a SAC etching process to expose a portion of the semiconductor substrate 10 to be connected to the storage node electrode and to expose the storage node contact plug 15 on the exposed semiconductor substrate 10. ) Is shown.

The nitride hard mask 13 and the nitride spacer 13 formed on the bit line 12 and the sidewalls of the bit line 12 respectively prevent the bit line 12 from being damaged in the above-described SAC etching process.

Meanwhile, as semiconductor devices are highly integrated, it is difficult to obtain a desired capacitance and to implement a reproducible capacitor. Moreover, reproducible capacitor implementation is more difficult when the parasitic capacitance of the bitline is increased.

In the above-described conventional semiconductor device manufacturing process, since the spacers are formed on the sidewalls of the bitline using a nitride film having a relatively high dielectric constant, the bitline capacitance is increased, and thus, it is difficult to implement an appropriately reproducible capacitor.

In addition, since an insulating film deposition and etching process for forming a spacer on the sidewall of the bit line must be necessarily accompanied, there is a problem in that the process is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of fabricating a semiconductor device for simultaneously forming storage node contact holes and bit line insulating spacers in order to reduce parasitic capacitance of bit lines and to facilitate the process. have.

1A and 1B illustrate a semiconductor device manufacturing process according to the prior art.

2A to 2E are diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.

* Explanation of reference numerals for the main parts of the drawings

20: silicon substrate 21, 24: interlayer insulating film

22: bit line 23: nitride film hard mask

24A and 24B: insulating film spacer

The present invention for achieving the above object, forming a bit line on a semiconductor substrate; Forming a hard mask on the bit line; Forming an interlayer insulating film on the entire structure where the hard mask is formed; And forming an insulating layer spacer by selectively etching the interlayer insulating layer to form a storage node contact hole exposing the semiconductor substrate, and leaving the interlayer insulating layer on the sidewall of the bit line. .

In addition, the present invention for achieving the above object comprises the steps of forming a first interlayer insulating film covering the underlying structure formed on the semiconductor substrate; Forming a bit line on the first interlayer insulating film; Forming a hard mask on the bit line; Forming a second interlayer insulating film on the entire structure where the hard mask is formed; And selectively forming the storage node contact hole to expose the semiconductor substrate by selectively etching the second interlayer insulating layer and the first interlayer insulating layer, and leaving the second interlayer insulating layer on the sidewall of the bit line to form an insulating layer spacer. It provides a semiconductor device manufacturing method comprising a.

The present invention is characterized by reducing the process step by forming an insulating film spacer on the sidewall of the bit line in the interlayer insulating film etching process for forming the storage node contact hole. In addition, by forming the interlayer dielectric layer as an oxide film, an oxide spacer is formed on the sidewalls of the bit lines to further reduce the bit line parasitic capacitance.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2A is a plan view illustrating an arrangement of the semiconductor substrate 20, the bit lines 22, the storage node contact mask M1, and the storage node contact plug 25.

Hereinafter, the present invention will be described with reference to FIGS. 2B to 2E, which are cross-sectional views along the line AA ′ of FIG. 2A.

First, as shown in FIG. 2B, the bit line 22 is formed on the first interlayer insulating layer 21 covering the underlying structure formed on the semiconductor substrate 20, and the nitride film hard mask 23 is formed on the bit line 22. And a second interlayer insulating film 24 on the entire structure.

The bit line 22 is formed by forming a diffusion barrier film with a Ti / TiN laminated film having a thickness of 100 mW to 1000 mW, and depositing and etching a W film having a thickness of 500 mW to 1500 mW on the diffusion barrier. The W film is etched by applying a power of 300 W to 1000 W at a pressure of 20 mTorr to 70 mTorr with a mixed gas of SF ₆ , BCl ₃ , N _2, and Cl ₂ . On the other hand, the nitride film hard mask 23 on the bit line 22 forms a nitride film having a thickness of 2000 kPa to 4000 kPa, and is a mixed gas of CF ₄ , CHF ₃ , O _2, and Ar at a pressure of 20 mTorr to 70 mTorr. Is formed by etching the nitride film under a power condition of 300 W to 1000 W. The second interlayer insulating film is formed of an oxide film having a thickness of 4000 kPa to 10000 kPa.

Next, a storage node contact mask M shown in FIG. 2A is formed on the second interlayer insulating film 24, and as shown in FIG. 2B, the second interlayer insulating film 24 and the first interlayer insulating film 21 are formed. Is selectively etched to form a storage node contact hole exposing the semiconductor substrate 20, and a second interlayer insulating film is left on the sidewall of the bit line 22 to form an insulating film spacer 24A. The storage node contact mask is then removed.

Before forming the first etching mask M1, an organic anti-reflection coating having a thickness of 500 μm to 1000 μm may be formed on the second interlayer insulating layer 24. Etching of the organic antireflection film is performed under conditions having a selectivity of 3: 1 or more with respect to the lower interlayer insulating film. In an embodiment of the present invention, the organic antireflection film is etched by applying power of 1000 W to 1800 W at a pressure of 30 mTorr to 60 mTorr using Co, Ar, and O ₂ mixed gases.

The storage node contact hole is a mixed gas of any one of C ₄ F ₈ , C ₅ F _8, and C ₄ F ₆ and CH ₂ F ₂ , Ar, O ₂ , Co, and N ₂ , and has a pressure of 1000 to 10 mTorr to 70 mTorr. The second interlayer insulating film 24 and the first interlayer insulating film 21 are formed by etching under a power condition of W to 2000W.

After removing the storage node contact mask, a polymer formed during etching is removed using a mixed solution of H ₂ SO ₄ and H ₂ O ₂ .

Meanwhile, an additional etching process may be performed to form a narrow insulating layer spacer 24B on the sidewall of the bit line 22 and to expand the width of the storage node contact hole, as shown in FIG. 2D. At this time, any one of C ₄ F ₈ , C ₅ F ₈ and C ₄ F ₆ and a mixed gas of CH ₂ F ₂ , Ar, O ₂ , Co and N ₂ 500 W to 1000 W at a pressure of 10 mTorr to 60 mTorr The interlayer insulating film 22 is etched under the power condition of.

Next, as shown in FIG. 2E, a polysilicon film is formed on the entire structure and chemical mechanical polishing is performed to form the plug 25 in the storage node contact hole.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention as described above can reduce the process step by forming a bit line spacer as an interlayer insulating film remaining on the sidewall of the bit line in the self-aligned contact etching process for forming the storage node contact. In addition, since the bit line spacer may be formed of an oxide layer forming an interlayer insulating layer, the bit line parasitic capacitance may be reduced, thereby realizing a reproducible capacitor.

Claims (8)

Forming a bit line on the semiconductor substrate; Forming a hard mask on the bit line; Forming an interlayer insulating film on the entire structure where the hard mask is formed; And Selectively etching the interlayer insulating layer to form a storage node contact hole exposing the semiconductor substrate, and leaving the interlayer insulating layer on the sidewall of the bit line to form an insulating layer spacer Semiconductor device manufacturing method comprising a. The method of claim 1, The interlayer insulating film is formed of an oxide film, The hard mask is formed of a nitride film. Forming a first interlayer insulating film covering the underlying structure formed on the semiconductor substrate; Forming a bit line on the first interlayer insulating film; Forming a hard mask on the bit line; Forming a second interlayer insulating film on the entire structure where the hard mask is formed; And Selectively etching the second interlayer insulating layer and the first interlayer insulating layer to form a storage node contact hole exposing the semiconductor substrate, and leaving the second interlayer insulating layer on sidewalls of the bit line to form an insulating layer spacer. Semiconductor device manufacturing method comprising a. The method of claim 3, wherein Each of the first interlayer insulating film and the second interlayer insulating film is formed of an oxide film; The hard mask is formed of a nitride film. The method according to any one of claims 1 to 4, After the insulating film spacer forming step, And performing an additional etching process to reduce the width of the insulation spacer and to increase the area of the storage node contact hole. The method of claim 5, wherein After the insulating film spacer forming step or the additional etching process step, And forming a plug in the storage node contact hole. The method of claim 5, wherein The storage node contact hole is a mixture of CH ₂ F ₂ , Ar, O ₂ , Co and N ₂ with any one of C ₄ F ₈ , C ₅ F ₈ and C ₄ F ₆ , and a pressure of 10 mTorr to 70 mTorr and 1000 A semiconductor device manufacturing method, characterized in that formed under the power conditions of W to 2000W. The method of claim 5, wherein The additional etching process, Any of C ₄ F ₈ , C ₅ F ₈ and C ₄ F ₆ with a mixture of CH ₂ F ₂ , Ar, O ₂ , Co and N ₂ , 10 mTorr to 60 mTorr pressure and 500 W to 1000 W The semiconductor device manufacturing method characterized by the above-mentioned.