KR100440076B1 - Forming method for self aligned contact of semiconductor device - Google Patents
Forming method for self aligned contact of semiconductor device Download PDFInfo
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- KR100440076B1 KR100440076B1 KR10-1999-0048290A KR19990048290A KR100440076B1 KR 100440076 B1 KR100440076 B1 KR 100440076B1 KR 19990048290 A KR19990048290 A KR 19990048290A KR 100440076 B1 KR100440076 B1 KR 100440076B1
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- 239000010410 layer Substances 0.000 claims abstract description 37
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 74
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- -1 CH 3 F Chemical class 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
본 발명은 반도체소자의 자기정렬적인 콘택 형성방법에 관한 것으로,The present invention relates to a method for forming a self-aligned contact of a semiconductor device,
반도체기판 상부에 도전배선용 도전층을 형성하고 그 상부에 마스크절연막인 제1 카본함유 실리콘산화질화막을 형성하여 적층구조를 형성하고 상기 적층구조를 도전배선 마스크를 이용하여 패터닝하고 그 측벽에 제2 카본함유 실리콘산화질화막 스페이서를 형성한 다음, 전체표면상부에 층간절연막을 형성하고 상기 층간절연막을 콘택마스크를 이용한 사진식각공정으로 식각하여 콘택홀을 형성함으로써 질화막의 응력으로 인한 웨이퍼의 뒤틀림이나 박막의 리프팅 현상을 방지하고, 접합누설전류의 발생을 감소시킬 수 있고, 높은 유전율에 의한 기생 캐패시턴스의 증가를 방지할 수 있고, 산화막인 층간절연막 식각공정시 고 선택비를 확보할 수 있어 SAC 특성을 향상시킬 수 있으며 별도의 반사방지막을 필요로 하지 않는 기술에 관한 것이다.A conductive layer for conductive wiring is formed on the semiconductor substrate, and a first carbon-containing silicon oxynitride film, which is a mask insulating film, is formed on the semiconductor substrate to form a stacked structure. The stacked structure is patterned by using a conductive wiring mask, and the second carbon is formed on the sidewall thereof. After forming the silicon oxynitride-containing spacers, an interlayer insulating film is formed on the entire surface, and the interlayer insulating film is etched by a photolithography process using a contact mask to form contact holes. It is possible to prevent the phenomenon, reduce the occurrence of junction leakage current, prevent the increase of parasitic capacitance due to high dielectric constant, and secure high selectivity in the interlayer insulating film etching process, which is an oxide film, to improve SAC characteristics. And a technology that does not require a separate antireflection film.
Description
본 발명은 반도체소자의 자기정렬적인 콘택 형성방법에 관한 것으로, 특히 카본 함유 실리콘산화질화막 ( C-contain SiON ) 을 식각장벽으로 하여 자기정렬적인 콘택홀을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming self-aligned contacts in semiconductor devices, and more particularly, to a technique for forming self-aligned contact holes using a carbon-containing silicon oxynitride film (C-contain SiON) as an etch barrier.
일반적으로, 메모리 소자에서 중요한 특성인 리프레쉬 타임 ( refresh time ) 은 주로 저장전극 노드와 트랜지스터의 드레인을 연결하는 저장전극 콘택공정시 상기 드레인이 손상되어 발생되는 누설전류에 의하여 결정된다.In general, a refresh time, which is an important characteristic of a memory device, is mainly determined by a leakage current generated by damaging the drain during a storage electrode contact process connecting the storage electrode node and the drain of the transistor.
현재 사용되고 있는 노광기술로는 16 M DRAM 까지 콘택홀을 형성할 때 콘택홀 측벽의 도전층과 절연불량이 발생하지 않고 소자를 형성할 수 있으나, 소자가 고집적화됨에 따라 단위셀의 크기가 축소되고, 그에 따라서 콘택홀과 도전층의 간격이 좁아지게 된다.In the current exposure technology, when forming a contact hole up to 16 M DRAM, a device can be formed without a poor insulation with the conductive layer of the sidewall of the contact hole. However, as the device is highly integrated, the unit cell size is reduced. As a result, the gap between the contact hole and the conductive layer is narrowed.
상기와 같이 좁아진 콘택홀을 형성하기 위하여 콘택의 크기를 축소시켜야 하고, 이를 위하여 노광방식을 바꾸거나, 마스크를 바꾸어서 어느 정도는 해결할 수 있었다. 또한, 자기정렬적인 콘택 ( self-aligned contact, 이하에서 SAC 라 함 ) 으로 이를 해결하기도 하였다.In order to form a narrowed contact hole as described above, the size of the contact should be reduced, and for this purpose, it was solved to some extent by changing the exposure method or changing the mask. In addition, self-aligned contact (hereafter referred to as SAC) was solved.
한편, SAC 공정중 가장 각광받는 것으로 산화막 식각공정시 식각장벽으로 질화막을 사용하는 자기정렬적인 콘택 ( nitride barrier SAC, 이하에서 NBSAC 이라 함 ) 공정을 사용한다.On the other hand, the most popular among the SAC process is a self-aligned contact (nitride barrier SAC, hereinafter referred to as NBSAC) process using a nitride film as an etching barrier during the oxide film etching process.
도 1 은 종래기술에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a method for forming a self-aligned contact of a semiconductor device according to the prior art.
먼저, 반도체기판(31) 상부에 게이트전극용 도전층(33)을 형성하고 그 상부에 마스크절연막인 제1실리콘질화막(35)을 형성한다.First, a conductive layer 33 for a gate electrode is formed on the semiconductor substrate 31, and a first silicon nitride film 35, which is a mask insulating film, is formed on the semiconductor substrate 31.
그리고, 상기 제1실리콘질화막(35) 상부에 반사방지막으로 실리콘산화질화막(39)을 형성한다.A silicon oxynitride layer 39 is formed on the first silicon nitride layer 35 as an antireflection layer.
그리고, 게이트전극 마스크를 이용한 식각공정으로 상기 반사방지막인 실리콘산화질화막(39), 마스크절연막인 제1실리콘질화막(35)과 게이트전극용 도전층(33)을 식각하여 게이트전극을 형성한다.In addition, the gate electrode is formed by etching the silicon oxynitride layer 39, which is an antireflection film, the first silicon nitride layer 35, which is a mask insulating layer, and the conductive layer 33 for the gate electrode, by an etching process using a gate electrode mask.
여기서, 상기 반사방지막은 노광공정시 마스크절연막으로 사용되는 실리콘질화막의 난반사가 심하여 고집적화된 반도체소자의 제조공정에서는 반드시 필요한 박막이다.Here, the anti-reflection film is a thin film which is essential in the manufacturing process of the highly integrated semiconductor device due to severe diffused reflection of the silicon nitride film used as the mask insulating film during the exposure process.
그 다음, 상기 게이트전극 측벽에 제2실리콘질화막(37)으로 절연막 스페이서를 형성한다.Next, an insulating film spacer is formed on the sidewalls of the gate electrode with the second silicon nitride film 37.
그리고, 전체표면상부를 평탄화시키는 층간절연막(41)을 형성한다. 이때, 상기 층간절연막(41)은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ) 와 같이 유동성우 우수한 절연물질로 형성한다.Then, an interlayer insulating film 41 is formed to planarize the entire upper surface portion. At this time, the interlayer insulating film 41 is made of B.S.G. It is formed of an insulating material with excellent fluidity, such as boro phospho silicate glass (hereinafter referred to as BPSG).
그 다음, 상기 반도체기판(31)의 예정된 부분을 노출시키는 자기정렬적인 콘택공정으로 콘택홀(43)을 형성한다. (도 1)Next, the contact hole 43 is formed by a self-aligned contact process that exposes a predetermined portion of the semiconductor substrate 31. (Figure 1)
상기한 바와같이 종래기술에 따른 자기정렬적인 콘택공정은, 마스크절연막이나 절연막 스페이서로 사용되는 실리콘질화막의 큰 응력 ( stress ) 로 인하여 웨이퍼의 뒤틀림 현상이 유발될 수 있고 그로인한 도전층의 리프팅 ( lifting ) 등의현상이 발생한다. 그리고, 그에 따른 후속 리소그래피 ( lithography ) 공정을 어렵게 하는 문제점이 있다.As described above, the self-aligned contact process according to the prior art may cause warpage of the wafer due to the large stress of the silicon nitride film used as the mask insulating film or the insulating film spacer, thereby lifting the conductive layer. ) Occurs. And, there is a problem that makes subsequent lithography processes difficult.
그리고, 상기 실리콘질화막은 높은 유전율을 가지고 있어 도전층의 주변에 형성되어 높은 기생 캐패시턴스를 가지게 됨으로써 소자의 특성을 열화시킬 수 있는 문제점이 있다.In addition, the silicon nitride film has a high dielectric constant and is formed around the conductive layer to have a high parasitic capacitance, thereby degrading device characteristics.
그리고, 상기 실리콘질화막은 난반사가 심하여 그 상부에 반사방지막을 반드시 필요로 하게 되어 공정이 복잡해지는 문제점이 있다.In addition, since the silicon nitride film has severe diffused reflections, an antireflection film is necessarily required on the upper portion thereof, which causes a complicated process.
최근에는, 상기한 여러가지 문제점을 해결하기 위하여 실리콘질화막보다 응력이 작고, 유전율이 작으며 반사방지막의 적층이 필요없는 실리콘 리치 실리콘산화질화막을 마스크절연막과 절연막 스페이서로 사용한 자기정렬공정으로 콘택공정을 실시하였다. 이때, 상기 실리콘 리치 실리콘산화질화막은 실리콘이 20 퍼센트의 부피비로 함유된 것이다.Recently, in order to solve the various problems described above, a contact process is carried out in a self-aligning process using a silicon rich silicon oxynitride film as a mask insulating film and an insulating film spacer, which has a smaller stress, a smaller dielectric constant, and does not require the lamination of an antireflection film. It was. At this time, the silicon rich silicon oxynitride film is a silicon containing 20% by volume ratio.
그러나, 상기 실리콘리치 실리콘산화질화막은 실리콘질화막에 비하여 전기적특성이 떨어져 종래보다 누설전류가 증가되는 문제점이 유발되었다.However, the silicon rich silicon oxynitride film has a lower electrical characteristic than the silicon nitride film, resulting in a problem of increased leakage current.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 카본이 함유된 실리콘산화질화막을 이를 이용하여 용이하게 자기정렬적인 콘택 식각공정을 실시할 수 있도록 하는 반도체소자의 자기정렬적인 콘택 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming a self-aligned contact of a semiconductor device that can easily perform a self-aligned contact etching process using a silicon oxynitride film containing carbon to solve the above problems of the prior art. Its purpose is to.
도 1 은 종래기술에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도.1 is a cross-sectional view showing a self-aligned contact forming method of a semiconductor device according to the prior art.
도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도.2A and 2B are cross-sectional views illustrating a method for forming self-aligned contacts in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 게이트전극용 도전층11,31: semiconductor substrate 13,33: gate electrode conductive layer
15 : 제1 카본함유 실리콘산화질화막15: first carbon-containing silicon oxynitride film
17 : 제2 카본함유 실리콘산화질화막17: second carbon-containing silicon oxynitride film
19,41 : 층간절연막, 산화막19,41: interlayer insulating film, oxide film
21 : 감광막패턴21: photosensitive film pattern
23,43 : 콘택홀23,43: contact hole
35 : 제1실리콘질화막 37 : 제2실리콘질화막35: first silicon nitride film 37: second silicon nitride film
39 : 실리콘리치 실리콘산화질화막39: silicon rich silicon oxynitride film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 자기정렬적인 콘택 형성방법은,반도체기판 상부에 도전배선용 도전층을 형성하고 그 상부에 마스크절연막인 제1 카본함유 실리콘산화질화막을 형성하여 적층구조를 형성하는 공정과,상기 적층구조를 도전배선 마스크를 이용하여 패터닝하고 그 측벽에 제2 카본함유 실리콘산화질화막 스페이서를 형성하는 공정과,전체표면상부에 층간절연막을 형성하는 공정과,In order to achieve the above object, the self-aligned contact forming method of a semiconductor device according to the present invention comprises forming a conductive wiring conductive layer on a semiconductor substrate and forming a first carbon-containing silicon oxynitride layer, which is a mask insulating layer, on the semiconductor substrate. Forming a second carbon-containing silicon oxynitride film spacer on the sidewalls of the layered structure using a conductive wiring mask; forming an interlayer insulating film over the entire surface;
상기 카본 함유 실리콘산화질화막과 식각선택비 차이를 확보할 수 있는 C-F 계 플라즈마를 이용한 자기정렬적인 콘택식각공정으로 상기 층간절연막을 식각하여 콘택홀을 형성하는 공정을 포함하는 것을 제1특징으로한다.The self-aligned contact etching process using a C-F-based plasma that can secure the difference in etching selectivity with the carbon-containing silicon oxynitride film is a first feature comprising the step of forming a contact hole by etching the interlayer insulating film.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 자기정렬적인 콘택 형성방법은,Self-aligned contact forming method of a semiconductor device according to the present invention to achieve the above object,
반도체기판 상부에 도전배선용 도전층을 형성하고 그 상부 및 측벽에 산화막으로 마스크절연막 및 측벽 스페이서를 형성하는 공정과,Forming a conductive wiring conductive layer on the semiconductor substrate and forming a mask insulating film and sidewall spacers with oxide films on the upper and sidewalls thereof;
전체표면상부에 카본함유 실리콘산화질화막으로 식각장벽층을 형성하는 공정과,Forming an etch barrier layer on the entire surface with a silicon-containing silicon oxynitride film;
전체표면상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;
상기 층간절연막과 카본함유 실리콘산화질화막을 순차적으로 식각하여 상기 반도체기판의 콘택 예정부분을 노출시키는 자기정렬적인 콘택공정을 실시하는 공정과,Performing a self-aligned contact process of sequentially etching the interlayer insulating film and the carbon-containing silicon oxynitride film to expose a predetermined contact portion of the semiconductor substrate;
상기 카본함유 실리콘산화질화막 식각공정시 유발되는 폴리머를 등방성 건식식각공정으로 제거하는 공정을 포함하는 것을 제2특징으로한다.A second feature is to include a step of removing the polymer caused during the carbon-containing silicon oxynitride film etching process by an isotropic dry etching process.
이하, 첨부된 도면을 참고로 하여 본 발명은 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 워드라인, 즉 게이트전극용 도전층(13), 제1 카본함유 실리콘산화질화막(15)을 전체표면상부에 적층한다.First, a word line, that is, a conductive layer 13 for a gate electrode, and a first carbon-containing silicon oxynitride film 15 are stacked on the entire surface of the semiconductor substrate 11.
그리고, 게이트전극 마스크(도시안됨)를 이용한 사진식각공정으로 상기 적층구조를 패터닝한다. 이때, 상기 제1 카본함유 실리콘산화질화막(15)은 게이트전극용 도전층(13)의 도전특성을 보호하기 위한 마스크절연막으로 사용된 것이다.The stacked structure is patterned by a photolithography process using a gate electrode mask (not shown). In this case, the first carbon-containing silicon oxynitride film 15 is used as a mask insulating film for protecting the conductive properties of the gate electrode conductive layer 13.
그 다음, 상기 제1 카본함유 실리콘산화질화막(15) 측벽에 제2 카본함유 실리콘산화질화막(17) 스페이서를 형성한다.Next, a spacer of the second carbon-containing silicon oxynitride layer 17 is formed on the sidewall of the first carbon-containing silicon oxynitride layer 15.
이때, 상기 제2 카본함유 실리콘산화질화막(17) 스페이서는 전체표면상부에 제2 카본함유 실리콘산화질화막(17)을 일정두께 형성하고 이를 이방성식각하여 형성한다.In this case, the second carbon-containing silicon oxynitride film 17 spacer is formed by forming a second carbon-containing silicon oxynitride film 17 a predetermined thickness on the entire surface and anisotropically etching it.
여기서, 상기 제1,2 카본함유 실리콘산화질화막(15,17)은 함유되는 카본의 함유량을 임의로 조절하여 식각선택비를 향상시킬 수 있도록 할 수 있다.Here, the first and second carbon-containing silicon oxynitride films 15 and 17 may be controlled to improve the etching selectivity by arbitrarily adjusting the content of carbon.
그리고, 상기 제1,2 카본함유 실리콘산화질화막(15,17)은 산소와 질소의 비를 임의로 조절하여 식각선택비를 향상시킬 수도 있다.In addition, the first and second carbon-containing silicon oxynitride films 15 and 17 may improve the etching selectivity by arbitrarily adjusting the ratio of oxygen and nitrogen.
그 다음, 전체표면상부에 층간절연막(19)을 형성한다. 이때, 상기 층간절연막(19)은 산화막으로 형성한다.Then, an interlayer insulating film 19 is formed over the entire surface. In this case, the interlayer insulating film 19 is formed of an oxide film.
그리고, 상기 층간절연막(19) 상부에 감광막패턴(21)을 형성한다. 이때, 상기 감광막패턴(21)은 전체표면상부에 감광막을 도포하고 이를 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 패터닝하여 형성한다. (도 2a)A photosensitive film pattern 21 is formed on the interlayer insulating film 19. In this case, the photoresist pattern 21 is formed by coating a photoresist on the entire surface and patterning the photoresist by exposure and development using a contact mask (not shown). (FIG. 2A)
그 다음, 상기 감광막패턴(21)을 마스크로하여 상기 층간절연막(19)을 식각함으로써 상기 반도체기판(11)의 예정된 영역을 노출시키는 콘택홀(23)을 형성한다.Next, the interlayer insulating layer 19 is etched using the photoresist pattern 21 as a mask to form a contact hole 23 exposing a predetermined region of the semiconductor substrate 11.
이때, 상기 층간절연막(19)의 식각공정은 C-F 계 가스 플라즈마를 이용하여 실시하되, C/F 비가 커서 상기 비정질 카본막(19)과 용이하게 고선택비 확보할 수 있는 C2F6, C3F8, C4F8, C5F8또는 C4F6등의 가스를 이용하여 실시한다.In this case, the etching process of the interlayer insulating film 19 is performed using a CF-based gas plasma, but C 2 F 6 , C which can easily secure a high selectivity with the amorphous carbon film 19 because the C / F ratio is large. 3 F 8 , C 4 F 8 , C 5 F 8 or C 4 F 6 or the like.
또한, 식각선택비를 증가시키기 위하여 CH3F, CH2F2, C2HF5또는 C3H2F6등과 같이 수소가 함유된 C-H-F 계 가스를 첨가하여 실시할 수도 있다.In addition, in order to increase the etching selectivity, it may be carried out by adding a CHF-based gas containing hydrogen, such as CH 3 F, CH 2 F 2 , C 2 HF 5 or C 3 H 2 F 6 .
그리고, 상기한 PECVD 산화막(21)의 식각공정시 플라즈마를 안정화시키기 위하여 아르곤이나 헬륨과 같은 비활성가스를 첨가하여 실시할 수도 있다.In addition, in order to stabilize the plasma during the etching process of the PECVD oxide film 21, an inert gas such as argon or helium may be added.
그 다음, 남아있는 상기 감광막패턴(21)을 제거한다. (도 2b)Then, the remaining photoresist pattern 21 is removed. (FIG. 2B)
본 발명의 다른 실시예는 워드라인의 상부 및 측벽에 형성되는 마스크절연막이나 측벽 절연막 스페이서를 산화막으로 형성하는 경우로서, 마스크절연막과 절연막 스페이서가 형성된 전체표면상부에 식각장벽층을 형성하되, 카본 함유 실리콘산화질화막으로 형성하는 것이다.Another embodiment of the present invention is to form a mask insulating film or sidewall insulating spacer formed on the top and sidewalls of the word line as an oxide film, wherein an etch barrier layer is formed on the entire surface where the mask insulating layer and the insulating film spacer are formed, but containing carbon It is formed of a silicon oxynitride film.
상기 다른 실시예를 보다 구체적으로 설명하면 다음과 같다.The other embodiments will be described in more detail as follows.
상기 식각장벽층이 형성된 반도체기판 상부에 층간절연막을 형성하고 그 상부에 콘택용 감광막패턴을 형성한다.An interlayer insulating film is formed on the semiconductor substrate on which the etch barrier layer is formed, and a contact photoresist pattern is formed on the insulating substrate.
그리고, 상기 감광막패턴을 마스크로하여 상기 층간절연막을 식각하여 상기 식각장벽층인 카본함유 실리콘산화질화막을 노출시킨다.The interlayer insulating film is etched using the photosensitive film pattern as a mask to expose the carbon-containing silicon oxynitride film as the etch barrier layer.
그리고, 상기 카본 함유 실리콘산화질화막을 습식 또는 건식 등방성 식각공정으로 콘택영역에 위치한 카본함유 실리콘산화질화막을 제거하여 콘택홀을 형성한다.The carbon-containing silicon oxynitride layer is wet or dry isotropically etched to remove the carbon-containing silicon oxynitride layer located in the contact region to form a contact hole.
그 다음, 상기 카본함유 실리콘산화질화막으로 인하여 상기 콘택홀 영역에 남아있는 폴리머를 등방성 건식식각방법으로 제거한다. 이때, 상기 등방성 건식식각방법은 F 또는 Cl 를 함유하는 플라즈마를 이용하여 실시한다.Then, the polymer remaining in the contact hole region due to the carbon-containing silicon oxynitride film is removed by an isotropic dry etching method. At this time, the isotropic dry etching method is performed using a plasma containing F or Cl.
아울러, 본 발명은 반도체소자에 구비되는 다른 도전층, 즉 비트라인에 적용하여 실시할 수도 있다.In addition, the present invention may be applied to other conductive layers, that is, bit lines, provided in the semiconductor device.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 자기정렬적인 콘택 형성방법은, 질화막의 응력으로 인한 웨이퍼의 뒤틀림이나 박막의 리프팅 현상을 방지하고 별도의 반사방지막을 필요로 하지 않으며 접합누설전류의 발생을 감소시킬 수 있고 높은 유전율에 의한 기생 캐패시턴스의 증가를 방지할 수 있고, 산화막인 층간절연막 식각공정시 고 선택비를 확보할 수 있어 SAC 특성을 향상시킬 수 있는 효과가 있다.As described above, the self-aligned contact forming method of the semiconductor device according to the present invention prevents warping of the wafer or lifting of the thin film due to the stress of the nitride film, does not require a separate anti-reflection film, and generates a junction leakage current. It is possible to reduce the parasitic capacitance and increase the parasitic capacitance due to the high dielectric constant, and to secure a high selectivity during the interlayer insulating film etching process, which is an oxide film, thereby improving SAC characteristics.
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