KR20040049419A - Non-volatile memory and fabrication method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 88
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 108010033145 microsomal ethanol-oxidizing system Proteins 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
Description
본 발명은 반도체 소자에 관한 것으로, 더욱 상세하게는 비휘발성 메모리 장치를 제조하는 방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a nonvolatile memory device.
일반적으로 반도체 메모리 장치는 크게 휘발성 메모리 장치와 비휘발성 메모리 장치로 구분된다. 휘발성 메모리 장치는 디램(DRAM : dynamic random access memory), 에스램(SRAM : static random access memory) 등의 램(RAM)이 대부분을 차지하고 있는 것으로서, 전원 인가시 데이터의 입력 및 보존이 가능하지만, 전원 제거시 데이터가 휘발되어버려 보존이 불가능한 특징을 가진다.Generally, semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices occupy most of RAM, such as dynamic random access memory (DRAM) and static random access memory (SRAM), and can input and store data when power is applied. When removed, data is volatilized and cannot be preserved.
반면에, 비휘발성 메모리 장치는 롬(ROM : read only memory)이 대부분을 차지하고 있는 것으로서, 전원이 인가되지 않아도 데이터가 보존되는 특징을 가진다.On the other hand, nonvolatile memory devices occupy most of read only memory (ROM), and have a feature that data is preserved even when power is not applied.
현재, 공정기술 측면에서 비휘발성 메모리 장치는 플로팅 게이트(floating gate) 계열과, 두 종류 이상의 유전막이 2층 또는 3층으로 적층된 엠아이에스(MIS : metal insulator semiconductor) 계열로 구분된다.Currently, non-volatile memory devices are classified into a floating gate series and a metal insulator semiconductor (MIS) series in which two or more dielectric layers are stacked in two or three layers.
플로팅 게이트 계열의 비휘발성 메모리 장치는 전위우물(potential well)을 이용하여 기억 특성을 구현하며, 현재 플래쉬 이이프롬(EEPROM : electrically erasable programmable read only memory)으로 가장 널리 응용되고 있는 이티오엑스(ETOX : EPROM tunnel oxide) 구조가 대표적이다.Floating gate-type nonvolatile memory devices implement memory characteristics using potential wells, and are most widely used as an electrically erasable programmable read only memory (EEPROM). tunnel oxide) structure is typical.
반면에, MIS 계열의 비휘발성 메모리 장치는 유전막 벌크, 유전막과 유전막 사이의 계면, 그리고 유전막과 반도체 사이의 계면에 존재하는 트랩(trap)을 이용하여 기억 기능을 수행한다. 현재 EEPROM으로 주로 응용되고 있는 엠오엔오에스/에스오엔오에스(MONOS/SONOS : metal/silicon ONO semiconductor) 구조가 대표적이다.On the other hand, MIS-based nonvolatile memory devices perform a memory function by using traps present at the bulk of the dielectric film, the interface between the dielectric film and the dielectric film, and the interface between the dielectric film and the semiconductor. One of the most typical of these is the structure of MEOS / SONOS (metal / silicon ONO semiconductor), which is mainly applied as EEPROM.
도 1은 종래 SONOS 구조의 비휘발성 메모리 장치를 도시한 단면도로서, 이에 도시된 바와 같이, 반도체 기판(1) 내에 인(P)을 주입하여 제1반도체영역(2)을 형성하고, 그 위에 산화막/질화막/산화막의 적층구조인 ONO층(3)을 형성한 후, ONO층(3) 위에 다결정 실리콘층(4)을 형성함으로써. 반도체/ONO/반도체 구조인 SONOS 구조를 완성하였다.FIG. 1 is a cross-sectional view of a nonvolatile memory device having a conventional SONOS structure. As shown in the drawing, phosphorus (P) is injected into a semiconductor substrate 1 to form a first semiconductor region 2, and an oxide film thereon. By forming the polycrystalline silicon layer 4 on the ONO layer 3 after forming the ONO layer 3 which is a laminated structure of the / nitride film / oxide film. The SONOS structure, which is a semiconductor / ONO / semiconductor structure, was completed.
이러한 종래 SONOS 구조의 비휘발성 메모리 장치 제조 방법에서는 제1반도체영역(2)을 형성할 때 인 이온의 주입량 및 주입에너지를 적절히 조절하여 구동전압을 조절하는데, 이러한 인의 주입공정 중에 실리콘 기판이 손상되어 결과적으로 소자의 오동작을 유발하는 등의 문제점이 있었다.In the conventional method of manufacturing a non-volatile memory device having a SONOS structure, the driving voltage is controlled by appropriately adjusting the implantation amount and implantation energy of phosphorus ions when the first semiconductor region 2 is formed. As a result, there is a problem such as causing a malfunction of the device.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 SONOS 구조에서 최하층 반도체 영역을 형성할 때 반도체 기판이 손상되는 것을 방지하는 것이다.The present invention has been made to solve the above problems, and an object thereof is to prevent damage to the semiconductor substrate when forming the lowermost semiconductor region in the SONOS structure.
도 1은 종래 비휘발성 메모리 장치를 도시한 단면도이다.1 is a cross-sectional view illustrating a conventional nonvolatile memory device.
도 2a 내지 도 2e는 본 발명에 따른 비휘발성 메모리 장치의 제조 방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 반도체 기판 내에 인을 주입하는 대신에, 반도체 기판을 식각하여 트렌치를 형성한 후 트렌치 내에 p+다결정질 SiGe막을 매립하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, instead of implanting phosphorus into the semiconductor substrate, the semiconductor substrate is etched to form a trench, and then p + polycrystalline SiGe film is embedded in the trench.
즉, 본 발명에 따른 비휘발성 메모리 장치의 제조 방법은, 반도체 기판을 선택적으로 식각하여 트렌치를 형성하고, 트렌치를 제1도전형의 불순물이 도핑된 SiGe으로 매립하여 제1반도체영역을 형성하는 단계; 제1반도체영역을 포함하여 반도체 기판의 상부 전면에 게이트산화막, 제1폴리실리콘층, 제1절연막을 형성하고, 제1절연막, 제1폴리실리콘층, 및 게이트산화막을 선택적으로 식각하여 제1반도체영역을 노출시키는 단계; 노출된 제1반도체영역을 포함하여 제1절연막의 상부 전면에 제1산화막, 질화막, 및 제2산화막을 순차적으로 적층하고, 제2산화막 상에 다결정실리콘으로 이루어진 제2반도체영역을 형성하는 단계; 제2반도체영역, 제2산화막, 질화막, 및 제1산화막을 목적하는 제1게이트의 폭으로 남기도록 선택적 식각하는 단계; 제1절연막 및 제1폴리실리콘층을 선택적 식각하여 제2반도체영역, 제2산화막, 질화막, 및 제1산화막의 양측방에 각각 목적하는 제2게이트 및 제3게이트의 폭으로 남기는 단계; 및 제1폴리실리콘층의 양 외방에 위치하는 반도체 기판 내에 제2도전형의 불순물을 도핑하여 소스 및 드레인 영역을 형성하는 단계를 포함하여 이루어진다.That is, in the method of manufacturing a nonvolatile memory device according to the present invention, forming a trench by selectively etching a semiconductor substrate, and filling the trench with SiGe doped with impurities of a first conductivity type to form a first semiconductor region. ; A first oxide layer, a first polysilicon layer, and a first insulating layer are formed on the entire upper surface of the semiconductor substrate including the first semiconductor region, and the first insulating layer, the first polysilicon layer, and the gate oxide layer are selectively etched to form the first semiconductor. Exposing the area; Sequentially stacking a first oxide film, a nitride film, and a second oxide film on the entire upper surface of the first insulating layer including the exposed first semiconductor region, and forming a second semiconductor region made of polycrystalline silicon on the second oxide film; Selectively etching the second semiconductor region, the second oxide film, the nitride film, and the first oxide film to a width of a desired first gate; Selectively etching the first insulating layer and the first polysilicon layer to leave widths of the desired second and third gates on both sides of the second semiconductor region, the second oxide layer, the nitride layer, and the first oxide layer, respectively; And forming a source and a drain region by doping a second conductive type impurity into a semiconductor substrate positioned at both outer sides of the first polysilicon layer.
제1반도체영역을 형성할 때에는, SiGe을 증착하는 중에 제1도전형의 불순물을 도핑시킴으로써, 제1도전형의 불순물이 도핑된 다결정질의 SiGe을 제1트렌치에 매립하도록 증착하는 것이 바람직하고, SiGe의 증착 시에는 Si과 Ge의 비율이 9:1 내지 7:3 이 되도록 증착하며, SiGe의 증착 후에는 열처리를 수행하는 것이 바람직하다.When forming the first semiconductor region, it is preferable to deposit polycrystalline SiGe doped with the first conductivity type impurity in the first trench by doping the impurity of the first conductivity type during the deposition of SiGe. In the deposition of Si and Ge is deposited so that the ratio of 9: 1 to 7: 3, it is preferable to perform a heat treatment after the deposition of SiGe.
또한, 제1절연막, 제1폴리실리콘층, 및 게이트산화막을 선택적으로 식각하여 제1반도체영역을 노출시킬 때에는, 제1반도체영역의 폭보다 더 큰 폭으로 선택적 식각하여, 제1반도체영역과 이웃하는 반도체 기판을 소정폭 더 노출시키고, 노출된 제1반도체영역과 이웃하는 반도체 기판 내로 제1도전형의 불순물을 제1반도체영역에 도핑된 농도보다 저농도로 도핑하여 제1엘디디(LDD : lightly doped drain) 영역을 형성한 후, 노출된 제1반도체영역과 이웃하는 반도체 기판 상, 및 선택적 식각에 의해 노출된 제1폴리실리콘층 및 제1절연막의 측벽에 산화막으로 제1사이드월(side wall)을 형성하는 것이 바람직하다.In addition, when the first insulating layer, the first polysilicon layer, and the gate oxide film are selectively etched to expose the first semiconductor region, the first semiconductor region and the neighboring first semiconductor region are selectively etched by a width larger than the width of the first semiconductor region. The semiconductor substrate is exposed to a predetermined width, and the first conductive material is doped at a lower concentration than the concentration doped in the first semiconductor region into the exposed first semiconductor region and the first semiconductor region. After the doped drain region is formed, a first sidewall is formed on the exposed semiconductor substrate and the semiconductor substrate adjacent to the exposed first semiconductor region and on the sidewalls of the first polysilicon layer and the first insulating layer exposed by selective etching. Is preferably formed.
제1절연막 및 제1폴리실리콘층을 선택적 식각한 후에는, 제1폴리실리콘층의 양 외방에 위치하는 반도체 기판 내에 제2도전형의 불순물을 소스 및 드레인 영역에 도핑된 농도보다 저농도로 도핑하여 제2엘디디 영역을 형성한 후, 제1절연막 및제1폴리실리콘층의 양 외방 측벽에 산화막으로 제2사이드월을 형성하며, 소스 및 드레인 영역 형성을 위한 제2도전형의 불순물 도핑을 할 때에는 제2사이드월을 마스크로 하여 이온주입함으로써 도핑하는 것이 바람직하다.After the first insulating film and the first polysilicon layer are selectively etched, the second conductive dopant is doped at a lower concentration than that doped in the source and drain regions in the semiconductor substrate positioned on both outer sides of the first polysilicon layer. After the second LED region is formed, second sidewalls are formed on both outer sidewalls of the first insulating film and the first polysilicon layer by an oxide film, and when doping the second conductive type impurity to form the source and drain regions. Doping is preferably performed by ion implantation using the second sidewall as a mask.
이하, 본 발명에 따른 비휘발성 메모리 장치 제조 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a nonvolatile memory device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2e는 본 발명에 따른 비휘발성 메모리 장치 제조 방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with the present invention.
먼저, 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11)의 소정영역을 선택적으로 식각하여 트렌치(100)를 형성한 후, 트렌치(100)의 내부에 고농도 p형 불순물로 도핑된 p+다결정질의 SiGe 영역(12)을 형성하여 매립한다.First, as shown in FIG. 2A, the trench 100 is formed by selectively etching a predetermined region of the silicon wafer 11, and then p + polycrystalline doped with a high concentration of p-type impurities in the trench 100. SiGe regions 12 are formed and embedded.
이 때 트렌치(100)는 소스/드레인 영역으로 작용할 수 있는 정도의 크기로 형성하도록 한다.At this time, the trench 100 is formed to a size that can act as a source / drain region.
SiGe 영역(12)을 형성할 때에는 Si 소스물질과 Ge 소스물질을 동시에 공급하여 다결정질의 SiGe을 증착하되, Si와 Ge의 비율은 9:1 내지 7:3 정도가 되도록 하며, 바람직하게는 Si와 Ge이 8:2의 비율이 되도록 할 수 있다.When forming the SiGe region 12, the Si source material and the Ge source material are simultaneously supplied to deposit polycrystalline SiGe, but the ratio of Si and Ge is about 9: 1 to 7: 3, preferably Si and Ge can be set to the ratio of 8: 2.
또한, 구동전압 조절을 위한 불순물 도핑은 SiGe 증착과 동시에 이루어지도록 하며, SiGe 증착 후에는 열처리를 수행하여 불순물, Si 및 Ge을 확산시키고 막질을 안정화시킨다.In addition, impurity doping for driving voltage control is performed simultaneously with SiGe deposition, and after SiGe deposition, heat treatment is performed to diffuse impurities, Si and Ge, and to stabilize the film quality.
다음, 도 2b에 도시한 바와 같이, SiGe 영역(12)을 포함하여실리콘웨이퍼(11)의 상부 전면에 게이트산화막(21)을 형성하고, 그 위에 제1폴리실리콘층(22) 및 제1절연막(23)을 순차적으로 형성한 후, 제1절연막(23), 제1폴리실리콘층(22) 및 게이트산화막(21)을 선택적으로 식각하여 SONOS 구조의 소자 형성을 위한 소자구(200)를 형성하고 소자구(200)를 통해 SiGe 영역(12)을 노출시킨다.Next, as shown in FIG. 2B, the gate oxide film 21 is formed on the entire upper surface of the silicon wafer 11 including the SiGe region 12, and the first polysilicon layer 22 and the first insulating film are formed thereon. After sequentially forming 23, the first insulating layer 23, the first polysilicon layer 22, and the gate oxide layer 21 are selectively etched to form the device sphere 200 for forming a device having a SONOS structure. The SiGe region 12 is exposed through the device sphere 200.
이 때 선택적 식각으로 인해 형성되는 소자구(200)의 폭은 SiGe 영역(12)을 포함하여 이보다 약간 더 크도록, 즉 SiGe 영역(12)의 양 측방으로 엘디디(LDD : lightly doped drain) 영역이 형성될 수 있는 정도의 폭만큼 더 크게 선택적 식각하도록 한다.In this case, the width of the device sphere 200 formed by the selective etching is slightly larger than that including the SiGe region 12, that is, the lightly doped drain (LDD) region on both sides of the SiGe region 12. This allows selective etching to be as large as the width that can be formed.
이어서, 소자구(200)를 통해 노출된 실리콘웨이퍼(11) 및 SiGe 영역(12) 내로 p형 불순물이온을 저농도로 주입하여 제1LDD 영역(24)을 형성한다.Subsequently, p-type impurity ions are implanted at low concentration into the silicon wafer 11 and the SiGe region 12 exposed through the device sphere 200 to form the first LDD region 24.
다음, 도 2c에 도시된 바와 같이, 소자구(200)를 통해 노출된 실리콘웨이퍼(11) 상에 산화막으로 이루어진 제1사이드월(25)을 형성한 후, 제1사이드월(25) 및 SiGe 영역(12)을 포함하여 제1절연막(23)의 상부 전면에 산화막/질화막/산화막 구조의 ONO층(13)을 형성하고, 그 위에 제2폴리실리콘층(14)을 형성한다.Next, as shown in FIG. 2C, after forming the first sidewall 25 made of an oxide film on the silicon wafer 11 exposed through the device sphere 200, the first sidewall 25 and the SiGe are formed. An ONO layer 13 having an oxide film / nitride film / oxide film structure is formed on the entire upper surface of the first insulating film 23 including the region 12, and a second polysilicon layer 14 is formed thereon.
다음, 도 2d에 도시된 바와 같이, 제2폴리실리콘층(14) 및 ONO층(13)을 선택적으로 식각하여 적어도 소자구(200)의 상부에 남도록 함으로써, SiGe 영역(12)과 ONO층(13) 및 제2폴리실리콘층(14)으로 이루어진 SONOS 구조의 소자를 완성한다. 이 때 제2폴리실리콘층(14) 및 ONO층(13)은 소자구(200)보다 조금 더 큰 폭으로 남기는 것이 좋다.Next, as shown in FIG. 2D, the second polysilicon layer 14 and the ONO layer 13 are selectively etched so as to remain at least on the device sphere 200, thereby allowing the SiGe region 12 and the ONO layer ( 13) and a device of the SONOS structure consisting of the second polysilicon layer 14 is completed. At this time, it is preferable that the second polysilicon layer 14 and the ONO layer 13 have a width larger than that of the device sphere 200.
이어서, 제1절연막(23) 및 제1폴리실리콘층(22)을 선택적으로 식각하여 상기 SONOS 구조의 양 측방에 각 소자에서 원하는 폭으로 남긴다.Subsequently, the first insulating film 23 and the first polysilicon layer 22 are selectively etched to leave desired widths in each device on both sides of the SONOS structure.
다음, 도 2e에 도시된 바와 같이, 제1절연막(23) 및 제2폴리실리콘층(14)을 마스크로 하여 노출된 게이트산화막(21) 하부의 실리콘웨이퍼(11) 내로 n형 불순물이온을 저농도로 주입하여 제2LDD 영역(26)을 형성한다.Next, as shown in FIG. 2E, the n-type impurity ions are low concentration into the silicon wafer 11 under the gate oxide film 21 exposed by using the first insulating film 23 and the second polysilicon layer 14 as a mask. To form a second LDD region 26.
어어서, 제2폴리실리콘층(14)과 ONO층(13)의 양 측방, 그리고 제1절연막(23)과 제1폴리실리콘층(22)의 노출된 양 측방에 산화막으로 이루어진 제2사이드월(27)을 형성하고, 제2사이드월(27) 및 제2폴리실리콘층(14)을 마스크로 하여 노출된 게이트산화막(21) 하부의 실리콘웨이퍼(11) 내로 n형 불순물이온을 고농도로 주입하여 n+불순물 영역인 소스/드레인영역(28)을 형성한다.For example, a second sidewall made of an oxide film on both sides of the second polysilicon layer 14 and the ONO layer 13 and on both exposed sides of the first insulating film 23 and the first polysilicon layer 22. (27) and implanting a high concentration of n-type impurity ions into the silicon wafer 11 under the gate oxide film 21 exposed using the second sidewall 27 and the second polysilicon layer 14 as a mask. As a result, a source / drain region 28 that is n + impurity region is formed.
이로써, 3중 게이트(tri-gate) 형태의 SONOS 구조가 완성되며, 이후 후속공정을 통해 이러한 SONOS 구조의 상부에 컨택을 형성하여 상부 금속배선과 전기적으로 연결할 것이다.As a result, a tri-gate type SONOS structure is completed, and a subsequent process will form a contact on the top of the SONOS structure to electrically connect with the upper metallization.
상술한 바와 같이, 본 발명에서는 SONOS 구조에서 최하층의 제1반도체영역을 형성할 때, 종래 반도체 기판 내에 인 이온을 주입하여 제1반도체영역을 형성하는 것 대신에, 반도체 기판 내에 트렌치를 형성하고 그 트렌치를 p+다결정질 Si-Ge으로 매립하기 때문에, 종래 이온주입 시 반도체 기판이 손상되는 문제가 방지되는 효과가 있다.As described above, in the present invention, when forming the lowermost first semiconductor region in the SONOS structure, instead of implanting phosphorus ions into the conventional semiconductor substrate to form the first semiconductor region, a trench is formed in the semiconductor substrate and the Since the trench is filled with p + polycrystalline Si-Ge, there is an effect of preventing the problem of damaging the semiconductor substrate during conventional ion implantation.
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