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KR950011030B1 - Making method eeprom - Google Patents

Making method eeprom Download PDF

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Publication number
KR950011030B1
KR950011030B1 KR1019920014983A KR920014983A KR950011030B1 KR 950011030 B1 KR950011030 B1 KR 950011030B1 KR 1019920014983 A KR1019920014983 A KR 1019920014983A KR 920014983 A KR920014983 A KR 920014983A KR 950011030 B1 KR950011030 B1 KR 950011030B1
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South Korea
Prior art keywords
forming
gate
region
oxide film
oxidation layer
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KR1019920014983A
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Korean (ko)
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KR940004859A (en
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이주현
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엘지반도체주식회사
문정환
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Publication of KR940004859A publication Critical patent/KR940004859A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)

Abstract

The method consists of a step of forming a gate oxidation layer on a substrate, a step of forming the gate of selected transistor region, a step of forming an oxidation layer on the substrate, forming a photoresist layer on the oxidation layer, and forming N+ region on the surface of the substrate sequentially, a step of forming a side wall in the gate by removing the gate oxidation layer, a step of forming N- region to surround the N+ region, a step of forming a floating gate oxidation layer with a tunnel oxidation layer in the area overlapping with the N+ region, and a step of forming a floating gate on the floating gate oxidation layer, an interlevel oxidation layer on the floating gate, and a control gate on the interlevel oxidation layer.

Description

반도체 장치의 이이피롬 제조방법Ipyrom manufacturing method of semiconductor device

제1도는 종래 이이피롬의 제조를 설명하기 위한 공정단면도.1 is a cross-sectional view for explaining the production of conventional ypyrom.

제2도는 본 발명 이이피롬의 제조를 설명하기 위한 공정단면도.2 is a cross-sectional view for explaining the production of the present invention ypyrom.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : P형 기판 2 : 필드산화막1: P-type substrate 2: Field oxide film

3 : 게이트산화막 4 : 선택트랜지스트의 다결정규소3: gate oxide film 4: polycrystalline silicon of select transistor

9 : 산화막 5 : 감광막9: oxide film 5: photosensitive film

6 : 첫번째 다결정규소 7 : 두번째 다결정규소6: first polycrystalline silicon 7: second polycrystalline silicon

8 : 터널산화막 10 : N+영역8: tunnel oxide film 10: N + region

11 : N-영역 12 : 다결정규소층간 산화막11: N - region 12: polysilicon interlayer oxide film

본 발명은 반도체 장치의 이이피롬(Electrically Erasable Programmable Read Only Memory)에 관한 것으로, 특히 DDD(Double Doped Drain)를 형성하여 고집적화에 적당하도록 한 반도체 장치의 이이피롬 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an electronically erasable programmable read only memory (IIP) of a semiconductor device, and more particularly to a method for fabricating a semiconductor device of a semiconductor device in which a double doped drain (DDD) is formed to be suitable for high integration.

종래의 이이피롬은 제1(a)도와 같이 P형기판(1) 상부 양측에 필드산화막(2)을 성장하여 활성영역과 격리 영역을 정의(Define)하고, 전면에 감광막(5)을 증착하고 불순물 형성영역을 정의하여 불순물 이온주입으로 기판(1)에 N-영역(11)을 형성한 다음, 제1(b)도와 같이 게이트산화막(3) 및 터널산화막(8)을 형성한 후 첫번째 다결정규소로 플로팅게이트(Floating Gate)(6)를 형성하고, 제1(c)도와 같이 다결정규소층간 산화막(12) 및 두번째 다결정규소층을 이용해서 콘트롤게이트(Contral Gate)(7)와 선택 트랜지스터(Select Transistor)의 게이트(7a)를 형성한 후 N+영역을 형성하는 과정을 거쳐서 얻어진 제1(d)도와 같은 구조의 소자(DEVICE)이다.In the conventional Y pyrom, the field oxide film 2 is grown on both sides of the P-type substrate 1, as shown in FIG. 1A, to define the active region and the isolation region, and to deposit the photoresist film 5 on the entire surface. Define an impurity formation region to form an N region 11 on the substrate 1 by impurity ion implantation, and then form the gate oxide film 3 and the tunnel oxide film 8 as shown in FIG. A floating gate 6 is formed of silicon, and a control gate 7 and a selection transistor are formed using the polysilicon interlayer oxide film 12 and the second polysilicon layer as shown in FIG. 1 (c). The device DEVICE having the structure as shown in FIG. 1D obtained through the process of forming the N + region after forming the gate 7a of the select transistor.

그러나, 이와같은 종래의 기술에 있어서는 플로톡스 타입(FLOTOX Type)의 이이피롬은 저장 트랜지스터와 선택 트랜지스터로 구성되어 있는데, 프로그램[쓰기(Write)지우기(Erase)]시 선택 트랜지스터의 소오스와 드레인에 약 20V 정도의 고압이 걸리므로 셀(Cell) 크기를 작게하려면, 절연파괴(Breakdown)를 방지할 수 있는 DDD 구조가 필요하게 됨에도 불구하고 측벽(Side Wall)을 이용한 Ldd(Lightly Doped Drain)나 DDD와 같은 자기정렬(Self-aligned) 소오스/드레인을 형성할 수 없기 때문에 셀 크기를 작게할 수 없으므로서 고집적화가 어렵다.However, in such a conventional technique, the FLOTOX type Y pyrom is composed of a storage transistor and a selection transistor, which is roughly applied to the source and drain of the selection transistor during the program (write erasure). Since a high voltage of about 20V is applied, a smaller cell size requires a DDD structure that can prevent breakdown, Since the same self-aligned source / drain cannot be formed, the cell size cannot be reduced and high integration is difficult.

본 발명은 이와 같은 종래의 결점을 감안하여 안출한 것으로 이이피롬에 자기정렬 DDD구조로 실현시켜 고집적화 할 수 있는 반도체 장치의 이이피롬 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a method for manufacturing an ipyrom in a semiconductor device which can be realized by a self-aligned DDD structure and can be highly integrated.

이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

제2도는 본 발명의 공정 단면도로, 제2(a)도와 같이 P형기판(1) 상부 양측에 필드산화막(2)을 성장하여 활성영역과 격리영역을 정의하고, 전표면에 게이트산화막(3)을 성장한 후 선택 트랜지스터 영역의 표면에 다결정규소(4)을 패터닝하여 선택 트랜지스터의 게이트를 형성한다.FIG. 2 is a cross-sectional view of the process of the present invention, as shown in FIG. 2 (a), the field oxide film 2 is grown on both sides of the P-type substrate 1 to define an active region and an isolation region, and the gate oxide film 3 is formed on the entire surface. ) And then patterning the polysilicon 4 on the surface of the selection transistor region to form a gate of the selection transistor.

다음, 전표면에 산화막(9)을 증착하고, 그 위에 저장 트랜지스터의 소오스/드레인 형성을 위한 감광막(5)을 패터닝한 후 표면에 이온(Phosphorus)을 높은 에너지로 고농도 주입하여 P형 기판(1)에 상부에 N+영역(10)을 형성하고, 제2(b)도와 같이 감광막(5) 및 다결정 규소(4)를 마이크로하여 산화막(9) 및 게이트산화막(3)의 불필요한 부분을 이방성식각에 의해 선택적으로 제거하므로써 다결정규소(4)에 측벽산화막을 형성한다.Next, an oxide film 9 is deposited on the entire surface, and the photoresist film 5 for source / drain formation of the storage transistor is patterned thereon, and a high concentration of ions (Phosphorus) is implanted into the surface to form a P-type substrate (1). An N + region 10 is formed on the top surface), and an unnecessary portion of the oxide film 9 and the gate oxide film 3 is anisotropically etched with the photosensitive film 5 and the polycrystalline silicon 4 as shown in FIG. 2 (b). By selectively removing by means, a sidewall oxide film is formed on the polysilicon 4.

이어서 표면에 이온(Phosphorus)을 높은 에너지로 저농도 주입하여 N-영역(11)을 형성하므로써 선택 트랜지스터에 자기정렬 DDD를 형성한다.Subsequently, a low concentration of ions (Phosphorus) is implanted into the surface to form the N region 11 to form a self-aligned DDD in the selection transistor.

여기서, 고농도 이온주입시 보다 저농도 이온주입의 에너지를 더 크게하여 N-영역(10)을 N-영역(11)이 감싸도록 형성한다.Here, the N region 10 is formed to surround the N region 11 by enlarging the energy of the low concentration ion implantation more than the high concentration ion implantation.

제2(c)도와 같이 상기 감광막(5) 및 감광막(5) 하측의 산화막(9)을 제거한 후 노출된 간판 및 다결정규소층에 열산화막(3a)을 성장하되 중앙에 있는 N+영역(10)의 열산화막(3a)에 터널산화막(8)을 형성하고, 플로팅게이트(6)을 형성한다.As shown in FIG. 2 (c), the thermal oxide film 3a is grown on the exposed signboard and the polysilicon layer after removing the photosensitive film 5 and the oxide film 9 under the photosensitive film 5, but in the center of the N + region 10 The tunnel oxide film 8 is formed in the thermal oxide film 3a of the (), and the floating gate 6 is formed.

여기서, 터널산화막(8) 형성방법은 그 부위의 산화막(3a)을 소정깊이로 식각한 것이며, 플로팅게이트(6)를 전면에 다결정규소막을 증착하고 선택적으로 식각하여 형성한다.Here, the tunnel oxide film 8 is formed by etching the oxide film 3a at a predetermined depth, and the floating gate 6 is formed by depositing and selectively etching the polysilicon film on the entire surface.

이때 선택 트랜지스트의 다결정규소 위에 성장된 산화막이 식각정지(Etch Stop) 역할을 한다.At this time, the oxide film grown on the polycrystalline silicon of the select transistor serves as an etch stop.

그리고, 첫번째와 두번째, 다결정규소 층간의 산화막(12)을 성장시킨 다음 플로팅게이트(6) 상층의 산화막(12) 위에 콘트롤게이트를 형성한다.Then, the oxide film 12 between the first and second polysilicon layers is grown, and then a control gate is formed on the oxide film 12 above the floating gate 6.

이때에도 선택 트랜지스트의 다결정규소 위에 더욱 두껍게 성장된 산화막이 식각정지 역할을 하므로써 제2(d)도와 같은 구조를 갖는 이이피롬이 제조된다.In this case, the ypyrom having a structure as shown in FIG.

이상에서 설명한 바와같이 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, 자기정렬 DDD가 비디칭으로 형성되므로써 고압이 걸리는 선택 트랜지스터 근처에 N-영역(11)의 넓게 분포되므로 고압을 사용해도 절연파괴가 일어나지 않는다.First, since the self-aligned DDD is formed by non-diching, a wide distribution of the N region 11 near the selection transistor to which a high voltage is applied does not cause dielectric breakdown even when a high voltage is used.

둘째, 고농도의 N+영역(10)을 형성하므로써 터널 산화막의 에너지장벽(Barrier Height)을 낮추어주기 때문에 프로그램의 속도를 높이고, 프로그램 전압을 낮출 수 있으므로 고속저전압 동작 뿐만 아니라 소자의 소형화를 가장 큰 장해요소중의 하나인 대단히 얇은 터널산화막의 두께를 비교적 두껍게 할 수 있다.Second, by forming a high concentration of N + region 10, the barrier height of the tunnel oxide film can be lowered, so that the program speed can be increased and the program voltage can be lowered. One of the elements, a very thin tunnel oxide film can be made relatively thick.

Claims (1)

기판의 활성영역과 결리영역을 정의하고, 상기 기판위에 게이트산화막을 형성하는 단계와, 상기 활성영역의 선택 트랜지스터영역의 게이트를 형성하는 단계와, 상기 게이트를 포함한 기판위에 산화막을 형성하고 저장트랜지스터의 소오스 및 드레인 영역을 형성하기 위해 상기 산화막위에 감광막을 형성하고 이온을 주입하여 상기 기판표면에 N+영역을 형성하는 단계와, 상기 감광막 및 상기 게이트를 마스크로하여 상기 산화가 및 상기 게이트산화막을 제거함으로써 게이트측면에 측벽을 형성하는 단계와, 이온을 주입하여 N+영역을 둘러싸도록 N-영역을 형성하는 단계와, 상기 감광막과 상기 측벽을 제거하고 상기 게이트전극을 포함한 상기 기판위에 N+영역과 중첩된 영역에 터널산화막을 가진 플로팅게이트 산화막을 형성하는 단계와, 상기 플로팅게이트 산화막 위에 플로팅게이트와 상기 플로팅게이트 위에 층간산화막, 상기 층간산화막위에 콘트롤게이트를 형성하는 단계를 포함하여 이루어지는 반도체 장치의 이이피롬 제조방법.Defining an active region and a isolation region of the substrate, forming a gate oxide layer on the substrate, forming a gate of the selection transistor region of the active region, forming an oxide layer on the substrate including the gate, and forming a gate transistor. Forming a photoresist film on the oxide film and implanting ions to form an N + region on the surface of the substrate to form a source and a drain region, and removing the oxidation value and the gate oxide film by using the photoresist film and the gate as a mask. by forming a side wall on the gate side, and implanting ions in a manner to surround the N + region N - forming a region, removing the photosensitive film and the side wall, and an N + region on the substrate including the gate electrode and Forming a floating gate oxide film having a tunnel oxide film in an overlapped region; Forming a floating gate on the floating gate oxide layer, an interlayer oxide film on the floating gate, and a control gate on the interlayer oxide film.
KR1019920014983A 1992-08-20 1992-08-20 Making method eeprom KR950011030B1 (en)

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KR950011030B1 true KR950011030B1 (en) 1995-09-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501682B2 (en) 2006-04-24 2009-03-10 Samsung Sdi Co., Ltd. Nonvolatile memory device, method of fabricating the same, and organic lighting emitting diode display device including the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100341348B1 (en) * 1999-07-16 2002-06-21 박찬구 Polycarbonate thermoplastic resin composition

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7501682B2 (en) 2006-04-24 2009-03-10 Samsung Sdi Co., Ltd. Nonvolatile memory device, method of fabricating the same, and organic lighting emitting diode display device including the same

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