KR20040022737A - Preprocessor circuit of moving picture encoder and it's method - Google Patents

Abstract

PURPOSE: A preprocessing circuit and a preprocessing method for a motion picture encoder are provided to obtain images with improved resolution by allowing for a wide variety of horizontal/vertical scaling ratios. CONSTITUTION: A preprocessing circuit comprises a synchronous signal sensor unit(102) for sensing horizontal and vertical synchronous signals of the digital image signal input from an external source; a capture window size determining unit(104) for outputting horizontal and vertical valid signals from the input image; a capture image scaling ratio determining unit(106) for outputting horizontal and vertical output synchronous signals and pixel output request signal by using horizontal and vertical valid signals output from the capture window size determining unit; a horizontal filter unit(108) for outputting a horizontally filtered value so as to reduce the degradation of image quality caused due to the scale down; and a vertical filter unit(110) for outputting a vertically filtered value obtained from the vertical filtering of the horizontally filtered value so as to reduce the degradation of image quality caused due to the scale down.

Description

Preprocessor circuit of moving picture encoder and it's method

The present invention relates to a pre-processing circuit and method for a video encoder, and more particularly, filtering to prevent a deterioration in image quality due to conversion while converting an input video to a desired video size before encoding a video signal to transmit a predetermined data rate. It relates to a pretreatment circuit and method.

In general, when a video signal such as a video telephone or an HDTV is to be transmitted as a digital signal, a high rate data compression method is used to reduce a large amount of data.

Video communication compresses and transmits video data, and high-resolution video of a video source to be compressed must first be converted into low-resolution video such as QCIF or CIF, which is mainly used in video communication.

However, if the simple partial removal (decimation) of each pixel according to the scaling ratio in order to convert to a low resolution, the image quality deteriorates, so it is necessary to filter using the correlation of neighboring pixels.

Before the video encoding process, the process of filtering to change the desired image size in this way and to prevent the deterioration of image quality due to the conversion is called preprocessing.

US Patent (Patent No. 5,874,937, Method and appratus for scaling up and down a video image) has been disclosed as a prior art regarding a method and apparatus for up and down scaling during the pretreatment process as shown in FIGS. 1 and 2.

The liquid crystal projector shown in FIG. 1 projects the video image generated by the PC 1 onto the screen.

The liquid crystal projector includes a CPU 9, a main memory 8, an input panel 7 functioning as an input means, an A / D converter 2, a frame memory 3, a video scaler 4, an LCD driver. (5), the LCD panel 6, and a light source.

The frame memory 3 comprises three memory plates for storing R, G and B signals.

In addition, the LCD driver 5 and the LCD panel 6 provide R, G, and B signals.

The CPU 9 includes a frequency determination unit 9a for determining the frequency of the synchronization signal SYNC given by the PC 1, and a resolution determination unit 9b for determining the resolution in accordance with the synchronization signal SYNC. Function

The CPU 9 executes computer program code stored in the main memory 8 to implement the above functions.

The A / D converter 2 converts the analog video signal VPC generated by the PC 1 into a digital video signal DPC and converts the digital video signal DPC into a video scaler 4. To pass.

The video scaler 4 receives not only the digital video signal DPC but also the synchronization signal SYNC output from the PC 1.

The video scaler 4 reads the video signal from the frame memory 3 and writes the input digital video signal DPC to the frame memory 3 while providing the video signal to the LCD driver 5.

During the recording and reading procedure, the video scaler 4 enlarges or reduces the video image to match the standard resolution of the LCD panel 6.

The LCD driver 5 reproduces the video image transmitted from the video scaler 4 to the LCD panel 6.

The video image reproduced on the LCD panel 6 is eventually projected as a color image onto the screen by means of an optical system included in the light source.

FIG. 2 is a diagram structurally showing the function of the video scaler shown in FIG.

As shown on the left side of FIG. 2, video images are generated by the PC 1 at various resolutions (eg, 640x400, 640x480, 800x600, 1024,768, 1600,1200).

On the other hand, the standard resolution of the LCD panel 6 is fixed to a predetermined value and in the example of FIG. 2, the standard resolution is 800x600.

The video scaler 4 enlarges or reduces the input video signal VPC to generate a video signal possessed by the standard resolution of the LCD panel 6.

When the video signal generated by the PC 1 is the input of the liquid crystal projector, the video image represented by the video signal VPC will be generated on the entire screen of the LCD panel.

In FIG. 2, in order to display an image on a display device (LCD panel) having a resolution of 800x600, since the image supports only limited scaling ratio, the size of the input image should be selected from 640x400, 640x480, 800x600, 1024x768, and 1600x1200.

That is, there is a problem in that only a limited size image is used as the input video by scaling up / down only a specific size of input video image to obtain an output video image having a desired resolution.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to use a horizontal / vertical scaling ratio of a video scaler to obtain an image having a desired resolution even for an input video image of any size. The present invention provides a preprocessing circuit and a method of a video encoder.

Another object of the present invention is to provide a pre-processing circuit and a method of a video encoder which facilitates a video input interface in an image system implementation by interfacing a low-cost digital CMOS camera or the like that outputs in various sizes. have.

In order to achieve the above object, the present invention, by the SYNC detection unit for detecting the horizontal synchronization signal (HSYNC) and the vertical synchronization signal (VSYNC) of the digital image signal input from the outside, by the synchronization signal (HSYNC / VSYNC) Horizontal output / vertical which is a scaled down section using a capture window sizing unit that outputs a valid signal (HVALID / VVALID) horizontally and vertically from an input image and the HVALID / VVALID signal outputted from the capture window sizing unit. Capture image scaling ratio deciding unit which outputs output synchronizing signal (ccd_hs / ccd_vs) and pixel output request signal (ccdi_req), and horizontal filter unit which outputs YOUT by filtering horizontally to reduce image quality deterioration due to the scaling down. And a vertical filter unit which vertically filters the horizontally filtered YOUT to reduce the deterioration of the image quality due to the scaling down and outputs the VFILO. And to provide a pre-processing circuit of the encoder.

In order to achieve the above object, the present invention, pre-processing of the video encoder to capture the image output from the external device to scale up or down and filtering in the horizontal / vertical direction in order to reduce the deterioration of the image quality caused by the scaling down In the way:

In capturing the image, a WID representing a horizontal size of the captured image, an HEI representing a vertical size of the captured image, an HSP representing a horizontal starting point of the captured image, a VSP representing a vertical starting point of the captured image, and an HSR are displayed. Provides a method of pre-processing a video encoder characterized by capturing an image with the parameter value using six parameters of an HSR indicating a horizontal scaling ratio and a VSR indicating a vertical scaling ratio of a captured image. I would like to.

1 is a block diagram showing a conventional liquid crystal projector.

FIG. 2 is a diagram illustrating a function of the video scaler shown in FIG. 1.

3 is a block diagram of a preprocessing circuit according to the present invention.

4 is a diagram illustrating parameters required for capturing an image.

5 is a diagram illustrating a process of capturing an image of an arbitrary size.

6 is a diagram illustrating an example of capturing a CIF image.

FIG. 7 is a detailed block diagram of the SYNC sensing unit and the capture window sizing unit shown in FIG. 3.

FIG. 8 is a detailed block diagram of the captured image scaling ratio determiner shown in FIG. 3.

FIG. 9 is a detailed block diagram of the horizontal filter unit shown in FIG. 3.

FIG. 10 is a detailed block diagram of the vertical filter unit shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

1: PC2: A / D Converter

3: frame memory 4: video scaler

5: LCD Driver 6: LCD Panel

7: input panel 8: main memory

9: CPU9a: Frequency Determination Unit

9b: resolution determination unit 100: preprocessor

102: SYNC detection unit 104: capture window size determination unit

106: capture image scaling non-determining unit

108: horizontal filter unit 109: MUX

110: vertical filter unit 112: CPU

114: DMA116: Video memory

118: memory controller

Hereinafter, the configuration and operation of the present invention will be described with reference to the accompanying drawings.

3 illustrates a process of capturing an image output from an external device (interface of a predecoder 100 and an external device (video decoder or digital camera) that is in charge of image input and output from the external device) and storing it in the video memory 116.

One of the main functions of the preprocessor 100 is to convert a high resolution image into a low resolution image required by an encoder.

The size and shape of the screen to be converted are determined through register settings, and filtering is performed in the horizontal and vertical directions by using correlations between pixels in order to minimize the deterioration of the quality caused by the conversion to low resolution.

112 denotes a CPU, 114 a DMA, and 118 a memory controller.

4 shows parameters required for image capture.

Where WID (Capture Image Width) represents the horizontal size of the captured image, HEI (Capture Image Height) represents the vertical size of the captured image, HSP (Horizontal Capture Start Position) represents the horizontal start point of the captured image, and VSP (Vertical Capture Start Position (Capture) indicates the vertical start point of the captured image, HSR (Horizontal Capture Scaling Ratio) indicates the horizontal ratio of the captured image, and VSR (Verticla Capture Scaling Ratio) indicates the vertical ratio of the captured image.

5 shows a process of capturing an image of arbitrary size in an MxN size image.

The image input from the digital camera or ADC (video decoder) can be of any size and the VSP, HSP, WID, HEI, VSR and HSR register values are determined programmatically to capture the image as shown in FIG.

The six parameters can be changed externally.

VSR and HSR determine the scaling ratio horizontally and vertically when capturing images. , Used as.

The n value can be changed externally.

The reason why the scaling ratio is divided horizontally and vertically, respectively, is to support images input at various sizes during capture.

6 shows an example of capturing a 352x288 CIF image in a 512x496 digital CMOS camera.

7 is a detailed block diagram of the SYNC detector 102 and the capture window sizing unit 104 shown in FIG.

A vertical sync signal VSYNC output from an external video decoder or ADC, a SYNC detector 102 for detecting a horizontal sync signal HSYNC, and a capture window sizing unit for outputting a valid horizontal / vertical section from an input image ( 104).

The vertical sync signal VSYNC represents a vertical regression section and is used as a signal to indicate the vertical start of the screen inside.

The horizontal synchronization signal (HSYNC) represents a horizontal regression section and is used as a signal to indicate the horizontal start of the screen inside.

The image input from the digital camera or the ADC (Video Decoder) can be any size, and the HSP, WID, VSP, and HEI values are adjusted to output a valid screen area vertically and horizontally.

The portion that calculates and outputs a horizontally valid section is composed of a horizontal counter 104ba and a comparator 104bb.

The horizontal counter 104ba is initialized by the horizontal synchronizing signal HSYNC and makes the horizontal valid signal HVALID equal to 1 when compared with the HSP in the comparator 104bb.

When the horizontal counter value becomes HSP + WID in the comparator 104bb, the horizontal valid signal HVALID is set to 0 to output a HVALID indicating a valid interval horizontally.

The portion that calculates and outputs a vertically valid section by the above method is composed of a vertical counter 104aa and a comparator 104ab.

The vertical counter 104aa is initialized by the vertical synchronizing signal VSYNC and sets the vertical valid signal VVALID to 1 if it is equal to the VSP in the comparator 104ab.

When the vertical counter value becomes VSP + HEI in the comparator 104ab, the vertical valid signal VVALID is set to 0 and a VVALID indicating a valid interval is output vertically.

FIG. 8 is a detailed block diagram of the captured image scaling ratio determiner 106 shown in FIG. 3, wherein the captured image scaling ratio determiner 106 is a vertical valid signal VVALID generated by the capture window sizing unit 104. ) And the horizontal valid signal (HVALID).

The line counter 106ba operates during the period in which the vertical valid signal VVALID = 1, and compares the VSR value with the comparator 106bb and outputs a valid vertical section lin_v.

For example, in the case of VSR = 1/2, when the value of the line counter 106ba (lin_cnt) increases and becomes a multiple of 2, the effective vertical section (lin_v) is made to 1 to perform 1/2 scaling down operation. Do it.

Likewise, the pixel counter 106ca operates during the period in which the horizontal valid signal HVALID = 1, and the effective horizontal pixel pix_v is output by comparing the HSR value with the comparator 106cb.

The capture ratio capt_rate is a function of adjusting the frame rate captured by the preprocessor 100 to a valid screen fld_v using the value fld_cnt of the field counter 106aa which is increased by the vertical sync signal VSYNC. Indicates.

Combined fld_v representing valid screen, lin_v representing effective vertical section, and pix_v representing effective horizontal pixel with combiner 106c, and finally the scaled down interval calculated by HSP, VSP, WID, HEI, HSR, VSR values Output

That is, the preprocessor 100 outputs the vertical output synchronizing signal ccd_vs, the horizontal output synchronizing signal ccd_hs, and the pixel output request signal ccdi_req.

9 illustrates a horizontal filter unit for reducing deterioration of image quality due to scaling down.

9, the shift register SR1-SR7, the shift and adder operation units SA1-SA7, and the adder 108a are horizontally scaled down and output to the shift registers SR1-SR7. The values Y_1D-Y_7D are shifted and input in order, shifted and added with the filter coefficient values COEF1-4 in the shift and adder operating units SA1-SA7, and the resultant values PROD1-7 are output.

In this case, the filter coefficient value COEF1-4 may be determined and input by the external CPU 112, and the weight may be determined in consideration of the correlation between the pixels.

Each result value is added by the adder 108a and output as a horizontally filtered output value HFILO, and whether or not horizontal filtering is determined by the MUX 109 is horizontally scaled down and outputs a value YOUT. Will print.

9 shows that using a 8-bit floating point value as the filter coefficient value COEF1-4 does not require the use of a multiplier.

10 illustrates a vertical filter unit 110 for reducing deterioration of image quality due to scaling down.

When the value YOUT that is horizontally scaled down and output is stored in the line buffer SRAM1 in order, and the YOUT of the next line is output, the value of the line buffer SRAM1 is stored in the line buffer SRAM2 and the new YOUT is lined. It is stored in the buffer SRAM1.

If YOUT of the next line is output, YOUT is intact, output value CDOUT1 of line buffer SRAM1 is shifted right, output value CDOUT2 of line buffer SRAM2 is equal to 1: 2: The adder 110a is input to the adder 110a at a ratio of 1 and outputs an added and vertically filtered output value VFILO.

As described above, according to the present invention, an image having a desired resolution can be obtained even for an input video image having any size by using various horizontal / vertical scaling ratios.

In particular, it is possible to interface with a low-cost digital CMOS camera that outputs in various sizes to obtain an image having a desired resolution, thereby facilitating an image input interface in an image system.

Claims (6)

SYNC detection unit for detecting the horizontal synchronization signal (HSYNC) and vertical synchronization signal (VSYNC) of the digital image signal input from the outside; A capture window sizing unit for outputting a valid signal (HVALID / VVALID) horizontally and vertically from an input image by the synchronization signal (HSYNC / VSYNC); Determining a capture image scaling ratio that outputs a horizontal output / vertical output synchronization signal (ccd_hs / ccd_vs) and a pixel output request signal (ccdi_req) which are scaled down using the HVALID / VVALID signal output from the capture window sizing unit. Wealth, A horizontal filter unit which horizontally filters and outputs a YOUT to reduce deterioration of image quality due to the scaling down; And a vertical filter unit vertically filtering the horizontally filtered YOUT to reduce the deterioration of the image quality due to the scaling down and outputting a VFILO. The method of claim 1, wherein the capture window size determination unit, If the horizontal counter initialized by the horizontal synchronization signal HSYNC and the value of the horizontal counter are equal to the horizontal start point HSP of the captured image, the horizontal valid signal HVALID is set to 1, and the value of the horizontal counter is When the HSP + WID (horizontal size of the captured image) is reached, a comparator for making the horizontal valid signal HVALID 0 and outputting a valid section horizontally, a vertical counter initialized by the vertical synchronization signal VSYNC, and the vertical counter. If the value of is equal to the vertical start point (VSP) of the captured image, the vertical valid signal (VVALID) is set to 1, and when the value of the vertical counter becomes HSP + HEI (vertical size of the captured image), the vertical valid signal (VVALID) is obtained. And another comparator for outputting the valid section vertically by making 0 equal to 0. The method of claim 1, wherein the capture image scaling ratio determiner, The line counter operating during the period of the vertical valid signal VVALID = 1 and the value of the round counter are compared with the vertical ratio VSR of the captured image to create a valid vertical section lin_v to perform scaling up or down operations. A comparator, a pixel counter that operates during the horizontal valid signal HVALID = 1, and compares the value of the pixel counter with the horizontal ratio HSR of the captured image to generate an effective horizontal pixel pix_v. Alternatively, a valid screen fld_v is compared with another comparator performing a down operation, a field counter that is increased by the vertical sync signal VSYNC, and a capture rate capt_rate that adjusts a frame rate for capturing the value of the field counter. A video coder comprising: a comparator for outputting a comparator and a combiner for outputting a scaled down section by combining the fld_v, lin_v, and pix_v A preprocessing circuit. A pre-processing method of a video encoder for capturing an image output from an external device, scaling up or down, and filtering in a horizontal / vertical direction to reduce deterioration of image quality caused by scaling down; When capturing the image, WID representing the horizontal size of the captured image, HEI representing the vertical size of the captured image, HSP representing the horizontal starting point of the captured image, VSP representing the vertical starting point of the captured image, and HSR representing the horizontal scaling ratio of the captured image. And scaling up or down by capturing an image with the parameter value using six parameters of the HSR and VSR representing the vertical scaling ratio of the captured image. The method of claim 4, wherein the scaling ratio of the HSR is Or A pre-processing method of a video encoder, characterized in that. The method of claim 4, wherein the scaling ratio of the VSR is Or A pre-processing method of a video encoder, characterized in that.