JP3096756B2 - Image conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image conversion apparatus suitable for a camera for capturing an image in a personal computer, a workstation, a videophone, a video conference, and the like. The present invention relates to an image conversion device suitable for displaying on a pixel display.

[0002]

2. Description of the Related Art Conventionally, most cameras for capturing images are
Analog signal output, such an analog signal output,
When an attempt is made to display on a square pixel display in which each dot is formed of a square, the analog signal is sampled at 13.5 MHz, and then passed through a reduction filter that reduces the number of lines and dots in the vertical and horizontal directions. Alternatively, the image data is converted into image data corresponding to the display of the square pixel by setting the sampling frequency to be a square pixel.

Further, in the case of a digital processing / digital output camera using a CCD as an image pickup device, a CCD corresponding to a square pixel must be used in order to obtain image data corresponding to the number of pixels of the CCD. Was.

[0004]

In such a conventional example, since the image data from the image sensor is once converted into an analog signal and then subjected to A / D conversion, the image quality is degraded due to analog signal processing. In addition, A / D conversion is required, which is uneconomical.

[0005] Also, digital processing / digital output CC
For cameras using D, a CCD that supports square pixels
Has to be used, and there is a disadvantage that the CCD is limited.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide an image conversion apparatus which can provide a high-quality image corresponding to a square pixel and can use an arbitrary CCD. I do.

[0007]

In order to achieve the above-mentioned object, the present invention is configured as follows.

That is, the image conversion apparatus according to the first aspect of the present invention comprises: an image pickup means for converting an image pickup light from an incident object into an electric signal; and an output signal from the image pickup means.
Preprocessing means for performing preprocessing such as noise suppression and automatic gain control; A / D conversion means for converting an output signal from the preprocessing means into a digital signal; and digital data output from the A / D conversion means. Signal processing means for separating a luminance signal and a color signal, and format conversion means for converting digital image data output from the signal processing means into image data of a format corresponding to a square pixel by digital processing , the format conversion means Is
Digital image data output from the
Image data of the first format corresponding to a pixel
Conversion means for converting the data into
When the converted image data has the number of lines and the number of dots of 1
/ 2 converted to image data of the second format
Conversion means and an image converted to the second format
The data is stored in a third file having half the number of lines and dots.
A third converting means for converting the image data into a format image data;
According to the specification signal that specifies the format to be changed,
Control means for controlling the conversion operation of each conversion means.
I have.

[0009] In the image conversion apparatus according to the present invention, the format conversion means may further include:
Equipped with contour enhancement means for enhancing the contour of image data
You.

According to a third aspect of the present invention, in the image conversion apparatus, the first conversion means is inputted in synchronization with a clock.
Digital image data in the first format.
Converted to image data including image data and synchronized with the clock
A first converter for outputting the first format, and the first format
Generates a data valid timing signal indicating the image data
A first timing signal generator, and the second converter
The stage is provided with the first format input in synchronization with a clock.
Converting the image data of the mat into an image of the second format;
Converted to image data including data and synchronized with the clock
A second converter for converting and outputting,
Generates a data valid timing signal indicating image data
A second timing signal generator, wherein the third converter
Is the second foreground input in synchronization with the clock.
The image data including the image data of the
Converted to image data containing format image data
A third converter for outputting in synchronization with the clock;
Data valid time indicating image data of format 3
And a third timing signal generator for generating a signaling signal.
Things.

According to a fourth aspect of the present invention, in the image conversion apparatus according to the present invention, the second conversion unit includes an image in a first format.
One of the odd or even fields of the data
To reduce the number of lines by half
And the third conversion unit performs the dot calculation by the arithmetic processing.
A horizontal operation unit for reducing the number to １ ／, the horizontal operation unit comprising:
Data of both adjacent dots or
Either of the data of both dots one dot away can be selected
Things.

According to a fifth aspect of the present invention, in the image conversion apparatus of the present invention, the third conversion unit reduces the number of lines to one by an arithmetic processing.
/ 2 vertical operation unit and the number of dots
A horizontal operation unit for reducing the power to 1/2, and the vertical operation unit includes:
The image data in which the number of dots has been converted to で by the horizontal operation unit
Line memo that data is written and read
Image data read from this line memory.
Data and image data from the horizontal calculation unit.
Is Umono.

According to a sixth aspect of the present invention, there is provided an image conversion apparatus comprising:
The first format has a resolution of 640 × 480 dots.
VGA (Video Graphics Array) format
It is.

According to a seventh aspect of the present invention, there is provided an image conversion apparatus comprising:
The first format has a resolution of 352 × 288 dots.
CIF (Common Intermediate Format).

According to an eighth aspect of the present invention, there is provided an image conversion apparatus comprising:
The second conversion unit is configured to perform a second conversion in accordance with the control of the control unit.
The image data of the first format is converted to the second format
Image data or convert it without conversion.
Output to the third conversion means as it is.
(3) the second conversion means, in accordance with the control of the control means,
Format image data in a third format.
Data, or image data in the first format.
Data or data in a second format
It is output without any change.

[0016]

According to the first aspect of the present invention, digital image data obtained by A / D conversion of an output signal from an image pickup means is converted into image data corresponding to a square pixel by digital processing. A digital image data obtained by A / D conversion of an output signal from the means is once converted to analog image data, and then a high-quality image without deterioration in image quality is obtained compared with a conventional example in which A / D conversion is performed again. it is possible to provide, it can be used square pixels corresponding non CCD CCD as an imaging element of the imaging means, format converting means, first to third conversion hand
Control means for controlling the stages and each conversion operation.
Thus, it is possible to support a plurality of formats.

According to the second aspect of the present invention, the former
The cut conversion means enhances the outline of the converted image data.
Contour emphasizing means, so that images with sharp outlines
Obtainable.

According to the third aspect of the present invention, each converter is
In the stage, input and output of image data in synchronization with a common clock
Is performed and image data in the converted format is
Data valid timing signal indicating that the data is valid
The image data with a common clock.
Data rate depending on the format being converted.
No need to convert.

According to the fourth aspect of the present invention, the third
The conversion unit converts the number of dots to half by arithmetic processing.
It has a flat computing section, and the horizontal computing section is used as data to be computed.
Of both adjacent dots or two dots separated by 1 dot
You can select one of the data in the
It can correspond to the conversion to the mat.

According to the fifth aspect of the present invention, the third
The horizontal direction is displayed on the line memory of the vertical
The image data for which the number of dots is halved by the arithmetic
Or read, so after converting the number of lines,
Compared to the configuration where the number of dots is converted by the
The capacity of the memory can be reduced.

According to the sixth aspect of the present invention, the first
Format is 640 x 480 dot resolution VG
A format, so VGA format
320 × 2 with half the number of dots and the number of lines
Format of 40 dots (hereinafter referred to as "QVGA")
Or the number of dots in QVGA format
And 160 x 120 dots with half the number of lines
(Hereinafter referred to as “Q ² VGA”) format
It becomes possible.

According to the seventh aspect of the present invention, the first
Format is CI of 352 × 288 dots.
F, the resolution is 176 x 144 dots.
It can be converted to QCIF.

According to the eighth aspect of the present invention, it is relatively simple.
Conversion to multiple formats is possible with a simple circuit configuration
You.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an image conversion apparatus according to one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an image pickup means for converting an optical image captured by an image pickup lens into an electric signal;
Sample and hold the output signal of
C) A / D for converting an output signal from the preprocessing unit 2 into digital data in dot units
The conversion means 4 is based on the digital data from the A / D conversion means 3 and has a luminance signal (Y) and a chrominance signal (RY, B-
Y), and performs a white balance process, a gamma correction process, and the like to perform a luminance signal (Y) and a chrominance signal (RY, B-
Y) is a video signal processing means for outputting a digital signal.
It is output as a point-sequential color difference signal of Y, BY.

Reference numeral 7 denotes a driving means for generating a driving timing pulse for controlling the image pickup means 1, a synchronizing pulse for a video signal, a pulse for processing a video signal, and the like. This is control means for controlling a format conversion means 5, a driving means 7, and the like, which will be described later.

The format conversion means 5 converts the luminance signal and the chrominance signal output from the video signal processing means 4 into image data of a predetermined image size corresponding to the square pixel and outputs the image data to the outside. .

This image converter is connected to a workstation, for example, and is used to input a captured image to the workstation, and is used for a video conference or the like.

In this embodiment, the image data of 410,000 pixels (768 × 494 pixels) constituting the CCD which is the image pickup device of the image pickup means 1 is converted by the format conversion means 5 into a VGA (640 × 480 dots) corresponding to a square pixel. Convert to format.

It should be noted that image data consists of one field (64
(0x240 dots) is sent twice, odd and even, to form one screen.

If it is assumed that the CCD of 410,000 pixels is read out at 768 × 247 dots for each of the odd and even fields, the vertical direction is 240 lines. , And the lower three lines are deleted.

The horizontal direction needs to be converted into 640 dots. In this embodiment, 640 dots are obtained by converting 12 dots into 10 dots.

By performing such vertical / horizontal conversion, it becomes possible to output VGA format image data corresponding to the square pixels.

FIG. 2 is a block diagram showing the structure of the format conversion means 5, and FIGS. 3 and 4 show signals input to the format conversion means 5, ie, output signals of the video signal processing means 4. FIGS. 3 and 4
Indicates the start of the horizontal period and the start of the vertical period with different time axes.

FIG. 3A shows a dot clock DCLK, and FIG. 3B shows a horizontal start signal LST indicating the start of a horizontal period.
N, FIG. 3C shows a luminance signal, FIG. 3D shows a chrominance signal, FIG. 4B shows a vertical start signal FSTN indicating the start of a vertical period, and FIG. 4C shows a luminance signal. And color signals.

As shown in FIG. 3, simultaneously with the end of the horizontal blanking period, the dot clock DCLK and the horizontal start signal LSTN rise, and valid luminance signals and color signals are input.

As shown in FIG. 4, the horizontal start signal LSTN and the vertical start signal FSTN rise at the same time as the end of the vertical blanking period, and valid luminance signals and color signals are input. The vertical start signal FSTN and the horizontal start signal LSTN are composed of vertical and horizontal drive signals VD,
HD.

The format conversion means 5 of this embodiment comprises:
As shown in FIG. 2, based on the vertical start signal FSTN and the horizontal start signal LSTN, 24
A vertical valid timing generator 25 that outputs a start signal START that becomes active over a period corresponding to the 0 line, and converts the number of dots in the horizontal direction from 12 to 10
And a dot conversion unit 24.

The vertical valid timing generator 25 includes a first LSTN signal counter 21 for deleting the upper four lines.
And the second LS for counting valid 240 lines
Based on the TN signal counter 22 and the outputs of these counters 21 and 22, the effective 240
Start signal STA active over the period of the line
A START signal generator 23 for outputting RT.

FIGS. 5A and 5B are timing charts for explaining the operation of the vertical valid timing generator 25. FIG. 5A shows the vertical start signal FSTN, FIG. 5B shows the horizontal start signal LSTN, and FIG. (C) is the output of the first LSTN signal counter 21, (D) is the output of the second LSTN signal counter 22, and (E) is the start signal STAR.
T is shown.

As shown in FIG. 5, the first LSTN
The signal counter 21 is cleared at the fall of the horizontal start signal LSTN when the vertical start signal FSTN is active, and counts the fall of the horizontal start signal to four. The second LSTN signal counter 22 outputs the horizontal start signal LST when the vertical start signal FSTN is active.
Cleared at the falling edge of N and the start signal START
During the active period, the falling of the horizontal start signal LSTN is counted, and when the count value reaches 240, an output for deactivating the start signal START is supplied to the START signal generation unit 23. The START signal generator 23 activates the start signal START at the rising edge of the horizontal start signal LSTN immediately after the count value of the first LSTN signal counter 21 becomes 4, and also activates the second LSTN signal counter 2.
When the count value of 2 becomes 240, the start signal START is made inactive.

That is, in the vertical valid timing generator 25, the active start signal S over a period corresponding to 240 lines excluding the upper four lines and the lower three lines.
TART will be output.

Conversion of the number of dots in the horizontal direction 12 → 1
As the 0-dot conversion unit 24, there are a method of thinning out 2 dots from 12 dots and a method of calculating by multiplying data of each 12 dots by a coefficient. In this embodiment,
It is calculated by calculation.

Here, the image data from the video signal processing means 4 is continuously transmitted for one line in synchronization with the dot clock DCLK. Therefore, 10 dots are output for every 12 dots of the image data. In this case, for the output, a signal having a period of 10/12 of the dot clock DCLK is used, or if a calculation result is output in synchronization with the dot clock DCLK, invalid data for two dots must be inserted. Must be done.

In this embodiment, the dot clock DCLK
And outputs an invalid result for two dots, and outputs a data active signal DTACTV indicating whether the output data is valid or invalid.
Is caused to occur.

FIG. 6 is a timing chart for explaining the above operation in the 12 → 10 dot conversion section 24. FIG. 6 (A) shows the dot clock DCLK, FIG. 6 (B) shows the horizontal start signal LSTN, and FIG. The figure (C) shows the dot N
o. (D) shows the output data as the operation result, and (E) shows the data active signal DTATV indicating the validity / invalidity of the output data.

Here, the No. assigned to the output data is
Is the dot No. used in the calculation. For example, 1 + 2 indicates a dot No. 1 and dot No. 2 is calculated by calculating the image data.

This operation is not a simple addition, but is actually weighted. In this embodiment,
The following calculation is performed.

0th dot after conversion = 0th dot before conversion 1st dot after conversion = (1st dot before conversion × 4 + 2nd dot before conversion × 1) ÷ 5 2nd dot after conversion = (2nd dot before conversion) × 3 + 3rd dot before conversion × 2) ÷ 5 3rd dot after conversion = (3rd dot before conversion × 2 + 4th dot before conversion × 3) ÷ 5 4th dot after conversion = (4th dot before conversion × 1 +) (5th dot before conversion × 4) ÷ 5 After the 5th dot after the conversion, it is the same as the 0th dot and after the conversion.

In this output data, invalid data for 2 dots is inserted for every 12 dots. In this embodiment, as shown in FIG. 6, the invalid data correspond to the first dot and the seventh dot before conversion. Invalid data is inserted at the specified position.

A data active signal DTATV indicating whether the output data is valid or invalid is a 12 → 10 dot conversion unit 24.
Dot no. Is formed by decoding a count value of a dot counter (not shown) for counting the number of pixels.

Note that the color signal is changed from 6 dots to 1 dot.
The dots are simply thinned out.

The above-mentioned start signal START is AND-processed with this data active signal DTATV, and is output as a data valid timing signal shown in FIG. Therefore, in the subsequent stage of the format conversion means 5, by taking in the converted video data only during the period when the data valid timing signal is active, 640 dots ×
VGA data corresponding to a 240-pixel square pixel can be received.

As described above, the image data from the CCD of the imaging means 1 is A / D converted and then digitally processed to obtain image data corresponding to the square pixels. Compared to the case where A / D conversion is performed once after conversion to
A high-quality image can be provided, and the CCD is not limited to a square pixel-compatible CCD unlike the conventional example.

Further, the image data to be output is digital, so that A / D conversion or the like is not required when the image data is taken into a personal computer or a work station. Can be realized with a simpler configuration than that corresponding to.

FIG. 7 is a block diagram of a format conversion means 5 according to another embodiment of the present invention. The structure of the format conversion means 5 up to the preceding stage is the same as that of the embodiment of FIG.

In this embodiment, according to the mode designation,
VGA for square pixels similar to the above embodiment
(640 × 480 dots) format (first format), or a 320 × 240 dots (hereinafter referred to as “QVGA”) format (hereinafter referred to as “QVGA”) in which the number of dots and the number of lines in the VGA format are halved.
Or the number of dots and lines in the QVGA format is reduced to half.
It is converted into a format (third format) of × 120 dots (hereinafter referred to as “Q ² VGA”).

For this reason, the image data from the video signal processing means 4 in FIG. 1 is converted into the VGA format as in the above-described embodiment, and the VGA conversion means 31 (first conversion means) for generating a data valid timing signal. Means), QVGA conversion means 32 (second conversion means) for converting the VGA format to the QVGA format, and
The Q ₂ VGA conversion means 33 (third conversion means) for converting the GA format to the Q ² VGA format, and each of the conversion means 3 according to a mode designation signal for designating a conversion mode from a microcomputer, an operation switch or the like (not shown).
A valid / invalid control means 34 for prohibiting or allowing the conversion operation of 1, 32, 33 is provided.

The configuration of the VGA conversion means 31 is the same as that of the above-described embodiment, and a description thereof will be omitted.

The QVGA conversion means 32 for converting the VGA format from the VGA conversion means 31 into the QVGA format converts the data into 240 lines in the vertical direction by processing data of only one of the odd field and the even field. , And horizontally,
The average value of two adjacent dots is converted to 320 dots.

The field identification is performed using, for example, a field identification pulse output from a general timing IC or the like used for the driving means 7 in FIG.

In the horizontal direction, as in the above-described embodiment, when inputting and outputting image data in synchronization with the dot clock DCLK, one dot is output for every two dots.
You need to insert invalid dot data,
In this embodiment, a first signal indicating valid data timing is used.
A data active signal DTATV1 is generated.

FIG. 8 is a timing chart for explaining the conversion operation of the QVGA conversion means 32. FIG. 8A is a dot clock DCLK, FIG. 8B is a horizontal start signal LSTN, and FIG. ) Is the VGA output data from the VGA conversion means 31, FIG. 4D is a data active signal DTATV indicating whether the VGA output data is valid, and FIG. 4E is a data active signal DTATV delayed by one dot clock from the dot clock DCLK. (F) shows the result of calculating the average value of two adjacent dots, and (G) shows the first data active signal DACTTV indicating whether the output data is valid or invalid.
1 are shown.

The horizontal operation in the QVGA conversion means 32 uses an arithmetic unit that outputs an average value of adjacent data, and uses a dot clock DCL as a clock.
K, a data active signal DTATV is used as a clock enable, so that only valid data at the time of VGA conversion is input to the arithmetic unit.

Instead of the clock enable, a clock signal VCLK, which is an AND output of the dot clock DCLK and the data active signal DTATV delayed by one dot clock, may be used as a clock. As shown in FIG. 9, the circuit comprises two-stage flip-flops 81 and 82 and a computing unit 83.

First data active signal DTATV1
Is a signal whose level is inverted by the rise of the clock signal VCLK.

The data valid timing signal indicating the validity / invalidity of the QVGA output data of the QVGA conversion means 32 is an AND output of the first data active signal DTATV1 and the above-mentioned field identification pulse. Q ² VGA with output
The conversion means 32 is provided.

Next, the QVG from the QVGA conversion means 32
The Q ² VGA conversion means 33 for converting the A format to the Q ² VGA format will be described.

In this Q ₂ VGA conversion means 33, QVG
This is for converting the image data of the A format to 共 に both vertically and horizontally.

First, in the vertical direction, there are a method of calculating the average value of the data of two lines and combining them into one line, and a method of simply thinning out one line. In this embodiment,
The average value of the data of two lines is calculated and put together in one line. For this reason, since valid data is one line for every two lines, a line active signal LNAV signal indicating line valid / invalid is generated.

In the horizontal direction, QVGA conversion means 3
Similarly to the conversion by 2, conversion is performed by taking an average value of two adjacent dots, and a second data active signal DTATV2 indicating valid / invalid of the converted data is generated.

FIG. 10 is a block diagram of the Q ² VGA conversion means 33.

The line memory control circuit 91 writes the QVGA output data into the line memory 92 and controls the data one line before to be read out. QVG
The average value of the A output data and the current QVGA output data is calculated. This data is input to the horizontal calculator 94 to calculate the average value with the adjacent dots.

The line valid / invalid instruction signal generator 95 becomes active every other line based on the start signal START shown in FIG. 11C and the horizontal start signal LSTN shown in FIG. 11B. The line active signal LNAV shown in FIG. 11D is generated.

In the dot valid / invalid instruction signal generator 96, the horizontal start signal LSTN shown in FIG. 12B and the first data active signal DTA shown in FIG.
Based on CTV1 and dot clock DCLK shown in FIG.
A second data active signal DTATV2, which becomes active every other CTV1, is generated.

In the horizontal 1/2 operation unit 94, QVGA
The clock signal V shown in FIG.
In order to obtain the operation result shown in FIG. 12F using CLK as a clock, it cannot be obtained by averaging adjacent data actually input, and an operation is performed between data separated by one dot. There is a need.

For this reason, in this embodiment, the horizontal 1/2 operation unit 94 is provided with three stages of flip-flops 121 to 123, as shown in FIG. And the output of the flip-flop 123 is calculated by the calculator 125.

The data valid timing signal indicating the validity / invalidity of the Q ² VGA output data of the Q ² VGA conversion means 33 is the first data active signal DTATV1, the above-mentioned field identification pulse, the line active signal NAPV and the second data active signal DTATV2. And the data valid timing signal is Q ² VGA
Output with output.

The valid / invalid control means 34 shown in FIG.
According to the mode designation, for example, when the VGA mode is designated, only the conversion operation by the VGA conversion means 31 is allowed, and the QVGA conversion means 32 and Q ² V
The conversion operation of the GA conversion unit 33 is prohibited to pass the VGA output data and the data valid timing signal from the VGA conversion unit 31 through. When the QVGA mode is designated, the VGA conversion unit 31 and the QVGA
The conversion operation by the conversion means 32 is allowed, and Q ² VG
The conversion operation of the A conversion means 33 is prohibited to allow the QVGA output data and the data valid timing signal from the QVGA conversion means 32 to pass through, and when the Q ² VGA mode is designated, all the conversion means 31, 32 ,
33 conversion operations are allowed.

As described above, the QVGA conversion means 32 and the Q ² VGA conversion means 3 are provided after the VGA conversion means 31.
Provision of 3 enables conversion into a plurality of formats with a relatively simple circuit configuration as compared with the case where each conversion is performed independently.

Further, since the image data can be supplied to each of the conversion means 31 to 33 by the common dot clock DCLK, the conversion of the speed of the image data becomes unnecessary, and
It can be suitably used for an FPGA (field programmable gate array) or the like in which the number of clock lines is limited.

FIG. 14 shows Q ² VG according to another embodiment of the present invention.
FIG. 11 is a block diagram of the A conversion means 33, and portions corresponding to FIG. 10 are denoted by the same reference numerals.

The Q ² VGA conversion means 33 of this embodiment
The horizontal 1/2 arithmetic unit 134 is provided in a stage preceding the line memory 132 and the line memory control circuit 131
The data active signal DTATV2 is input, and the line memory clock of the line memory 132 is changed to the second data active signal DTAC indicating the validity of the horizontal 1/2 conversion data.
This is to match TV2.

FIG. 15 is a timing chart for explaining the operation of this embodiment. The line memory 132 of this embodiment is read and reset by the reset pulse shown in FIG. 15G, the pointer for writing is reset, and one data is read and written by the line memory clock shown in FIG. Read and write to the same address are performed simultaneously.

According to this embodiment, since only the data after the horizontal conversion is written, the capacity of the line memory can be reduced as compared with the configuration of FIG.

The other structure is the same as that of the above-described embodiment.

FIG. 16 is a block diagram of the format conversion means 5 according to still another embodiment of the present invention, and portions corresponding to FIG. 7 are denoted by the same reference numerals.

In this embodiment, the Q ² VGA conversion means 33
The edge emphasis means 35 is provided at the subsequent stage,
The invalidation control means 36 prohibits or permits the emphasis operation of the edge emphasis means 35.

The edge emphasizing means 35 is composed of a conventionally known edge emphasizing filter, and emphasizes the outline of an image whose outline has become unclear by the operations of the conversion means 31 to 33.

The other structure is the same as that of the above-described embodiment.

Next, application of the present invention to other formats and the like will be described.

For example, in addition to the CCD of 410,000 pixels as in the above-described embodiment, a CCD of 220,000 pixels (362 × 582)
Pixel), and the conversion in the first stage is CI
F (352 × 288 dots), and can be applied to the case where the conversion in the second stage is QCIF (176 × 144 dots).

In this case, the first conversion means corresponding to the VGA conversion means 31 of the above-described embodiment deletes the number of dots by 4 dots on the left and 6 dots on the right, and reduces the number of lines in one field. Is converted to CIF by deleting the upper three lines, and this image data is passed through the QVGA conversion means 32 of the above-described embodiment, and Q ² V
The processing by the GA conversion means 33 in the same manner as in the above-described embodiment can be converted into QCIF.

At this time, the Q ² VGA conversion means 33
Since the calculation of the average value in the horizontal direction is not a calculation between dots separated by one dot as in the above-described embodiment, but is a calculation between adjacent dots, the configuration in FIG. 13 cannot be used as it is. Therefore, as shown in FIG.
A selector 1 that can select either the output of the first-stage flip-flop 121 or the output of the second-stage flip-flop 122
24 may be provided so that conversion to Q ² VGA or conversion to QCIF similar to the above-described embodiment can be selected.

A 270,000 pixel CCD (512 × 49)
Corresponding to 2 pixels), conversion in the first stage is QVGA, be converted in a second stage to apply the present invention is also applicable to the case of Q ² VGA Tekiru.

In this case, the first conversion means corresponding to the VGA conversion means 31 of the above-described embodiment converts, for example, the number of dots from 16 to 10, and also changes the number of lines in one field up and down. The image data is converted to QVGA by deleting three lines at a time, and this image data is passed through the QVGA conversion means 32 of the above-described embodiment, and is similarly processed by the Q ² VGA conversion means 33 having the configuration of FIG. As a result, it can be converted to Q ² VGA.

As described above, in the conversion of the second stage, FIG.
Thus, the Q ² VGA conversion means 33 having the above configuration can be effectively used.

Therefore, in the case where the three conversion means 31 to 33 are formed into an ASIC as one circuit, the first conversion means
The conversion of the stage needs to be individually designed according to the application, but the conversion of the second stage is performed by Q ² as described above.
Since the VGA conversion means 33 can be shared, the versatility of the ASIC can be improved and the efficiency can be improved.

In the above-described embodiment, three conversion means are provided. However, as another embodiment of the present invention, the conversion means includes two conversion means.
Of course, four or more may be used.

[0101]

As described above, according to the present invention, digital image data obtained by A / D conversion of an output signal from an imaging means is converted into image data corresponding to a square pixel by digital processing. The digital image data obtained by A / D converting the output signal from the imaging means is
Once converted to analog image data, A / D
It is possible to provide a high-quality image without deterioration in image quality as compared with the conventional example of conversion, and it is possible to use a CCD other than a CCD corresponding to a square pixel as an imaging element of the imaging means.

According to the present invention, since the format conversion means includes the first to third conversion means and the control means for controlling each conversion operation, the format conversion means can cope with a plurality of formats. Since the image processing apparatus is provided with the outline emphasizing means for emphasizing the outline of the converted image data, it is possible to obtain a clear image of the outline.

According to the present invention, each conversion means inputs and outputs image data in synchronization with the same clock and generates a data valid timing signal indicating that the image data is in a converted format. Therefore, image data can be transmitted with a single clock, and there is no need to convert the data speed according to the format to be converted.

According to the present invention, the third conversion section of the third conversion means has a horizontal calculation section for reducing the number of dots to に よ っ て by a calculation process, and the horizontal calculation section is adjacent as calculation target data. Since either the data of both dots or the data of both dots separated by one dot can be selected, conversion to a different format can be supported.

According to the present invention, since the image data in which the number of dots is halved by the horizontal operation unit is written or read into the line memory of the third conversion unit, the number of dots is converted after the number of lines is converted. Thus, the capacity of the line memory can be reduced as compared with the configuration of FIG.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of the format conversion means of FIG.

FIG. 3 is a timing chart of an input signal to a format conversion unit in FIG. 1;

FIG. 4 is a timing chart of an input signal to a format conversion unit in FIG. 1;

FIG. 5 is a timing chart for explaining a vertical conversion operation of the format conversion means of FIG. 1;

FIG. 6 is a timing chart for explaining a horizontal conversion operation of the format conversion means of FIG. 1;

FIG. 7 is a block diagram of a format conversion unit according to another embodiment of the present invention.

FIG. 8 is a timing chart for explaining a QVGA conversion operation.

FIG. 9 is a block diagram of a calculation unit that performs horizontal 1/2 conversion.

FIG. 10 is a block diagram of Q ² VGA conversion means.

FIG. 11 is a timing chart for explaining the conversion operation of the Q ² VGA conversion means.

FIG. 12 is a timing chart for explaining the conversion operation of the Q ² VGA conversion means.

FIG. 13 is a block diagram of a calculation unit that performs horizontal 1/2 conversion.

FIG. 14 is a block diagram of a Q ² VGA converter according to another embodiment of the present invention.

FIG. 15 is a timing chart for explaining the operation of FIG. 14;

FIG. 16 is a block diagram of a format conversion unit according to another embodiment of the present invention.

FIG. 17 is a block diagram of a calculation unit according to another embodiment of the present invention.

[Explanation of symbols]

1 imaging unit 2 pre-processing means 3 A / D converter 4 video signal processing unit 5 format converting means 31 VGA converter 32 QVGA conversion means 33 Q ² VGA conversion means 34 enable / disable control means 35 edge enhancement means

Claims (8)

(57) [Claims] An imaging unit that converts imaging light from an incident subject into an electric signal; a preprocessing unit that performs preprocessing such as noise suppression and automatic gain control on an output signal from the imaging unit; A for converting an output signal from the preprocessing means into a digital signal
/ D conversion means, signal processing means for separating a luminance signal and a color signal from digital data output from the A / D conversion means, and digital image data output from the signal processing means corresponding to square pixels by digital processing. and format conversion means for converting the image data of the format
The format conversion means is provided from the signal processing means.
Digital image data corresponding to square pixels
A first converting means for converting to image data of a first format
And image data converted to the first format
Is converted to a second format having half the number of lines and the number of dots.
Second converting means for converting the image data into image data of
The image data converted to the format
Image data of the third format with half the number of dots
Conversion means for converting data into data and a format to be converted
The conversion operation of each of the conversion means according to a designation signal for designating
An image conversion apparatus comprising: a control unit that controls an operation . 2. The format conversion means according to claim 1, wherein
Provided with an outline emphasis means for emphasizing the outline of the image data
The image conversion device according to claim 1, wherein 3. The first conversion means synchronizes with a clock.
Digital image data input by the first format
The image data is converted into image data including
A first converter for outputting in synchronization with the lock;
Data validity data indicating that the image data is
A first timing signal generator for generating an imaging signal;
A, the second converting means is input in synchronization with the clock
The image data in the first format,
Converted to image data containing format image data
A second converter for outputting in synchronization with the clock;
Data indicating that the image data of the second format
Generating a second timing signal for generating a valid timing signal
And the third conversion means receives the signal in synchronization with the clock.
Image data including image data of the second format
An image including image data of the third format.
A third method of converting the data into data and outputting the data in synchronization with the clock
A conversion unit and image data of the third format.
A third timer for generating a data valid timing signal indicating that
And an imaging signal generator.
Is the image conversion device according to 2. 4. The method according to claim 1, wherein the second conversion unit is configured to output a first format.
One of the odd or even fields of the image data
Field image data to reduce the number of lines to half
Is intended to, the third conversion unit, the number of dots by the processing 1/2
And a horizontal operation unit for calculating the data to be operated.
Data of two adjacent dots or one dot apart
One of the two dot data
The image conversion device according to claim 3. 5. The method according to claim 1, wherein the third conversion unit is configured to
A vertical operation unit that reduces the number of inputs to と
A horizontal operation unit for reducing the number of dots to １ ／,
The calculating unit converts the number of dots into half in the horizontal calculating unit.
Image data is written and read
It has a line memory and is read from this line memory.
Of the image data from the horizontal operation unit
4. The image conversion device according to claim 3, wherein the image conversion device performs arithmetic processing . 6. The method according to claim 1, wherein the first format has a resolution of 64.
2. A VGA format of 0 × 480 dots.
6. The image conversion device according to any one of claims 1 to 5, 7. The method according to claim 1, wherein the first format has a resolution of 35.
6. A CIF of 2 × 288 dots according to claim 1.
An image conversion device according to any of the preceding claims . 8. The control device according to claim 1 , wherein said second conversion means controls said control means.
The image data of the first format is converted to the second
Format image data, or convert
Output directly to the third conversion means without performing
And the third conversion means, in accordance with the control of the control means,
The images data of the second format of the third format
Convert to image data or use the first format
Convert image data or image data in the second format
2. The method according to claim 1, wherein the data is output without conversion.
8. The image conversion device according to any one of items 7 to 7.