KR20040001899A - Method for fabricating capacitor in semiconductor device - Google Patents
Method for fabricating capacitor in semiconductor device Download PDFInfo
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- KR20040001899A KR20040001899A KR1020020037233A KR20020037233A KR20040001899A KR 20040001899 A KR20040001899 A KR 20040001899A KR 1020020037233 A KR1020020037233 A KR 1020020037233A KR 20020037233 A KR20020037233 A KR 20020037233A KR 20040001899 A KR20040001899 A KR 20040001899A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000002425 crystallisation Methods 0.000 claims abstract description 4
- 230000008025 crystallization Effects 0.000 claims abstract description 4
- 239000010409 thin film Substances 0.000 claims description 45
- 239000010408 film Substances 0.000 claims description 34
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000000678 plasma activation Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 2
- 238000004151 rapid thermal annealing Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 229910052741 iridium Inorganic materials 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910019899 RuO Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- VRIVJOXICYMTAG-IYEMJOQQSA-L iron(ii) gluconate Chemical compound [Fe+2].OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O.OC[C@@H](O)[C@@H](O)[C@H](O)[C@@H](O)C([O-])=O VRIVJOXICYMTAG-IYEMJOQQSA-L 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 집적회로의 제조방법에 관한 것으로, 특히 반도체 장치의 캐패시터 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.
반도체 소자, 특히 DRAM(Dynamic Random Access Memory)의 반도체 메모리의 집적도가 증가함에 따라 정보 기억을 위한 기본 단위인 메모리 셀의 면적이 급격하게 축소되고 있다.As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.
이러한 메모리 셀 면적의 축소는 셀 캐패시터의 면적 감소를 수반하여, 센싱 마진과 센싱 속도를 떨어뜨리고, α-입자에 의한 소프트 에러(Soft Error)에 대한 내구성이 저하되는 문제점을 유발하게 된다. 따라서, 제한된 셀 면적에서 충분한 정전용량을 확보할 수 있는 방안이 필요하게 되었다.Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.
캐패시터의 정전용량(C)은 하기의 수학식 1과 같이 정의된다.The capacitance C of the capacitor is defined as in Equation 1 below.
여기서, ε은 유전률, As는 전극의 유효 표면적, d는 전극간 거리를 각각 나타낸 것이다.Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.
따라서, 캐패시터의 정전용량을 늘리기 위해서는 전극의 표면적을 넓히거나,유전체 박막의 두께를 줄이거나, 유전률을 높여야 한다.Therefore, in order to increase the capacitance of the capacitor, the surface area of the electrode, the thickness of the dielectric thin film, or the dielectric constant must be increased.
이 중에서 전극의 표면적을 넓히는 방안이 제일 먼저 고려되어 왔다. 콘케이브(concave) 구조, 실린더(sylinder) 구조, 다층 핀(fin) 구조 등과 같은 3차원 구조의 캐패시터는 모두 제한된 레이아웃 면적에서 전극의 유효 표면적을 증대시키기 위하여 제안된 것이다. 그러나, 이러한 방법은 반도체 소자가 초고집적화 되면서 전극의 유효 표면적을 증대시키는데 한계를 보이고 있다.Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of electrodes in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.
그리고, 전극간 거리(d)를 최소화하기 위해 유전체 박막의 두께를 감소시키는 방안은 유전체 박막의 두께가 감소함에 따라 누설전류가 증가하는 문제 때문에 역시 그 한계에 직면하고 있다.In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.
따라서, 근래에 들어서는 주로 유전체 박막의 유전율의 증대를 통한 캐패시터의 정전용량 확보에 초점을 맞추어 연구, 개발이 진행되고 있다. 전통적으로, 실리콘산화막이나 실리콘질화막을 유전체 박막 재료로 사용한 소위 NO(Nitride-Oxide) 구조의 캐패시터가 주류를 이루었으나, 최근에는 Ta2O5, (Ba,Sr)TiO3(이하 BST라 함) 등의 고유전체 물질이나, (Pb,Zr)TiO3(이하 PZT라 함), (Pb,La)(Zr,Ti)O3(이하 PLZT라 함), SrBi2Ta2O9(이하 SBT라 함), SrBi2(Ta1-x,Nbx)2O9(이하 SBTN이라 함), Bi4-xLaxTi3O12(이하 BLT라 함), Bi4Ti3O12(이하, BIT라 함)등의 강유전체 물질을 유전체 박막 재료로 적용하고 있다.Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta 2 O 5 , (Ba, Sr) TiO 3 (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO 3 (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O 3 (hereinafter referred to as PLZT), SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) SrBi 2 (Ta 1-x , Nbx) 2 O 9 (hereinafter referred to as SBTN), Bi 4-x La x Ti 3 O 12 (hereinafter referred to as BLT), Bi 4 Ti 3 O 12 (hereinafter referred to as BIT Ferroelectric materials are applied as dielectric thin film materials.
이러한 고유전체 물질 또는 강유전체 물질을 유전체 박막 재료로 사용하는 고유전체 캐패시터 또는 강유전체 캐패시터를 제조함에 있어서, 고유전체 물질 또는 강유전체 물질 특유의 유전 특성을 구현하기 위해서는 유전체 주변 물질 및 공정의 적절한 제어가 수반되어야 한다.In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric materials or ferroelectric materials. do.
일반적으로, 고유전체 캐패시터나 강유전체 캐패시터의 상, 하부전극 물질로서 노블메탈(noble metal) 또는 이들의 화합물, 예컨대 Pt, Ir, Ru, RuO2, IrO2등을 사용하고 있다.In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO 2 , IrO 2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.
도1a 내지 도1d는 종래기술에 의한 반도체 장치의 캐패시터 제조방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.
먼저 도1a에 도시된 바와 같이, 활성영역(11)이 형성된 반도체기판(10)상에 층간절연막(12)을 형성한 후, 층간절연막(12)을 관통하여 반도체기판(10)의 활성영역(11)과 연결되는 콘택홀을 형성한다. 이어서 콘택홀을 도전성 물질로 매립하여 콘택플러그(13)를 형성한다.First, as shown in FIG. 1A, the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, and then penetrates the interlayer insulating film 12 to form an active region ( A contact hole connected to 11) is formed. Subsequently, the contact hole is filled with a conductive material to form the contact plug 13.
이어서 콘택플러그(13)과 연결되는 Pt등의 금속막으로 하부전극(14)을 형성한다.Subsequently, the lower electrode 14 is formed of a metal film such as Pt connected to the contact plug 13.
이어서 도1b에 도시된 바와 같이, 하부전극(14)을 덮을 수 있도록 캐패시터절연막(15)를 형성한다.Subsequently, as shown in FIG. 1B, a capacitor insulating film 15 is formed to cover the lower electrode 14.
이어서 도1c에 도시된 바와 같이, 하부전극(14)이 노출되도록 캐패시터절연막을 화학적기계적 연마 공정등을 이용하여 제거한다. 이어서 그 상부에 유전체 박막(17)을 형성하고 그 상부에 상부전극용 전도막(18)을 형성한다. 상기와 같이 캐패시터를 형성하게 되면 상부전극을 형성하기 전에 따로 평탄화 작업을 하지 않아도 되어 캐채시터의 구조로 인한 단차 때문에 생기는 여러가지 문제가 해결된다.Subsequently, as shown in FIG. 1C, the capacitor insulating film is removed using a chemical mechanical polishing process or the like so that the lower electrode 14 is exposed. Subsequently, a dielectric thin film 17 is formed thereon, and an upper electrode conductive film 18 is formed thereon. When the capacitor is formed as described above, it is not necessary to planarize separately before forming the upper electrode, thereby solving various problems caused by the step due to the structure of the capacitor.
이어서 도1d에 도시된 바와 같이, 상부전극용 전도막(18)을 패터닝하여 상부전극(19)을 형성한다.Subsequently, as shown in FIG. 1D, the upper electrode conductive film 18 is patterned to form the upper electrode 19.
여기서 유전체 박막으로는 SBT,SBTN, BIL, PZT등의 강유전체 물질을 사용하거나 STO, BST 등의 고유전체 물질을 사용하게 됨에 따라 유전체 박막을 형성하고 난 후 유전율 향상을 위한 열저리 공정이 필수적으로 필요하게 되었다. 그러데 전술한 바와 같이 유전체 박막을 형성하고 나서 열처리를 하게 되면 하부전극 주위의 캐패시터 절연막이 형성되어 있는 구조이기 때문에, 열처리 공정시에 캐패시터 절연막으로 부터 P,B, Si등이 유전체박막으로 확산 침투되어 유전체 박막의 결정성이 큰 차이를 가지기 된다.Since dielectric thin films are made of ferroelectric materials such as SBT, SBTN, BIL, and PZT, or high-dielectric materials such as STO and BST, a heat treatment process is necessary to improve the dielectric constant after forming a dielectric thin film. Was done. However, as described above, when the dielectric thin film is formed and then subjected to heat treatment, the capacitor insulating film around the lower electrode is formed. Therefore, P, B, Si, etc. diffuse and penetrate into the dielectric thin film from the capacitor insulating film during the heat treatment process. The crystallinity of the dielectric thin film has a large difference.
이로 인하여 유전체박막의 특성이 메모리 소자의 단위 셀에 따라 균일성이 극도로 나빠져 메모리 소자의 동작상의 신뢰성이 저하되는 문제점이 있다.As a result, the uniformity of the dielectric thin film becomes extremely poor depending on the unit cell of the memory device, thereby deteriorating operational reliability of the memory device.
본 발명은 고집적 반도체 장치의 동작상의 신뢰성이 향상된 캐패시터 제조방법을 제공함을 목적으로 한다.An object of the present invention is to provide a capacitor manufacturing method with improved operational reliability of a highly integrated semiconductor device.
도1a 내지 도1d는 종래기술에 따른 반도체 장치의 캐패시터 제조방법을 나타내는 공정단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.
도2a 내지 도2e는 본 발명의 바람직한 실시예에 따른 반도체 장치의 캐패시터 제조방법을 나타내는 공정단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20 : 기판20: substrate
21 : 활성영역21: active area
22 : 층간절연막22: interlayer insulating film
23 : 콘택플러그23: Contact Plug
24 : 하부전극용 전도막24: conductive film for lower electrode
25 : 유전체 박막25: dielectric thin film
26 : 하부전극26: lower electrode
27 : 캐패시터 절연막27: capacitor insulating film
28 : 상부전극28: upper electrode
상기의 목적을 달성하기 위해 본 발명은 기판상에 하부전극용 전도막을 형성하는 단계; 상기 하부전극용 전도막상에 유전체 박막을 형성하는 단계; 상기 유전체 박막의 결정화를 위한 열공정을 실시하는 단계; 상기 하부전극용 전도막 및 상기 유전체 박막을 동시에 패터닝하여 하부전극 및 패터닝된 유전체 박막을 형성하는 단계; 및 패턴닝된 상기 유전체 박막 상에 상부전극을 형성하는 단계를 포함하는 반도체 장치의 캐패시터 제조방법이 제공된다.In order to achieve the above object, the present invention comprises the steps of forming a conductive film for the lower electrode on the substrate; Forming a dielectric thin film on the conductive film for the lower electrode; Performing a thermal process for crystallizing the dielectric thin film; Simultaneously patterning the conductive film for the lower electrode and the dielectric thin film to form a lower electrode and a patterned dielectric thin film; And forming an upper electrode on the patterned dielectric thin film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2e는 본 발명에 의한 바람직한 실시예에 따른 반도체장치의 캐패시터 제조방법을 나타내는 도면이다.2A to 2E are views showing a capacitor manufacturing method of a semiconductor device according to a preferred embodiment of the present invention.
먼저 도2a에 도시된 바와 같이, 활성영역(21)이 형성된 반도체기판(20)상에 층간절연막(22)을 형성한 후, 층간절연막(22)을 관통하여 반도체기판(20)의 활성영역(21)과 연결되는 콘택홀을 형성한다. 이어서 콘택홀을 도전성 물질로 매립하여 콘택플러그(23)를 형성한다. 여기서 콘택홀 내부에 Ti를 증착하고 열공정을 실시하여 활성영역(21)과의 계면에 오믹 콘택을 위한 티타늄실리사이드를 형성할 수 있으며, 텅스텐을 이용하여 콘택플러그(23)을 형성한다. 또한 콘택플러그(23) 상단은 후속 공정에서 하부전극으로 사용될 물질(예컨대 이리듐)과 콘택플러그에 사용된 텅스텐과의 상호 물질 확산 방지를 위한 베리어 메탈로 TiN을 형성할 수 있다.First, as shown in FIG. 2A, the interlayer insulating film 22 is formed on the semiconductor substrate 20 on which the active region 21 is formed, and then penetrates the interlayer insulating film 22 to form the active region of the semiconductor substrate 20 ( A contact hole connected to 21 is formed. Subsequently, the contact hole is filled with a conductive material to form the contact plug 23. Here, Ti is deposited inside the contact hole and thermal processes are performed to form titanium silicide for ohmic contact at the interface with the active region 21, and the contact plug 23 is formed using tungsten. In addition, the upper end of the contact plug 23 may form TiN as a barrier metal for preventing mutual material diffusion between a material (eg, iridium) used as a lower electrode in a subsequent process and tungsten used in the contact plug.
이어서 하부전극용 전도막(24)를 기판전면에 형성한다.Subsequently, a lower electrode conductive film 24 is formed on the front surface of the substrate.
이어서 도2b에 도시된 바와 같이, 하부전극용 전도막(24) 상부에 유전체 박막(25)을 형성한다. 여기서 유전체 박막(25)의 핵생성은 RTA(rpaid thermalanneal)방식으로 400~800℃ 범위로 공정을 진행하고, 결정화를 위한 열공정은 로(furnace)에서 500~800℃ 범위에서 O2,N2O,N2+O2,H2O,H2O2등의 산화가스를 사용하여 공정을 진행한다.Subsequently, as shown in FIG. 2B, a dielectric thin film 25 is formed on the conductive film 24 for the lower electrode. The dielectric nucleation of the thin film 25 is RTA (rpaid thermalanneal) scheme 400 ~ O 2, 500 ~ at 800 ℃ range from tear Chung by (furnace) for crystallization proceeds the process, and to 800 ℃ range N 2 O The process is performed using oxidizing gases such as, N 2 + O 2 , H 2 O, H 2 O 2 .
이 때 유전체 박막(25)의 하부에는 하부전극용 전도막(24)가 형성되어 있으므로 종래의 P,B,Si 등의 물질이 유전체 박막(25)으로 침투하지 않는다. 유전체 박막(25)으로는 SBT, SBTN,BIT,BLT 또는 PZT 중에서 선택된 하나를 이용하여 50 ~ 3000Å 범위의 두께로 형성한다.At this time, since the lower electrode conductive film 24 is formed under the dielectric thin film 25, materials such as P, B, and Si do not penetrate into the dielectric thin film 25. The dielectric thin film 25 is formed to have a thickness in the range of 50 to 3000 mm by using one selected from SBT, SBTN, BIT, BLT, or PZT.
이어서 도2c에 도시된 바와 같이, 하부전극용 전도막(24) 및 유전체 박막(25)을 동시에 패터닝하여 하부전극(24)과 패터닝된 유전체 박막(25)을 형성한다. 하부전극용 전도막(24) 및 유전체 박막(25)을 동시에 패터닝시에 플라즈마 활성화 에너지를 사용하여 식각가스로는 Cl,Ar, N2를 사용하여 플라즈마 파워는 500 ~ 3000watt 범위에서, 압력은 0.5mtorr ~ 30torr 범위에서 공정을 진행한다.Subsequently, as shown in FIG. 2C, the lower electrode conductive film 24 and the dielectric thin film 25 are simultaneously patterned to form the lower electrode 24 and the patterned dielectric thin film 25. When the conductive film 24 and the dielectric thin film 25 for the lower electrode are simultaneously patterned, plasma activation energy is used and Cl, Ar, and N 2 are used as etching gases. The plasma power is in the range of 500 to 3000 watts, and the pressure is 0.5 mtorr. Process in the range of ~ 30 torr.
여기서 하부전극은 전극물질로 사용된 백금, 열공정시 산소침투 방지를 위한 이리듐과 백금과 이리듐의 상호 확산 방지를 위한 이리듐 옥사이드를 적층한 Pt/IrO2/Ir으로 형성할 수 있으며,백금은 500 ~ 3000Å 범위로 형성하고, IrO2는 50 ~ 1000Å 범위, Ir은 50 ~ 3000Å 범위로 형성한다.The lower electrode may be formed of Pt / IrO 2 / Ir laminated with platinum used as an electrode material, iridium for preventing oxygen infiltration during thermal processing, and iridium oxide for preventing interdiffusion of platinum and iridium. It is formed in the range of 3000 kHz, IrO 2 is formed in the range of 50 ~ 1000 Ir, Ir is formed in the range of 50 ~ 3000 Å.
이어서 도2d에 도시된 바와 같이, 하부전극(24)와 유전체 박막(25)를 덮을 수 있도록 캐패시터 절연막(27)을 형성하고, 유전체 박막(25)가 노출되도록 화학적 기계적 연마 공정등을 이용하여 캐패시터 절연막(27)을 제거한다.Subsequently, as shown in FIG. 2D, the capacitor insulating film 27 is formed to cover the lower electrode 24 and the dielectric thin film 25, and the capacitor is formed using a chemical mechanical polishing process to expose the dielectric thin film 25. The insulating film 27 is removed.
여기서 캐패시터 절연막(27)는 2000~ 10000Å 범위의 두께로 USG(Undoped-Silicate Glass), PSG(Phospho-Silicate Glass), BPSG(Boro-Phospho-Silicate Glass), HDP(High density Plasma) 산화막등을 사용하거나 열적산화막(Thermal Oxide; 퍼니스에서 600~1,100℃사이의 고온으로 실리콘 기판을 산화시켜 형성하는 막)으로 형성할 수 있다.Here, the capacitor insulating film 27 has a thickness in the range of 2000 to 10000 Å, using Undoped-Silicate Glass (USG), Phospho-Silicate Glass (PSG), Boro-Phospho-Silicate Glass (BPSG), and High Density Plasma (HDP) oxide film. Or a thermal oxide film (film formed by oxidizing a silicon substrate at a high temperature between 600 and 1,100 ° C. in a furnace).
이어서 도2e에 도시된 바와 같이, 패터닝된 유전체 박막(25) 상부에 500~3000Å범위의 두께로 상부전극(27)을 형성한다. 상부전극으로는 Pt, Ir, Ru, IrOx, W, TiN, 폴리실리콘막등을 사용할 수 있다.Subsequently, as illustrated in FIG. 2E, the upper electrode 27 is formed on the patterned dielectric thin film 25 to have a thickness in the range of 500 to 3000 microseconds. Pt, Ir, Ru, IrOx, W, TiN, a polysilicon film can be used as the upper electrode.
전술한 바와 같이 하부전극과 유전체 박막을 동시에 패터닝한후에 유전체박막의 핵생성 및 결정화 공정을 진행하여 캐패시터를 제조하게 되면, 반도체 소자의 단위셀 마다 유전체 박막의 결정성의 차이를 제거하여 안정적이고 신뢰성 높은 캐패시터를 제조할 수 있다.As described above, when the lower electrode and the dielectric thin film are patterned at the same time, the nucleation and crystallization process of the dielectric thin film is performed to manufacture the capacitor. The capacitor is stable and reliable by removing the difference in the crystallinity of the dielectric thin film for each unit cell of the semiconductor device. Can be prepared.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 의해 유전체 박막의 결정성에서 균일하여 신뢰성 높은 고집적 반도체 장치의 캐패시터를 제조할 수 있다.According to the present invention, it is possible to manufacture a capacitor of a highly integrated semiconductor device which is uniform in the crystallinity of the dielectric thin film and reliable.
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| KR101037767B1 (en) * | 2011-04-21 | 2011-05-27 | 대동전자(주) | The phase prediction device using variation contact resistance of the contact point of circuit braker in live wire state |
| KR101060763B1 (en) * | 2004-07-30 | 2011-08-31 | 주식회사 하이닉스반도체 | Ferroelectric Capacitor Manufacturing Method for Semiconductor Device |
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| KR100551884B1 (en) * | 1999-12-29 | 2006-02-10 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| KR100390938B1 (en) * | 2000-02-09 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| KR100680464B1 (en) * | 2000-06-28 | 2007-02-08 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
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| KR101060763B1 (en) * | 2004-07-30 | 2011-08-31 | 주식회사 하이닉스반도체 | Ferroelectric Capacitor Manufacturing Method for Semiconductor Device |
| KR101037767B1 (en) * | 2011-04-21 | 2011-05-27 | 대동전자(주) | The phase prediction device using variation contact resistance of the contact point of circuit braker in live wire state |
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