KR20040059848A - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of obtaining a stable capacitor hole and simplifying the process. CONSTITUTION: Gate patterns(33) are formed on a semiconductor substrate(30) with active regions(32a). An interlayer dielectric(34) and a capacitor insulating layer(36) are sequentially formed on the resultant structure. A capacitor hole(37) is formed to expose the active regions by patterning the capacitor insulating layer and the interlayer dielectric. A lower electrode is formed in the capacitor hole. A dielectric film and an upper electrode are sequentially formed on the lower electrode.

Description

Method for fabricating capacitor in semiconductor device

TECHNICAL FIELD The present invention relates to a semiconductor manufacturing process, and more particularly, to a capacitor manufacturing process of a semiconductor device.

As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Therefore, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = ε · As / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of the electrode in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.

In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.

Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta ₂ O ₅ , (Ba, Sr) TiO ₃ (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO ₃ (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O ₃ (hereinafter referred to as PLZT), SrBi2Ta2O ₉ (hereinafter referred to as SBT), Bi Ferroelectric materials such as _4-x La _x Ti ₃ O ₁₂ (hereinafter referred to as BLT) are applied as the dielectric thin film material.

In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric materials or ferroelectric materials. do.

Generally, noble metal or a compound thereof, such as platinum (Pt), iridium (Ir), ruthenium (Ru), ruthenium oxide (RuO ₂ ), as the upper and lower electrode materials of the high dielectric capacitor or the ferroelectric capacitor, Iridium oxide (IrO ₂ ) and the like are used.

However, by using a metal film as the upper and lower electrodes of the capacitor, the problem of adhesion between the metal film and the insulating film has emerged as a new problem in manufacturing the capacitor of the semiconductor device. This is because the metal film is deteriorated in adhesion properties with an oxide film or the like used as an insulating film due to its characteristics. In addition, since the upper and lower electrodes of the capacitor use a metal film, various processes including a silicide process for ohmic contact characteristics with a storage node contact plug formed of polysilicon having a lower structure are added, thereby making the manufacturing process complicated. I have a problem.

1A to 1F are process cross-sectional views showing a capacitor manufacturing method of a semiconductor device according to the prior art. Hereinafter, a capacitor manufacturing method according to the prior art will be described with reference to the accompanying drawings.

As shown in FIG. 1A, on the semiconductor substrate 10 on which the device isolation layer 11, the active regions 12a and 12b, and the gate pattern 13 (the pattern including the gate electrode, the gate insulating layer, the gate spacer, etc.) are formed. After the first interlayer insulating film 12 is formed on the bit line, the bit line contact hole through which the active region 12b of the semiconductor substrate 10 is exposed is formed through the first interlayer insulating film 12. The bit line contact hole is filled with a conductive material to form a bit line contact plug 15 ′ connected to the previously formed bit line 15.

Subsequently, as illustrated in FIG. 1B, a storage node is formed by forming a second interlayer insulating film 15 on the front surface of the substrate, and selectively removing the first and second interlayer insulating films 14 and 16 so that the active region 12a is exposed. (storage node) A contact hole 17 'is formed.

Subsequently, as shown in FIG. 1C, the storage node contact plug 17 is formed by filling the storage node contact hole 17 ′ with polysilicon, and the upper portion of the storage node contact plug 17 is recessed. If possible, the polysilicon formed on the upper portion is removed. Subsequently, titanium is formed in the recessed portion of the storage node contact plug and then reacts with polysilicon of the titanium and the storage node contact plug 17 through a thermal process to form the titanium silicide layer 18. A titanium nitride film 19 is then formed on the titanium silicide film 18. Here, the titanium silicide film 18 is for ohmic contact between the metal lower electrode to be formed in a subsequent process and the contact plug 17 formed of polysilicon, and the titanium silicide film 18 is a barrier metal for preventing material diffusion between them. It is used as a membrane.

Subsequently, as shown in FIG. 1D, an insulating film 20 for forming a capacitor is formed on the entire surface of the substrate so that the capacitor is formed thereon.

Subsequently, as shown in FIG. 1E, the capacitor forming insulating film 20 is selectively removed to expose the titanium nitride film 19 formed on the upper end of the storage node contact plug 17 to form the capacitor hole 22. To form.

Subsequently, as shown in FIG. 1F, the lower electrode 24 is formed in the capacitor hole 22, and the dielectric thin film 23 is formed on the lower electrode 24. Subsequently, an upper electrode is formed to fill the capacitor hole 22. As the material for the upper and lower electrodes, platinum, iridium, ruthenium, ruthenium oxide, iridium oxide, and the like are used as described above.

Meanwhile, as semiconductor memory devices are highly integrated, the area corresponding to one unit cell is gradually reduced, and the area for manufacturing cell capacitors has also been gradually reduced. As a result, the depth of the capacitor hole formed to secure a constant capacity of the cell capacitor is getting deeper and narrower. In the 0.10㎛ technology, the depth of the capacitor hole is required to be 1.5㎛ or more to secure the required capacitor capacity.However, in current process equipment, it is large to stably form a capacitor hole having a depth of about 1.5㎛ in a very narrow state. It is a problem.

In particular, the upper end of the capacitor hole, which is formed by selectively removing the capacitor insulating layer, becomes wider while the lower end becomes narrower, which makes it difficult to stably expose the upper end of the storage contact plug. If the substrate is overetched more than the thickness of the capacitor forming insulating layer in order to stably expose the storage node contact plug, the titanium nitride and the titanium silicide layers formed thereunder may be damaged.

2 is a process sectional view showing a problem in manufacturing a capacitor according to the prior art.

2 shows that when the capacitor formation insulating layer 21 is selectively etched to form the capacitor hole, the titanium nitride 19 and the titanium silicide 18 on the lower storage node contact plug are removed due to overetching, thereby causing the storage node contact plug to be removed. The polysilicon of (12a) is exposed (A, B). If the process is completed by continuing the process while the polysilicon is exposed, the contact resistance between the lower electrode of the capacitor and the active region becomes worse.

In addition, as the metal is used as the upper and lower electrodes, there is a problem in that adhesion characteristics between the metal electrode and the capacitor forming insulating film are also deteriorated.

An object of the present invention is to provide a method of manufacturing a capacitor that can stably form a capacitor hole in a highly integrated memory device, thereby simplifying a process step, producing a reliable capacitor in a subsequent process, and reducing a manufacturing cost.

1A to 1F are process cross-sectional views showing a capacitor manufacturing method of a semiconductor device according to the prior art.

Fig. 2 is a process sectional view showing a problem when manufacturing a capacitor according to the prior art.

3A to 3H are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

30: substrate

31: device isolation film

32a, 32b: active area

33: gate pattern

34: interlayer insulating film

35: bit line pattern

36: insulating film for capacitor formation

37: capacitor hole

38: titanium film

39: titanium nitride film

40: titanium silicide film

41: lower electrode

42: dielectric thin film

43: upper electrode

The present invention for achieving the above object comprises the steps of forming an interlayer insulating film for insulating between the pre-formed word line pattern on the substrate on which the active region is formed; Forming an insulating film for forming a capacitor on the interlayer insulating film; Forming a capacitor hole by patterning the interlayer insulating film and the capacitor forming insulating film to expose the active region; Forming a lower electrode in the capacitor hole; Forming a dielectric thin film on the lower electrode; It provides a method of manufacturing a capacitor of a semiconductor device comprising the step of forming an upper electrode on the dielectric thin film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3H are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention. Hereinafter, a capacitor manufacturing method according to the present embodiment will be described with reference to the accompanying drawings.

First, as shown in FIG. 3A, the semiconductor substrate 30 on which the device isolation layer 31, the active regions 32a and 32b, and the gate pattern 33 (the pattern including the gate electrode, the gate insulating layer, and the gate spacer) are formed. After the interlayer insulating film 32 is formed on the bit line, the bit line contact hole through which the active region 32b of the semiconductor substrate 30 is exposed is formed through the interlayer insulating film 32. The bit line contact hole is filled with a conductive material to form a bit line contact plug 35 ′ connected to the previously formed bit line 35.

Subsequently, as shown in FIG. 3B, an insulating film 36 for forming a capacitor is formed on the entire surface of the substrate. The capacitor forming insulating film 36 may include a high density plasma (HDP) oxide film, a plasma enhanced-tetraethylorthosilicate (PE-TEOS) film, an ozone TEOS film, a Boro-Phospho-Silicate Glass (BPSG) film, and a HTO (High Temperature Oxidation, 830) film. Oxide film deposited at a temperature above about ℃, LTO (low temperauure deposition oxide) film, deposited at a temperature of about 400 ~ 450 ℃, MTO (Medium Temperature Deposition of Oxide, about 800 ℃) It is formed using one film selected from the films.

Subsequently, as shown in FIG. 3C, the capacitor forming insulating film 36 and the interlayer insulating film 32 are selectively removed at the same time to form the capacitor hole 37 so as to expose the active region 32a on the substrate.

Subsequently, as shown in FIG. 3D, a titanium film 38 is formed on the front surface of the substrate including the inside of the capacitor hole 37 to a thickness in the range of 10 to 500 kV, and the titanium nitride film 39 is formed on the titanium film 38. ). The titanium film 38 and the titanium nitride film 39 are selected from chemical vapor deposition, atomic layer depostion, and plasma enhanced atomic layer depostion. Deposition by the method of. In addition, the titanium nitride film 39 is formed to a thickness of 10 ~ 1000Å range.

The titanium nitride film 39 primarily serves to prevent material diffusion between the lower electrode and the active region 32a to be formed in a subsequent process, and also serves as a seed layer of the metal to be formed as the lower electrode. .

Subsequently, as shown in FIG. 3E, the active region 32a and the titanium film 38 on the substrate react with each other through a rapid thermal anneal and furnace anneal process so that the active region 32a and the titanium are reacted with each other. The titanium silicide film 40 is formed between the films 38. When the rapid heat treatment process is used, the process is performed at a temperature in the range of 600 to 900 ° C. In the heat process, N ₂ , Ar, Ne, He, N ₂ + Ar, and the like are used as a reducing atmosphere. The titanium silicide film 40 is a film for forming ohmic contact between the titanium nitride film 39 and the active region 32a.

Subsequently, as shown in FIG. 3F, a lower electrode 41 is formed on the titanium nitride film 39. The lower electrode 41 is deposited by one method selected from chemical vapor deposition, atomic layer deposition, and plasma enhanced atomic layer depostion. It is formed to a thickness of 1000Å range.

The lower electrode 41 includes platinum (Pt), tungsten (W), tungsten nitride film (WN), titanium nitride (TiN), ruthenium (Ru), ruthenium oxide (RuO ₂ ), iridium (Ir), and iridium One selected from oxide (IrO ₂ ) is used.

3G, the lower electrode 41, the titanium nitride film 39, and the titanium film 38 are removed so as to remain only inside the capacitor hole using a chemical mechanical process or an etch back process.

Subsequently, as shown in FIG. 3H, the dielectric thin film 42 is formed on the lower electrode 41, and the upper electrode 43 is formed on the dielectric thin film 42 so that the capacitor hole 37 is embedded.

Here, as the dielectric thin film 43, one selected from Si ₃ N ₄ , Al ₂ O ₃ , HfO ₃ , Ta ₂ O ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , (Pb, Zr) TiO ₃ is used. , By chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition method selected from one of the methods, and the thickness of 10 ~ 500Å range Deposit at a temperature in the range of 200-700 ° C. N ₂ , Ar, O ₂ , N ₂ O, H ₂ O ₂ , H ₂ O, N ₂ + O _2, and the like are used as the reaction gas when the dielectric thin film is deposited.

As the upper electrode 43, one selected from platinum, tungsten, tungsten nitride, titanium nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, and tantalum nitride (TaN) is used, and chemical vapor deposition is performed. ), The atomic layer deposition method (atomic layer depostion), plasma enhanced atomic layer deposition method (plasma enhanced atomic layer depostion) selected by one of the methods, and deposited to a thickness in the range of 10 ~ 500Å.

When the capacitor is manufactured according to the above-described embodiment, the capacitor forming insulating film 36 and the interlayer insulating film 32 are selectively removed at the same time to form the capacitor hole 37 to expose the active region 32a on the substrate. There is no need to form a conventional storage node contact plug, and only one interlayer insulating film (see 34 in FIG. 3b) is used to form the first and second interlayer insulating films (see 14 and 16 in FIG. 1D). The process is simplified.

When the capacitor is manufactured according to the present invention, the titanium nitride film used as the barrier metal and the titanium silicide film for the ohmic contact are formed on the lower part of the capacitor hole, and then formed, so that the etching process is excessively performed during the formation of the capacitor hole. Even if the lower barrier metal and the ohmic contact layer is damaged does not occur.

In addition, in the past, it was possible to use only the electrode surface area of the capacitor as much as the height of the capacitor forming insulating film, according to the present invention has the effect that even the interlayer insulating film of the lower structure to the height of the capacitor forming insulating film can be used as the electrode surface area of the capacitor.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the manufacturing of a concave capacitor is described as an example. However, the present invention can be applied to the manufacture of a cylindrical capacitor.

When the three-dimensional capacitor is formed in accordance with the present invention, the process of forming the interlayer dielectric film and the storage node contact plug can be omitted.

In addition, after forming the capacitor hole, the titanium nitride film used as the barrier metal and the titanium silicide film for the ohmic contact are formed at the bottom, so that the lower barrier metal and the ohmic contact layer are formed even if the etching process is excessively performed. Damage does not occur so that a reliable capacitor can be manufactured.

Claims (7)

Forming an interlayer insulating film for insulating between the word line patterns formed on the substrate on which the active region is formed; Forming an insulating film for forming a capacitor on the interlayer insulating film; Forming a capacitor hole by patterning the interlayer insulating film and the capacitor forming insulating film to expose the active region; Forming a lower electrode in the capacitor hole; Forming a dielectric thin film on the lower electrode; Forming an upper electrode on the dielectric thin film Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1 Forming a titanium film on the bottom and sidewalls of the capacitor hole; Forming a titanium nitride film on the titanium film; And And forming a titanium silicide film between the titanium nitride film and the active region through a thermal process. The method of claim 2, The method of manufacturing a capacitor of a semiconductor device, characterized in that the thermal process is rapid heat treatment or furnace heat treatment. The method of claim 3, wherein The rapid heat treatment is a capacitor manufacturing method of a semiconductor device, characterized in that proceeding at a temperature in the range of 600 ~ 900 ℃. The method of claim 2, Wherein the lower electrode is one selected from platinum, tungsten, tungsten nitride, titanium nitride, ruthenium, ruthenium oxide, iridium, and iridium oxide. The method of claim 2, The titanium film is a capacitor manufacturing method of the semiconductor device, characterized in that formed in a thickness of 10 ~ 500 10 range. The method of claim 2, The titanium nitride film is a capacitor manufacturing method of a semiconductor device, characterized in that formed in a thickness of 10 ~ 1000Å range.