KR20030094692A - Method of forming electroless solder bumps - Google Patents
Method of forming electroless solder bumps Download PDFInfo
- Publication number
- KR20030094692A KR20030094692A KR1020020031948A KR20020031948A KR20030094692A KR 20030094692 A KR20030094692 A KR 20030094692A KR 1020020031948 A KR1020020031948 A KR 1020020031948A KR 20020031948 A KR20020031948 A KR 20020031948A KR 20030094692 A KR20030094692 A KR 20030094692A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- pads
- solder
- forming
- chips
- Prior art date
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000007772 electroless plating Methods 0.000 claims abstract description 23
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 238000007747 plating Methods 0.000 claims description 29
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 21
- 239000010931 gold Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 238000005246 galvanizing Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000006467 substitution reaction Methods 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 19
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000005272 metallurgy Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 71
- 238000009713 electroplating Methods 0.000 description 11
- 230000005496 eutectics Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000002407 reforming Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemically Coating (AREA)
Abstract
Description
본 발명은 솔더범프 형성방법에 관한 것으로서, 더욱 상세하게는 무전해 도금에 의해 솔더범프를 형성하는 무전해 솔더범프 형성방법에 관한 것이다.The present invention relates to a solder bump forming method, and more particularly, to an electroless solder bump forming method of forming a solder bump by electroless plating.
일반적으로 인쇄회로기판(printed circuit board)과 같은 외부기판(substrate)에 칩을 연결하는 방법에는 와이어 본딩법(wire bonding method), 자동테이프 본딩법(taped automated bonding method), 플립칩법(flip chip method) 등이 있다. 이 들 중 상기 플립칩 법은 전기접속의 경로(electron pathway)가 짧아 속도와 파워를 향상시킬 수 있고 단위 면적당 패드의 수를 증가시킬 수 있다는 장점이 있기 때문에, 우수한 전기적 특성을 필요로 하는 슈퍼컴퓨터에서 휴대용 전자 제품들까지 넓은 응용분야에 이용되고 있다.In general, a method of connecting a chip to an external substrate such as a printed circuit board includes a wire bonding method, a taped automated bonding method, and a flip chip method. ). Among these, the flip chip method has the advantage of shortening the electric pathway and improving the speed and power, and increasing the number of pads per unit area. Are used in a wide range of applications, from to portable electronics.
한편, 상기 플립칩법은 칩과 외부기판의 양호한 본딩을 위하여 웨이퍼(wafer)에 솔더범프를 형성할 것을 요구하는데, 이러한 솔더범프의 제작 기술은 양호한 전도성과 균일한 높이를 가지며 미세 피치(fine pitch)를 갖는 솔더범프를 형성하는 방향으로 발달해 왔다. 이와 같은 플립칩의 범핑 기술은 범핑되는 물질에 따라 솔더범프의 특성 및 그 응용범위가 결정되는 특징이 있는데, 대표적인 범핑 기술로는 전기 도금으로 범프를 형성하는 전기도금법(electroplating)과, 무전해 도금으로 범프를 형성하는 무전해도금법(electroless plating)이 있다.On the other hand, the flip chip method requires forming solder bumps on a wafer for good bonding between the chip and the external substrate. The manufacturing technique of such solder bumps has good conductivity and uniform height and fine pitch. It has been developed in the direction of forming a solder bump having a. Such flip chip bumping technology is characterized in that the characteristics of solder bumps and its application range are determined according to the material to be bumped. Representative bumping technologies include electroplating and electroless plating in which bumps are formed by electroplating. There is an electroless plating method for forming bumps.
도 1a 내지 도 1g에는 종래 전기 도금에 의한 솔더범프 형성방법의 일례를 나타낸 횡단면도가 도시되어 있다.1A to 1G are cross-sectional views showing an example of a conventional solder bump forming method by electroplating.
도 1a에 도시된 바와 같이, 제공된 웨이퍼(11)의 상부에는 복수의 칩들(미도시)과, 이 복수의 칩들 상에 각각 제공된 복수의 패드들(12) 및 복수의 칩들을 보호하고 복수의 패드들(12)을 노출시키는 패시베이션층(passivation layer;13)이 구비되어 있다. 웨이퍼(11)가 제공된 후에는, 도 1b에 도시된 바와 같이, 스퍼터링(sputtering)에 의해 웨이퍼(11) 전체를 도포하여 전기 도금을 위한 도금선(14)을 형성한다. 도금선(14)이 형성된 후에는, 도 1c에 도시된 바와 같이, 솔더범프들이 형성되는 위치를 한정하기 위한 복수의 개구들(15a)이 형성되도록 패턴화된 포토레지스트층(photoresist layer;15)이 도금선(14) 상에 형성된다. 포토레지스트층(15)에 의해 덮이지 않은 도금선(14)의 부분은, 도 1d에 도시된 바와 같이, 전기 도금에 의해 솔더층(16a)이 형성된다. 솔더층(16a)이 형성된 후, 도 1e에 도시된 바와 같이, 포토레지스트층(15)은 제거된다. 포토레지스트층(15)이 제거된 후, 도 1f 에 도시된 바와 같이, 솔더층(16a)을 마스크(mask)로 한 에칭(etching)에 의해 도금선(14)이 제거된다. 마지막으로, 솔더층(16a)의 재 성형(reform)을 통해 솔더범프(16b)를 형성하기 위하여 리플로우(reflow) 하는 공정이 수행된다.As shown in FIG. 1A, a plurality of chips (not shown), a plurality of pads 12 and a plurality of chips provided on the plurality of chips, respectively, are provided on the top of the provided wafer 11, and a plurality of pads are provided. A passivation layer 13 is provided which exposes the field 12. After the wafer 11 is provided, as shown in FIG. 1B, the entire wafer 11 is coated by sputtering to form a plating line 14 for electroplating. After the plating line 14 is formed, as shown in FIG. 1C, a photoresist layer 15 patterned to form a plurality of openings 15a for defining a position at which solder bumps are formed. It is formed on this plating line 14. In the portion of the plating line 14 not covered by the photoresist layer 15, as shown in FIG. 1D, the solder layer 16a is formed by electroplating. After the solder layer 16a is formed, as shown in FIG. 1E, the photoresist layer 15 is removed. After the photoresist layer 15 is removed, as shown in FIG. 1F, the plating line 14 is removed by etching using the solder layer 16a as a mask. Finally, a reflow process is performed to form the solder bumps 16b through the reforming of the solder layer 16a.
상기 전기 도금에 의한 솔더범프 형성방법은 포토마스크 공정을 이용해 필요한 부분에만 솔더범프를 형성하므로 형상 제어가 용이하며, 범프의 신뢰성이 높은 장점이 있다. 따라서, 전기 도금에 의한 솔더범프는 공융본딩(eutectic bonding)에 의해 미세 피치를 갖는 제품에 적용되는 등 그 응용범위가 폭 넓다. 여기서, 공융본딩은 두 성분계의 고체상과 액체상 곡선에서 두 성분이 고용체(固溶體)를 만들지 않고 액체 상태에서 완전히 녹아 섞이는 성질을 이용한 본딩 방법을 의미한다.The method of forming the solder bumps by the electroplating forms the solder bumps only in necessary portions by using a photomask process, so that shape control is easy and the bumps have high reliability. Therefore, the solder bumps by electroplating have a wide application range such as being applied to a product having a fine pitch by eutectic bonding. Here, eutectic bonding means a bonding method using a property in which two components are completely dissolved in a liquid state without making a solid solution in the solid and liquid phase curves of the two component systems.
그러나, 상기 전기 도금에 의한 솔더범프 형성방법은 도금선 형성을 위한 스퍼터링 공정, 포토레지스트 공정 및 도금선의 에칭을 위한 공정 등이 필요하므로 공정이 복잡하여 제조원가 높다는 단점이 있다.However, the method of forming the solder bumps by electroplating has a disadvantage in that it requires a sputtering process for forming a plating line, a photoresist process, a process for etching the plating line, and the like, so that the manufacturing process is complicated and expensive.
한편, 상기 전기 도금에 의한 솔더범프 형성방법과는 대조적으로 무전해 도금에 의한 솔더범프 형성방법은 도금선을 만드는 공정과, 포토레지스트를 형성하는 공정 및 도금선을 에칭하는 공정 등이 없기 때문에 공정이 간단하며 제조원가가 낮다는 장점이 있다.On the other hand, in contrast to the method for forming solder bumps by electroplating, the method for forming solder bumps by electroless plating does not include a process of forming a plating line, a process of forming a photoresist, and a process of etching the plating line. This simple and low manufacturing cost has the advantage.
이와 같은 종래 무전해 솔더범프 형성방법의 일례를 나타낸 횡단면도가 도 2a 내지 도 2d에 도시되어 있다. 여기서, 도 1a 내지 도 1g에 도시된 참조부호와 동일 참조부호는 동일기능을 하는 동일부재을 나타낸다.A cross sectional view showing an example of such a conventional electroless solder bump forming method is shown in FIGS. 2A to 2D. Here, the same reference numerals as those shown in Figs. 1A to 1G denote the same members having the same function.
도 2a에 도시된 바와 같이, 상부에 복수의 칩들(미도시)과, 복수의 패드들(12) 및 패시베이션층(13)이 구비된 웨이퍼(11)가 제공된다. 웨이퍼(11)가 제공된 후, 도 2b에 도시된 바와 같이, 상기 패드들(12)의 노출면을 아연산염(zincate) 처리하여 아연산염처리막(24)을 형성한다. 다음으로, 도 2c에 도시된 바와 같이, 패드들(12)의 아연산염처리막(24)상에 무전해 도금에 의하여 하부범프금속층(under bump metallurgy layer;25)을 형성한다. 마지막으로, 도 2d에 도시된 바와 같이, 치환도금에 의하여 도금층(26)을 형성한다.As shown in FIG. 2A, a wafer 11 having a plurality of chips (not shown), a plurality of pads 12, and a passivation layer 13 is provided thereon. After the wafer 11 is provided, as shown in FIG. 2B, the exposed surfaces of the pads 12 are subjected to zincate treatment to form a zincate treatment film 24. Next, as shown in FIG. 2C, an under bump metallurgy layer 25 is formed on the zincate treated film 24 of the pads 12 by electroless plating. Finally, as shown in FIG. 2D, the plating layer 26 is formed by substitution plating.
그러나, 무전해 도금에 의한 솔더범프의 형성방법은 포토레지스트가 없기 때문에 물질 확산에 의하여 버섯(mushroom) 형태의 범프가 형성되므로 형상 제어가 어렵다는 특징이 있다. 이 때문에 미세 피치를 갖는 솔더범프의 형성이 어렵고, 패드의 크기가 클 때에는 영향이 적지만 패드의 크기가 작아질수록 그 영향이 커져서작은 크기의 패드에는 무전해 도금법을 적용하기 어렵다는 문제점이 있다. 또한, 무전해 도금에 의해 하부범프금속층을 형성하는 데 일반적으로 사용되는 물질인 니켈(Ni)은 전기 도금에 의해 솔더층을 형성하는데 일반적으로 사용되는 물질인 금(Au)에 비하여 그 물성상 경도가 크기 때문에 공융본딩이 어렵다는 특징이 있다. 이 때문에 공융본딩에 통해 미세 피치를 갖는 제품에는 적용하기 어렵고, 그 응용범위가 매우 좁다. 이러한 이유로 무전해 도금법은 스크린 프린팅법(screen printing method)으로 솔더범프를 형성하기 위한 하부범퍼금속층을 형성하는 데에만 주로 이용되어 왔다.However, the method of forming solder bumps by electroless plating has a feature that shape control is difficult because a bump in the form of mushrooms is formed by material diffusion because there is no photoresist. For this reason, it is difficult to form solder bumps having a fine pitch, and when the pads are large in size, they are less affected. However, as the pads are smaller in size, the effects become larger, and therefore, the electroless plating method is difficult to be applied to small pads. In addition, nickel (Ni), which is a material generally used to form the lower bump metal layer by electroless plating, has a higher hardness compared to gold (Au), which is a material generally used to form the solder layer by electroplating. Because of its large size, eutectic bonding is difficult. For this reason, it is difficult to apply to the product which has a fine pitch through eutectic bonding, and its application range is very narrow. For this reason, the electroless plating method has been mainly used only to form the lower bumper metal layer for forming the solder bumps by the screen printing method.
본 발명은 상기 문제점을 해결하기 위한 것으로서, 공정이 간단하고 제조원가가 낮으면서도 패드 크기가 작고 미세 피치를 갖는 솔더범프를 형성할 수 있는 무전해 솔더범프 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming an electroless solder bump capable of forming a solder bump having a small pad size and a fine pitch while having a simple process and a low manufacturing cost.
또한, 외부기판과 용이하게 공융본딩이 가능하여 그 응용범위가 넓은 솔더범프를 형성하는 무전해 솔더범프 형성방법을 제공하는데 또 다른 목적이 있다.In addition, it is another object to provide an electroless solder bump forming method that can be easily eutectic bonding with an external substrate to form a solder bump of a wide application range.
도 1a 내지 도 1g는 종래 전기 도금에 의한 솔더범프 형성방법의 일례를 도시한 횡단면도,1A to 1G are cross-sectional views showing one example of a method for forming solder bumps by conventional electroplating;
도 2a 내지 도 2d는 종래 무전해 솔더범프 형성방법의 일례를 도시한 횡단면도,Figure 2a to 2d is a cross-sectional view showing an example of a conventional electroless solder bump forming method,
도 3a 내지 도 3d는 본 발명의 제1실시예에 따른 무전해 솔더범프 형성방법을 도시한 횡단면도,3A to 3D are cross-sectional views illustrating a method of forming an electroless solder bump according to a first embodiment of the present invention;
도 4a 내지 도 4f는 본 발명의 제2실시예에 따른 무전해 솔더범프 형성방법을 도시한 횡단면도이다.4A to 4F are cross-sectional views illustrating a method for forming an electroless solder bump according to a second embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 간단한 설명><Brief description of symbols for the main parts of the drawings>
111...웨이퍼112...패드111 Wafer 112 Pad
113...패시베이션층114...아연산염처리막113 Passivation layer 114 Zinc treated film
120...하부범프금속층130a...솔더층120 Bottom bump metal layer 130a Solder layer
130b...솔더범프140a,140b...주석도금층130b ... solder bump 140a, 140b ... tin plated layer
150...금도금층150 ... Gold Plated
본 발명의 일 측면에 따른 무전해 솔더범프 형성방법은, 상부에 복수의 칩들과, 상기 복수의 칩들 상에 각각 제공된 복수의 패드들과, 상기 복수의 칩들을 보호하고 상기 복수의 패드들을 노출시키는 패시베이션층이 구비된 웨이퍼를 제공하는 단계와; 상기 복수의 패드들의 노출면을 아연산염 처리하는 단계와; 상기 복수의 패드들 상에 무전해 도금하여 하부범프금속층을 형성하는 단계와; 상기 하부범프금속층 상에 무전해 도금하여 솔더층을 형성하는 단계; 및 상기 솔더층을 리플로우 하는 단계;를 포함한다.Electroless solder bump forming method according to an aspect of the present invention, a plurality of chips on the top, a plurality of pads respectively provided on the plurality of chips, the plurality of chips to protect and expose the plurality of pads Providing a wafer having a passivation layer; Galvanizing the exposed surfaces of the plurality of pads; Electroless plating on the plurality of pads to form a lower bump metal layer; Forming a solder layer by electroless plating on the lower bump metal layer; And reflowing the solder layer.
또한, 본 발명의 또 다른 측면에 의하면, 상부에 복수의 칩들과, 상기 복수의 칩들 상에 각각 제공된 복수의 패드들과, 상기 복수의 칩들을 보호하고 상기 복수의 패드들을 노출시키는 패시베이션층이 구비된 웨이퍼를 제공하는 단계와; 상기 복수의 패드들의 노출면을 아연산염 처리하는 단계와; 상기 복수의 패드들 상에 무전해 도금하여 하부범프금속층을 형성하는 단계와; 상기 하부범프금속층 상에 무전해 도금하여 주석도금층을 형성하는 단계; 및 상기 주석도금층을 리플로우 하는 단계;를 포함하는 것을 특징으로 하는 무전해 솔더범프 형성방법이 제공된다.In addition, according to another aspect of the present invention, a plurality of chips, a plurality of pads respectively provided on the plurality of chips, and a passivation layer for protecting the plurality of chips and the plurality of pads are provided Providing a processed wafer; Galvanizing the exposed surfaces of the plurality of pads; Electroless plating on the plurality of pads to form a lower bump metal layer; Electroless plating on the lower bump metal layer to form a tin plating layer; And reflowing the tin plated layer. A method of forming an electroless solder bump is provided.
이하, 첨부된 도면들을 참조하면서 본 발명의 바람직한 제1실시예를 상세히 설명하도록 한다.Hereinafter, a first preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명의 제1실시예에 따른 무전해 솔더범프 형성방법을 도시한 횡단면도이다.3A to 3D are cross-sectional views illustrating a method of forming an electroless solder bump according to a first embodiment of the present invention.
먼저, 도 3a를 참조하면, 웨이퍼(111)가 제공된다. 제공된 웨이퍼(111)는 플라즈마 세척, 탈지 및 수세로 이루어진 전처리 과정을 거친다. 그리고, 전처 과정을 거친 웨이퍼(111)의 상부에는 복수의 칩들(미도시)과, 이 복수의 칩들 상에 각각 제공된 복수의 패드들(112) 및, 상기 복수의 칩들을 보호하고 상기 복수의 패드들(112)을 노출시키는 패시베이션층(113)이 구비된다.First, referring to FIG. 3A, a wafer 111 is provided. The provided wafer 111 is subjected to a pretreatment process consisting of plasma cleaning, degreasing and washing with water. In addition, a plurality of chips (not shown), a plurality of pads 112 provided on each of the plurality of chips, and a plurality of chips are protected on the upper portion of the wafer 111 which has been preprocessed. A passivation layer 113 is provided that exposes the fields 112.
다음으로, 도 3b에 도시된 바와 같이, 상기 복수의 패드들(112)의 노출면을 아연산염 처리하여 아연산염처리막(114)을 형성한다. 이는 아연핵을 중심으로 상기패드들(112)상에 무전해 도금을 용이하게 실시할 수 있도록 하기 위함이다.Next, as illustrated in FIG. 3B, a zincate treatment film 114 is formed by galvanizing the exposed surfaces of the plurality of pads 112. This is to facilitate the electroless plating on the pads 112 around the zinc core.
그 다음으로, 도 3c에 도시된 바와 같이, 아연산염처리막(114)이 형성된 복수의 패드들(112) 상에 무전해 도금을 하여 하부범프금속층(120)을 형성한다. 여기서, 상기 하부범프금속층(120)은 90 wt% 내지 95 wt%의 니켈(Ni)과 5 wt% 내지 10 wt%의 인(P)으로 형성된다. 이와 같이 형성된 하부범프금속층(120)의 두께는 1 ㎛ 내지 30 ㎛인 것이 바람직하다.3C, the lower bump metal layer 120 is formed by electroless plating on the plurality of pads 112 on which the zincate treatment film 114 is formed. Here, the lower bump metal layer 120 is formed of 90 wt% to 95 wt% nickel (Ni) and 5 wt% to 10 wt% phosphorus (P). The lower bump metal layer 120 formed as described above may have a thickness of 1 μm to 30 μm.
상기 하부범프금속층(120)이 형성된 후, 도 3d에 도시된 바와 같이, 하부범프금속층(120) 상에 무전해 도금을 하여 솔더층(130a)을 형성한다. 여기서, 상기 솔더층(130a)은 주석(Sn)과 납(Pb)으로 형성된다. 이와 같이 형성된 솔더층(130a)의 두께는 5 ㎛ 내지 50 ㎛인 것이 바람직하다.After the lower bump metal layer 120 is formed, as shown in FIG. 3D, the solder layer 130a is formed by electroless plating on the lower bump metal layer 120. Here, the solder layer 130a is formed of tin (Sn) and lead (Pb). The thickness of the solder layer 130a formed as described above is preferably 5 μm to 50 μm.
마지막으로, 솔더층(130a)을 재 성형하여 솔더범프(130b)를 형성하고 솔더층(130a)과 하부범프금속층(120)과의 접합력을 제공하기 위해 리플로우 하는 공정이 수행된다.Finally, a process of reflowing the solder layer 130a to form the solder bumps 130b and providing a bonding force between the solder layer 130a and the lower bump metal layer 120 is performed.
상술한 바와 같은 본 발명의 제1실시예에 따른 무전해 솔더범프 형성방법에 있어서, 상기 하부범프금속층(120)은 솔더층(130a)의 확산을 방지하는 장벽층 및 솔더층(130a)과의 접착에 필요한 접착력을 제공하는 접착층으로서의 역할을 수행할 뿐만 아니라 형성된 솔더범프(130b)의 전기적 특성을 좌우하게 된다. 상기 솔더층(130a)은 하부범프금속층(120)의 산화를 방지하고 외부기판과의 본딩 메커니즘을 부여하는데, 특히 상기 솔더층(130a)은 주석과 납으로 형성되어 있으므로 외부기판과의 용이한 공융본딩을 가능하게 한다. 무전해 도금에 의해 버섯 형태를 갖는 상기 하부범프금속층(120)과 솔더층(130a)은 리플로우 하는 공정을 거치면서 재 성형되어 제어된 형상의 솔더범프(130b)를 형성하므로, 패드 크기가 작고 미세 피치를 갖는 솔더범프(130b)를 형성하는 것이 가능하게 된다.In the electroless solder bump forming method according to the first embodiment of the present invention as described above, the lower bump metal layer 120 and the barrier layer and the solder layer (130a) to prevent the diffusion of the solder layer (130a) Not only serves as an adhesive layer that provides the adhesion necessary for adhesion, but also influences the electrical properties of the formed solder bumps 130b. The solder layer 130a prevents oxidation of the lower bump metal layer 120 and provides a bonding mechanism with the external substrate. Particularly, since the solder layer 130a is formed of tin and lead, it is easily eutectic with the external substrate. Enable bonding. The lower bump metal layer 120 and the solder layer 130a having a mushroom shape by electroless plating are reshaped during a reflow process to form a solder bump 130b having a controlled shape. It is possible to form the solder bumps 130b having a fine pitch.
이하, 본 발명의 바람직한 제2실시예를 첨부된 도면들을 참조하여 상세히 설명하도록 한다.Hereinafter, a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 4a 내지 도 4f는 본 발명의 제2실시예에 따른 무전해 솔더범프 형성방법을 도시한 횡단면도이다. 여기서, 도 3a 내지 도 3e에 도시된 참조부호와 동일참조 부호는 동일기능을 하는 동일부재를 나타내므로 반복적인 설명은 가능한 생략하도록 한다.4A to 4F are cross-sectional views illustrating a method for forming an electroless solder bump according to a second embodiment of the present invention. Here, the same reference numerals and the same reference numerals shown in Figs. 3a to 3e represent the same members having the same function, so that repeated descriptions will be omitted as much as possible.
먼저, 도 4a 내지 도 4c에 도시된 바와 같이, 상부에 칩들과, 패드들(112)과, 패시베이션층(113)을 구비한 웨이퍼(111)가 제공되고, 패드들(112 )상에 아연산염처리막(114)이 형성되며, 패드들(112) 상에 무전해 도금을 하여 하부범프금속층(120)을 형성하는 단계는 상기 제1실시예와 동일하다. 다만, 여기에서도 상기 하부범프금속층(120)은 90 wt% 내지 95 wt%의 니켈(Ni)과 5 wt% 내지 10 wt%의 인(P)으로 형성되며, 이와 같이 형성된 하부범프금속층(120)의 두께는 1 ㎛ 내지 30 ㎛인 것이 바람직하다.First, as shown in FIGS. 4A-4C, a wafer 111 is provided with chips, pads 112, and passivation layer 113 on top, and zincate on pads 112. The process film 114 is formed, and the step of forming the lower bump metal layer 120 by electroless plating on the pads 112 is the same as in the first embodiment. However, the lower bump metal layer 120 is also formed of 90 wt% to 95 wt% nickel (Ni) and 5 wt% to 10 wt% phosphorus (P), and the lower bump metal layer 120 formed as described above. It is preferable that the thickness of 1 micrometer is 30 micrometers.
다음으로, 상기 하부범프금속층(120) 상에 치환 주석 도금을 하여 주석도금층(130a)을 형성한다. 여기서, 상기 주석도금층의 두께는 0.1 ㎛ 내지 2 ㎛ 인 것이 바람직하다.Next, the tin plating layer 130a is formed by performing substitution tin plating on the lower bump metal layer 120. Here, the thickness of the tin plating layer is preferably 0.1 ㎛ to 2 ㎛.
그 다음으로, 상기 주석도금층(140a)을 재 성형하기 위해 리플로우 하는 공정이 수행된다. 여기서, 리플로우 온도는 230 ℃ 내지 270℃인 것이 바람직하다.Next, a process of reflowing to reshape the tin plated layer 140a is performed. Here, it is preferable that reflow temperature is 230 degreeC-270 degreeC.
마지막으로, 리플로우 공정에 의해 재 성형된 주석도금층(140b) 상에 치환 금(Au) 도금을 하여 금도금층(150)을 형성한다. 여기서, 상기 금도금층(150)의 두께는 0.02 ㎛ 내지 0.2 ㎛ 인 것이 바람직하다.Finally, the gold plating layer 150 is formed by performing substitution gold (Au) plating on the tin plating layer 140b reshaped by the reflow process. Here, the thickness of the gold plated layer 150 is preferably 0.02 ㎛ to 0.2 ㎛.
상술한 바와 같은 본 발명의 제2실시예에 따른 무전해 솔더범프 형성방법에 있어서, 하부범프금속층(120)과 금도금층(150) 사이에는 주석도금층(140b)이 개재되는데, 상기 주석도금층(140b)을 형성하는 주석은 녹는점이 대략 232℃로 녹는점이 낮은 물질이다. 따라서, 외부기판과의 본딩을 할 때 주석도금층(140b)과 그 주석도금층(140b)상에 형성된 금도금층(150)의 본딩 온도를 낮추어 외부기판과 용이하게 공융본딩이 가능하도록 한다. 그리고, 주석도금층(140a)과 하부범프금속층(120)과의 접합력을 제공하기 위해 수행되는 리플로우 공정에 의해 하부범프금속층(120)의 형상이 제어된다.In the electroless solder bump forming method according to the second embodiment of the present invention as described above, the tin plating layer 140b is interposed between the lower bump metal layer 120 and the gold plating layer 150, the tin plating layer 140b. The tin forming) is a material with a low melting point of about 232 ° C. Accordingly, when bonding with an external substrate, the bonding temperature of the tin plating layer 140b and the gold plating layer 150 formed on the tin plating layer 140b is lowered to facilitate eutectic bonding with the external substrate. Then, the shape of the lower bump metal layer 120 is controlled by a reflow process performed to provide a bonding force between the tin plating layer 140a and the lower bump metal layer 120.
상술한 바와 같이 본 발명에 따른 무전해 솔더범프 형성방법에 의하면, 제조공정이 간단하고 제조원가가 저렴하면서도 패드의 크기가 작고 미세 피치를 갖는 솔더범프를 형성할 수 있다. 또한, 외부기판과 용이하게 공융본딩이 가능하다.As described above, according to the method for forming an electroless solder bump according to the present invention, a solder bump having a small pitch and a small pitch can be formed while the manufacturing process is simple and the manufacturing cost is low. In addition, eutectic bonding with an external substrate is possible easily.
본 발명은 첨부된 도면에 도시된 실시예를 참고로 하여 설명되었으나, 이는 예시적인 것에 불과하며, 당해 기술 분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위의 기술적 사상에 의해 정해져야 할 것이다.Although the present invention has been described with reference to the embodiments illustrated in the accompanying drawings, it is merely an example, and those skilled in the art may realize various modifications and equivalent other embodiments therefrom. Will understand. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020031948A KR20030094692A (en) | 2002-06-07 | 2002-06-07 | Method of forming electroless solder bumps |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020031948A KR20030094692A (en) | 2002-06-07 | 2002-06-07 | Method of forming electroless solder bumps |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030094692A true KR20030094692A (en) | 2003-12-18 |
Family
ID=32386226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020031948A KR20030094692A (en) | 2002-06-07 | 2002-06-07 | Method of forming electroless solder bumps |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030094692A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100464537B1 (en) * | 2002-06-29 | 2005-01-03 | 주식회사 하이닉스반도체 | Manufacturing of Method of Semiconductor Device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000164623A (en) * | 1998-11-30 | 2000-06-16 | Sharp Corp | Semiconductor device |
| JP2000269259A (en) * | 1999-03-18 | 2000-09-29 | Seiko Epson Corp | Structure of projected electrode on semiconductor device and its formation |
| KR20010019775A (en) * | 1999-08-30 | 2001-03-15 | 윤덕용 | Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating and Their Use |
-
2002
- 2002-06-07 KR KR1020020031948A patent/KR20030094692A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000164623A (en) * | 1998-11-30 | 2000-06-16 | Sharp Corp | Semiconductor device |
| JP2000269259A (en) * | 1999-03-18 | 2000-09-29 | Seiko Epson Corp | Structure of projected electrode on semiconductor device and its formation |
| KR20010019775A (en) * | 1999-08-30 | 2001-03-15 | 윤덕용 | Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating and Their Use |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100464537B1 (en) * | 2002-06-29 | 2005-01-03 | 주식회사 하이닉스반도체 | Manufacturing of Method of Semiconductor Device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4660643B2 (en) | Semiconductor package substrate for forming pre-solder structure, semiconductor package substrate on which pre-solder structure is formed, and manufacturing method thereof | |
| US20100132998A1 (en) | Substrate having metal post and method of manufacturing the same | |
| US8759958B2 (en) | Semiconductor package and method of manufacturing the same | |
| KR100592609B1 (en) | Method for forming bump and method for making semiconductor device | |
| EP2591497B1 (en) | Method to form solder deposits on substrates | |
| US7851345B2 (en) | Semiconductor device and method of forming oxide layer on signal traces for electrical isolation in fine pitch bonding | |
| US20060201997A1 (en) | Fine pad pitch organic circuit board with plating solder and method for fabricating the same | |
| US20080261390A1 (en) | Method for forming bumps on under bump metallurgy | |
| US20060219567A1 (en) | Fabrication method of conductive bump structures of circuit board | |
| KR101034161B1 (en) | Semiconductor package substrate | |
| US20120175265A1 (en) | Circuit board surface structure and fabrication method thereof | |
| US20090102050A1 (en) | Solder ball disposing surface structure of package substrate | |
| US5877560A (en) | Flip chip microwave module and fabrication method | |
| US9559076B2 (en) | Package having substrate with embedded metal trace overlapped by landing pad | |
| TW200408095A (en) | Chip size semiconductor package structure | |
| KR20200035197A (en) | Semiconductor device and method for manufacturing the same | |
| US20040065949A1 (en) | [solder bump] | |
| TWI223883B (en) | Under bump metallurgy structure | |
| KR20030094692A (en) | Method of forming electroless solder bumps | |
| KR100494023B1 (en) | Fabrication and assembly method of image sensor using by flip chip packaging process | |
| KR100705757B1 (en) | Flip Chip Having Ultra-fine Pitch and Fabrication Method thereof | |
| KR19990048003A (en) | Metal bump manufacturing method | |
| JP2009135345A (en) | Semiconductor device and manufacturing method thereof | |
| US20230130436A1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| KR100726059B1 (en) | formation of electroplate solder on an organic circuit board for flip chip joints and board to board solder joints |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application | ||
| J201 | Request for trial against refusal decision | ||
| J301 | Trial decision |
Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20090302 Effective date: 20100630 |