KR20030002022A - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
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- KR20030002022A KR20030002022A KR1020010038755A KR20010038755A KR20030002022A KR 20030002022 A KR20030002022 A KR 20030002022A KR 1020010038755 A KR1020010038755 A KR 1020010038755A KR 20010038755 A KR20010038755 A KR 20010038755A KR 20030002022 A KR20030002022 A KR 20030002022A
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- taon
- capacitor
- oxide film
- tantalum oxide
- depositing
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- 239000003990 capacitor Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 33
- 229910003071 TaON Inorganic materials 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000011065 in-situ storage Methods 0.000 claims abstract description 5
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 45
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 45
- 238000000151 deposition Methods 0.000 claims description 29
- 238000010438 heat treatment Methods 0.000 claims description 28
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 239000012495 reaction gas Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000012298 atmosphere Substances 0.000 claims description 3
- 239000012159 carrier gas Substances 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract description 9
- 239000010410 layer Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 229910008484 TiSi Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000010406 interfacial reaction Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 206010021143 Hypoxia Diseases 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 캐패시터 제조 방법에 관한 것으로, 특히 MIM 구조의 탄탈륨산화막을 이용한 캐패시터의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor using a tantalum oxide film having a MIM structure.
반도체 소자가 고집적화됨에 따라 충분한 정전용량을 확보하기 위해 캐패시터의 구조를 실린더(Cylinder), 핀(Pin), 적층(Stack) 또는 반구형 실리콘(HSG) 등의 복잡한 구조로 형성하여 전하저장 면적을 증가시키거나, SiO2나 Si3N4에 비해 유전상수가 큰 Ta2O5, TiO2, SrTiO3, (Ba,Sr)TiO등의 고유전물질에 대한 연구가 활발히 진행되고 있다.As semiconductor devices are highly integrated, the capacitor structure is formed into a complex structure such as cylinder, pin, stack, or hemispherical silicon (HSG) to secure sufficient capacitance, thereby increasing the charge storage area. In addition, studies on high dielectric materials such as Ta 2 O 5 , TiO 2 , SrTiO 3 , and (Ba, Sr) TiO, which have a higher dielectric constant than SiO 2 or Si 3 N 4 , are being actively conducted.
특히, 저압화학적기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD)을 이용한 탄탈륨산화막(Ta2O5)은 비교적 유전율이 높아 적용 가능성이 높은 것으로 알려졌다.In particular, a tantalum oxide film (Ta 2 O 5 ) using Low Pressure Chemical Vapor Deposition (LPCVD) has a relatively high dielectric constant and is known to have high applicability.
최근에, 소자의 집적화에 의해 소자 크기가 감소함에 따라 유효산화막두께의 감소가 요구되며, 보다 신뢰성있는 소자를 제조하기 위해서는 바이어스전압(Bias voltage)에 따른 ΔC의 감소 및 누설전류와 같은 전기적 특성을 개선시키는 것이 필요하다.Recently, as the device size decreases due to the integration of devices, the effective oxide film thickness is required to be reduced, and in order to manufacture a more reliable device, electrical characteristics such as a decrease in ΔC and a leakage current according to a bias voltage are required. It is necessary to improve.
이러한 특성 개선을 위해서 통상 폴리실리콘대신 금속막을 상하부전극으로 이용하는 MIM(Metal-Insulator-Metal) 캐패시터가 연구되고 있으며, MIM 캐패시터 제조시 캐패시터의 유효산화막두께(Tox), 누설전류 특성이 개선된 신뢰성 있는 소자를 제조하기 위해서는 양질의 캐패시터 유전막을 증착하는 공정이 매우 중요하다할 것이다.MIM using a metal film instead of the conventional polysilicon to these characteristics improve the upper and lower electrodes (Metal-Insulator-Metal) capacitor is researched and which, MIM capacitors effective oxide thickness for the manufacture of a capacitor (T ox), the leakage current a characteristic to improve reliability In order to fabricate such devices, the process of depositing a high quality capacitor dielectric film will be very important.
특히, 탄탈륨산화막을 유전막으로 이용하는 MIM 캐패시터 제조시, 금속전극의 배향성에 따라 탄탈륨산화막이 방향성을 나타내어 유전상수가 증가하며, 금속전극은 폴리실리콘과의 전기적 에너지장벽(Energy barrier)(또는 일함수)이 크므로 유효산화막두께(Tox)를 감소시킬 수 있어 동일한 유효산화막 두께에서의 누설전류를 감소시키는 장점이 있다.In particular, when manufacturing a MIM capacitor using a tantalum oxide film as a dielectric film, the tantalum oxide film has a directionality according to the orientation of the metal electrode, and the dielectric constant increases, and the metal electrode has an electrical energy barrier (or work function) with polysilicon. Since the effective oxide film thickness (T ox ) can be reduced because of this large, there is an advantage of reducing the leakage current at the same effective oxide film thickness.
도 1은 종래기술에 따라 제조된 MIM구조의 탄탈륨산화막 캐패시터를 도시한 도면이다.1 is a view showing a tantalum oxide film capacitor of the MIM structure manufactured according to the prior art.
도 1을 참조하여 캐패시터의 제조 방법을 설명하면, 소스/드레인(12)을 포함한 트랜지스터 제조 공정이 완료된 반도체기판(11)상에 층간절연막(Inter Layer Dielectric; ILD)(13)을 형성한 다음, 층간절연막(13)을 선택적으로 식각하여 소스/드레인(12)의 소정 부분이 노출되는 콘택홀을 형성한다.Referring to FIG. 1, a method of manufacturing a capacitor includes forming an interlayer dielectric (ILD) 13 on a semiconductor substrate 11 on which a transistor manufacturing process including a source / drain 12 is completed. The interlayer insulating layer 13 is selectively etched to form a contact hole through which a predetermined portion of the source / drain 12 is exposed.
계속해서, 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 에치백(Etch back)공정으로 소정 깊이만큼 리세스시켜 콘택홀의 소정 부분에 매립되는 폴리실리콘플러그(14)를 형성한 다음, 폴리실리콘플러그(14)상에 티타늄실리사이드(이하 TiSi2라 약칭함)(15)와 티타늄나이트라이드(이하 'TiN'이라 약칭함)(16)의 적층막을 형성한다.Subsequently, after the polysilicon is formed on the entire surface including the contact hole, the polysilicon plug 14 embedded in the predetermined part of the contact hole is formed by recessing the substrate to a predetermined depth by an etch back process, and then polysilicon. On the plug 14, a laminated film of titanium silicide (hereinafter referred to as TiSi 2 ) 15 and titanium nitride (hereinafter referred to as TiN) 16 is formed.
이 때, TiSi2(15)는 폴리실리콘플러그(14)와 후속 하부전극과의 오믹 콘택(Ohmic contact)을 형성해 주고, TiN(16)는 후속 탄탈륨산화막의 열처리공정시하부전극내에 잔존하는 산소가 폴리실리콘플러그(14) 또는 반도체기판(11)으로 확산하는 것을 방지하는 확산방지막의 역할을 한다.At this time, TiSi 2 (15) forms an ohmic contact between the polysilicon plug (14) and the subsequent lower electrode, and TiN (16) forms oxygen remaining in the lower electrode during the subsequent heat treatment of the tantalum oxide film. It serves as a diffusion barrier that prevents diffusion into the polysilicon plug 14 or the semiconductor substrate 11.
다음으로, TiN(16)를 포함한 층간절연막(13)상에 질화물계 식각정지막(17)과 캐패시터산화막(18)을 형성한 후, 스토리지노드마스크로 캐패시터산화막(18)과 식각정지막(17)을 순차적으로 식각하여 폴리실리콘플러그(14)에 정렬되는 하부전극이 형성될 영역(이하 '오목부'라 약칭함)을 형성한다.Next, after forming the nitride-based etch stop film 17 and the capacitor oxide film 18 on the interlayer insulating film 13 including TiN (16), the capacitor oxide film 18 and the etch stop film 17 as a storage node mask. ) Is sequentially etched to form a region (hereinafter, abbreviated as 'concave portion') in which a lower electrode aligned with the polysilicon plug 14 will be formed.
계속해서, 오픈된 오목부를 포함한 캐패시터산화막(18)의 표면을 따라 하부전극으로서 TiN을 화학기상증착법(CVD)으로 증착한 다음, 에치백 또는 화학적기계적연마를 통해 오목부내에만 TiN을 잔류시켜 이웃한 셀간 서로 격리되는 TiN-하부전극(19)을 형성한다.Subsequently, TiN was deposited by chemical vapor deposition (CVD) as a lower electrode along the surface of the capacitor oxide film 18 including the open recesses, and then TiN was left only in the recesses by etch back or chemical mechanical polishing. The TiN-bottom electrodes 19 are isolated from each other between the cells.
계속해서, TiN-하부전극(19)을 포함한 전면에 탄탈륨산화막(21)을 증착한 후, 산소결핍을 제거하기 위한 열처리와 탄탈륨산화막(21)내 잔류하는 불순물을 제거하기 위한 열처리를 순차적으로 진행한다.Subsequently, after depositing the tantalum oxide film 21 on the entire surface including the TiN-bottom electrode 19, the heat treatment for removing oxygen deficiency and the heat treatment for removing impurities remaining in the tantalum oxide film 21 are sequentially performed. do.
이 때, 산소결핍을 제거하기 위한 열처리는 산소플라즈마 또는 UV/O3열처리와 같은 저온열처리를 이용하고, 불순물 제거를 위한 열처리는 급속열처리 또는 노열처리와 같은 고온열처리를 이용한다.At this time, the heat treatment for removing oxygen deficiency uses a low temperature heat treatment such as oxygen plasma or UV / O 3 heat treatment, and the heat treatment for removing impurities uses high temperature heat treatment such as rapid heat treatment or furnace heat treatment.
다음으로, 탄탈륨산화막(21)상에 상부전극(22)으로서 TiN을 증착한다.Next, TiN is deposited on the tantalum oxide film 21 as the upper electrode 22.
상술한 종래기술에서는 화학기상증착법(CVD)을 이용하여 증착된 TiN을 하부전극으로 이용하고, 유전막으로 유전율(εr)이 높은 탄탈륨산화막(εr=∼25)을 이용하였다.In the above-described prior art, TiN deposited by chemical vapor deposition (CVD) was used as a lower electrode, and a tantalum oxide film having high dielectric constant epsilon r (? R = 25) was used as the dielectric film.
그러나, 탄탈륨산화막의 유전율 확보를 위한 후속 열처리 과정에서, 하부전극과의 계면 반응을 통해 저유전층을 형성시키므로써 전체 정전용량(Capacitance)을 크게 저하시키는 문제점이 있다.However, in the subsequent heat treatment process to secure the dielectric constant of the tantalum oxide film, there is a problem of greatly reducing the overall capacitance by forming a low dielectric layer through an interfacial reaction with the lower electrode.
즉, 탄탈륨산화막의 후속 열처리가 진행될수록 탄탈륨산화막 자체의 유전특성은 향상될 수 있으나, 하부전극과의 계면을 열화시켜 전체 정전용량과 누설전류 특성을 악화시키는 결과를 초래한다.That is, as the subsequent heat treatment of the tantalum oxide film proceeds, the dielectric property of the tantalum oxide film itself may be improved, but the interface with the lower electrode may be degraded, resulting in deterioration of the overall capacitance and leakage current characteristics.
비록 금속 하부전극(TiN)을 이용하여 하부전극과 탄탈륨산화막 사이의 계면반응을 억제시키고 있으나, 탄탈륨산화막의 후속 열처리시 하부전극의 산화를 방지하기는 어렵다.Although the interfacial reaction between the lower electrode and the tantalum oxide film is suppressed using the metal lower electrode TiN, it is difficult to prevent oxidation of the lower electrode during subsequent heat treatment of the tantalum oxide film.
따라서, 금속 하부전극과 탄탈륨산화막과의 계면반응을 억제시키며, 탄탈륨산화막의 유전율을 극대화할 수 있는 최적의 공정조건이 필요하다.Therefore, an optimum process condition is required to suppress the interfacial reaction between the metal lower electrode and the tantalum oxide film and to maximize the dielectric constant of the tantalum oxide film.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 금속 하부전극과 탄탈륨산화막 사이의 계면반응에 따른 정전용량 및 누설전류특성 저하를 방지하는데 적합한 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, the object of the present invention is to provide a method for manufacturing a capacitor suitable for preventing the deterioration of capacitance and leakage current characteristics due to the interfacial reaction between the metal lower electrode and the tantalum oxide film. have.
도 1은 종래기술에 따라 제조된 MIM 구조의 탄탈륨산화막 캐패시터를 도시한 도면,1 is a view showing a tantalum oxide capacitor of the MIM structure manufactured according to the prior art,
도 2a 내지 도 2d는 본 발명의 실시예에 따른 MIM 구조의 탄탈륨산화막 캐패시터의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a tantalum oxide film capacitor having a MIM structure according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 34 : 폴리실리콘플러그31 semiconductor substrate 34 polysilicon plug
35 : TiSi236 : TiN35: TiSi 2 36: TiN
38 : 캐패시터산화막 39 : TiN-하부전극38 capacitor oxide film 39 TiN-bottom electrode
40a : TaON 40b : 탄탈륨산화막40a: TaON 40b: tantalum oxide film
41 : TiN-상부전극41 TiN-top electrode
상기의 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 하부전극을증착하는 단계, 상기 하부전극상에 TaON을 증착하는 단계, 상기 TaON상에 상기 TaON 증착시의 소스물질을 이용하여 인시튜로 탄탈륨산화막을 증착하는 단계, 및 상기 탄탈륨산화막상에 상부전극을 증착하는 단계를 포함하여 이루어짐을 특징으로 한다.According to another aspect of the present invention, there is provided a method of fabricating a capacitor, including depositing a bottom electrode, depositing TaON on the bottom electrode, and in situ using a source material during the TaON deposition on the TaON. Depositing a tantalum oxide film, and depositing an upper electrode on the tantalum oxide film.
바람직하게, 상기 TaON을 증착하는 단계는 상기 소스물질로 Ta(OC2H5)5를 비활성 가스를 운반가스로 이용하여 챔버내로 유입시키는 단계, 및 상기 챔버내에 반응가스로서 암모니아 가스를 유입시키는 단계를 포함하여 이루어짐을 특징으로 한다.Preferably, depositing the TaON includes introducing Ta (OC 2 H 5 ) 5 as the source material into the chamber using an inert gas as a carrier gas, and introducing ammonia gas into the chamber as a reaction gas. Characterized in that comprises a.
바람직하게, 상기 탄탈륨산화막을 증착하는 단계는, 상기 소스물질로 Ta(OC2H5)5소스를 이용하여 반응가스로서 산소가스를 이용하여 이루어짐을 특징으로 한다.Preferably, the step of depositing the tantalum oxide film, characterized in that using the oxygen gas as a reaction gas using a Ta (OC 2 H 5 ) 5 source as the source material.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 MIM 구조의 탄탈륨산화막 캐패시터의 제조 방법을 도시한 공정 단면도로서, 캐패시터의 유전막으로 탄탈륨산화막을 이용하고, 하부전극으로 TiAlN을, 상부전극으로 TiN 또는 루테늄막을 이용한 경우를 도시하고 있다.2A to 2D are cross-sectional views illustrating a method of manufacturing a tantalum oxide film capacitor having a MIM structure according to an embodiment of the present invention, using a tantalum oxide film as a dielectric film of a capacitor, TiAlN as a lower electrode, and TiN or as an upper electrode. The case where a ruthenium film is used is shown.
도 2a에 도시된 바와 같이, 소스/드레인(32)을 포함한 트랜지스터 제조 공정이 완료된 반도체기판(31)상에 층간절연막(ILD)(33)을 형성한 다음, 층간절연막(33)상에 통상의 노광 및 현상을 통해 콘택마스크를 형성한 후, 콘택마스크로 층간절연막(33)을 식각하여 소스/드레인(32)의 소정 부분이 노출되는 콘택홀을 형성하고, 콘택마스크를 제거한다.As shown in FIG. 2A, an interlayer insulating film (ILD) 33 is formed on a semiconductor substrate 31 on which a transistor manufacturing process including a source / drain 32 is completed, and then on a interlayer insulating film 33. After forming the contact mask through exposure and development, the interlayer insulating layer 33 is etched with the contact mask to form a contact hole through which a predetermined portion of the source / drain 32 is exposed, and the contact mask is removed.
계속해서, 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 에치백공정으로 소정 깊이만큼 리세스시켜 콘택홀의 소정 부분에 매립되는 폴리실리콘플러그(34)를 형성한다.Subsequently, after the polysilicon is formed on the entire surface including the contact hole, the polysilicon plug 34 embedded in the predetermined portion of the contact hole is formed by recessing it by a predetermined depth by an etch back process.
그리고, 전면에 티타늄(Ti)을 증착한 후, 급속열처리(RTP)하여 폴리실리콘 플러그(34)의 실리콘(Si) 원자와 티타늄(Ti)의 반응을 유발시켜 폴리실리콘플러그 (34)상에 TiSi2(35)를 형성한다. 이 때, TiSi2(35)는 폴리실리콘플러그(34)와 후속 하부전극과의 접촉저항을 개선시키기 위한 오믹 콘택층이다.After depositing titanium (Ti) on the front surface, rapid thermal treatment (RTP) causes a reaction between silicon (Si) atoms of the polysilicon plug 34 and titanium (Ti) to cause TiSi on the polysilicon plug 34. 2 (35) forms. At this time, TiSi 2 35 is an ohmic contact layer for improving the contact resistance between the polysilicon plug 34 and the subsequent lower electrode.
계속해서, TiSi2(35)상에 TiN(36)를 형성한 후, 층간절연막(33)의 표면이 노출될때까지 TiN(36)를 화학적기계적연마(CMP) 또는 에치백하여 콘택홀내에 매립시킨다.Subsequently, after the TiN 36 is formed on the TiSi 2 35, the TiN 36 is buried in the contact hole by chemical mechanical polishing (CMP) or etching back until the surface of the interlayer insulating film 33 is exposed. .
여기서, TiN(36)는 후속 탄탈륨산화막의 열처리공정시 하부전극내에 잔존하는 산소가 폴리실리콘플러그(34) 또는 반도체기판(31)으로 확산하는 것을 방지하는 확산방지막의 역할을 한다.Here, the TiN 36 serves as a diffusion barrier that prevents oxygen remaining in the lower electrode from diffusing into the polysilicon plug 34 or the semiconductor substrate 31 during the subsequent heat treatment of the tantalum oxide film.
계속해서, TiN(36)를 포함한 층간절연막(33)상에 질화물계 식각정지막(37)과 캐패시터산화막(38)을 형성한 후, 스토리지노드마스크로 캐패시터산화막(38)과 식각정지막(37)을 순차적으로 식각하여 폴리실리콘플러그(34)에 정렬되는 오목부를 오픈시킨다.Subsequently, after the nitride-based etch stop film 37 and the capacitor oxide film 38 are formed on the interlayer insulating film 33 including TiN 36, the capacitor oxide film 38 and the etch stop film 37 are formed using a storage node mask. ) Is sequentially etched to open the recesses aligned with the polysilicon plug 34.
계속해서, 오픈된 오목부를 포함한 캐패시터산화막(38)의 표면을 따라 하부전극으로서 TiN를 증착한 다음, 에치백 또는 화학적기계적연마를 통해 오목부내에만 TiN-하부전극(39)을 잔류시킨다. 즉, 이웃한 셀간 서로 격리되는 TiN-하부전극(39)을 형성한다.Subsequently, TiN is deposited as a lower electrode along the surface of the capacitor oxide film 38 including the open recesses, and then the TiN-bottom electrodes 39 remain only in the recesses through etch back or chemical mechanical polishing. That is, the TiN-bottom electrodes 39 are isolated from each other between neighboring cells.
여기서, TiN-하부전극(39)을 증착하는 방법은 TiCl4소스와 NH3반응가스로 이용한 화학기상증착법을 이용한다.Here, the TiN-bottom electrode 39 is deposited using a chemical vapor deposition method using a TiCl 4 source and an NH 3 reaction gas.
도 2b에 도시된 바와 같이, TiN-하부전극(39)을 포함한 전면에 전면에 캐패시터의 제 1 유전막으로서 TaON(40a)을 증착한다. 이 때, TaON(40a)는 금속유기화학기상증착법(Metal Organic Chemical Vapor Deposition; MOCVD)에 의해 증착된다.As shown in FIG. 2B, TaON 40a is deposited on the front surface including the TiN-bottom electrode 39 as the first dielectric film of the capacitor. At this time, TaON 40a is deposited by metal organic chemical vapor deposition (MOCVD).
TaON(40a)을 증착하는 방법은 Ta2O5의 소스물질로 사용되는 Ta(OC2H5)5를 아르곤 또는 질소와 같은 비활성 기체를 운반가스로 이용하여 챔버내로 유입시킨다.In the TaON (40a) deposition method Ta (OC 2 H 5 ) 5 used as a source material of Ta 2 O 5 is introduced into the chamber using an inert gas such as argon or nitrogen as a carrier gas.
계속해서, 반응가스로 암모니아(NH3)를 챔버내로 유입시켜 Ta(OC2H5)5과 암모니아를 화학반응시키므로써 10Å∼50Å 두께의 TaON(40a)를 증착시킨다. 이 때, TaON(40a)내 N이 10at% 함유되며, TaON(40a)은 200℃∼400℃의 온도에서 증착되고 비정질상을 갖는다.Subsequently, ammonia (NH 3 ) is introduced into the chamber as a reaction gas to chemically react Ta (OC 2 H 5 ) 5 and ammonia to deposit TaON 40a having a thickness of 10 Pa to 50 Pa. At this time, 10at% of N in TaON 40a is contained, and TaON 40a is deposited at a temperature of 200 ° C to 400 ° C and has an amorphous phase.
다음으로, TaON(40a)을 조밀화시키 위한 후처리를 실시하는데, N2+O2분위기에서 저온(200℃∼400℃) 열처리(플라즈마 또는 UV-O3) 또는 N2분위기에서 고온(500℃∼650℃) 급속질화열처리(Rapid Thermal Nitridation; RTN)하여 TaON(40a)내에 잔류하는 불순물을 제거함과 동시에 TaON(40a)을 조밀화시킨다.Next, a post-treatment for densifying the TaON 40a is performed, which is performed at low temperature (200 ° C. to 400 ° C.) heat treatment (plasma or UV-O 3 ) in an N 2 + O 2 atmosphere or at a high temperature (500 ° C. in an N 2 atmosphere. Rapid Thermal Nitridation (RTN) removes impurities remaining in the TaON 40a and densifies the TaON 40a.
위 두 방법 중 어느 하나를 선택하여 실시하거나, 또는 연속적으로 두 방법을 실시할 수 있다.Either of the above two methods can be selected and carried out, or two methods can be carried out continuously.
상기한 바와 같이, TaON(40a)은 증착시에 10at%의 질소(N)가 존재하는데, 이 질소는 후처리 과정에서 TiN-하부전극(39)과의 계면으로 확산하여 계면에 축적되는데, 계면에 축적된 질소는 TiN-하부전극(39)에서 TaON(40a)으로 여기되는 누설전류의 전도를 억제하여 전체 누설전류를 억제하는 역할을 한다.As described above, 10 at% of nitrogen (N) is present in TaON 40a during deposition, and this nitrogen diffuses to the interface with the TiN-bottom electrode 39 during the post-treatment process and accumulates at the interface. Nitrogen accumulated therein suppresses conduction of the leakage current excited from the TiN-lower electrode 39 to the TaON 40a, thereby suppressing the total leakage current.
도 2c에 도시된 바와 같이, TaON(40a)상에 제 2 유전막으로서 탄탈륨산화막(Ta2O5)(40b)을 증착하는데, 이 때 증착법으로는 금속유기화학기상증착법(MOCVD), 원자층증착법(Atomic Layer Deposition; ALD), 물리기상증착법 (Physical Vapor Deposition; PVD) 중에서 선택하여 이용한다.As shown in FIG. 2C, a tantalum oxide film (Ta 2 O 5 ) 40b is deposited on the TaON 40a as a second dielectric layer, wherein the deposition method is metal organic chemical vapor deposition (MOCVD), atomic layer deposition, or the like. (Atomic Layer Deposition; ALD), Physical Vapor Deposition (PVD).
예컨대, 금속유기화학기상증착법(MOCVD)을 이용하는 경우, 제 1 유전막인 TaON(40a)의 증착 및 후처리후 인시튜(In-situ)로 연속진행하며, 소스로는 TaON(40a)의 증착소스인 Ta(OC2H5)5를 이용하고 반응가스로는 산소(O2)를 이용한다.For example, when metal organic chemical vapor deposition (MOCVD) is used, the deposition and post-treatment of the first dielectric film TaON 40a is continuously performed in-situ, and as a source, the deposition source of TaON 40a is used. Phosphorus Ta (OC 2 H 5 ) 5 is used and oxygen (O 2 ) is used as the reaction gas.
이 때, 탄탈륨산화막(40b)은 막내 Ta-O가 2:5의 결합비를 갖도록 하여 유전특성을 개선시키고, TaON(40a)와 탄탈륨산화막(40b)의 비율은 1:1로 하되 전체 유전막은 100Å∼150Å의 두께를 갖는다.At this time, the tantalum oxide film 40b has a bonding ratio of 2: 5 in the film to improve dielectric properties, and the ratio of TaON 40a and tantalum oxide film 40b is 1: 1, but the entire dielectric film is It has a thickness of 100 kPa to 150 kPa.
전술한 것처럼, 캐패시터의 유전막 구조를 동일한 금속유기소스 Ta(OC2H5)5를 이용하여 TaON/탄탈륨산화막(40a/40b)의 이중막으로 형성한다.As described above, the dielectric film structure of the capacitor is formed as a double film of the TaON / tantalum oxide film 40a / 40b using the same metalorganic source Ta (OC 2 H 5 ) 5 .
여기서, TaON(40a)은 유전율이 20∼25이므로 캐패시터의 유전막으로 이용되기도 하며, 하부 TiN-하부전극(39)과 탄탈륨산화막(40b)의 계면반응을 방지하기 위한 방지막으로 이용된다.Here, TaON 40a is used as a dielectric film of a capacitor because the dielectric constant is 20 to 25, and is used as a prevention film for preventing the interfacial reaction between the lower TiN-bottom electrode 39 and the tantalum oxide film 40b.
한편, 탄탈륨산화막(40b)을 증착한 후, 탄탈륨산화막(40b)내 산소 공공을 제거하기 위해 저온에서 플라즈마 열처리 또는 UV-O3열처리를 실시한다.Meanwhile, after the tantalum oxide film 40b is deposited, plasma heat treatment or UV-O 3 heat treatment is performed at low temperature to remove oxygen vacancies in the tantalum oxide film 40b.
이 때, 플라즈마열처리는 산소(O2), N2O 또는 N2+O2의 혼합 가스분위기에서 300℃∼500℃의 온도로 30초∼120초동안 200W∼500W의 파워로 진행된다. 그리고, UV-O3열처리는 300℃∼500℃의 온도로 2분∼10분동안 램프의 강도를 15㎽/cm2∼30㎽/cm2로 유지하면서 진행된다.At this time, the plasma heat treatment proceeds at a power of 200W to 500W for 30 seconds to 120 seconds at a temperature of 300 ° C to 500 ° C in a mixed gas atmosphere of oxygen (O 2 ), N 2 O or N 2 + O 2 . And, UV-O 3 heat treatment is conducted while maintaining the strength of the lamp during 2-10 minutes at a temperature of 300 ℃ ~500 ℃ to 15㎽ / cm 2 ~30㎽ / cm 2 .
이와 같이, 탄탈륨산화막(40b)을 저온(300℃∼500℃)에서 플라즈마열처리하거나 또는 UV-O3열처리하면, 막내 산소결핍을 충분히 제거할 수 있다.As described above, when the tantalum oxide film 40b is subjected to plasma heat treatment or UV-O 3 heat treatment at low temperature (300 ° C to 500 ° C), oxygen deficiency in the film can be sufficiently removed.
다음으로, 탄탈륨산화막(40b)내 산소결핍을 제거한 후, 유전특성을 얻기 위해 질소분위기에서 급속열처리(RTP) 또는 노열처리(Furnace anneal)를 실시한다. 이 때, 급속열처리는 500℃∼650℃의 온도로 30초∼60초 동안 진행되며, 노열처리는 500℃∼650℃의 온도로 10분∼30분동안 진행된다.Next, after the oxygen deficiency in the tantalum oxide film 40b is removed, rapid thermal treatment (RTP) or furnace anneal is performed in a nitrogen atmosphere to obtain dielectric characteristics. At this time, the rapid heat treatment is performed for 30 seconds to 60 seconds at a temperature of 500 ° C to 650 ° C, and the furnace heat treatment is performed for 10 minutes to 30 minutes at a temperature of 500 ° C to 650 ° C.
이와 같이, 고온(500℃∼650℃)에서 열처리를 실시하면, 탄탈륨산화막(40b)내에 잔류하는 탄소, 수소 등의 불순물을 제거할 수 있다.In this manner, when the heat treatment is performed at a high temperature (500 ° C to 650 ° C), impurities such as carbon and hydrogen remaining in the tantalum oxide film 40b can be removed.
도 2d에 도시된 바와 같이, TaON/탄탈륨산화막(40a/40b)의 이중 유전막상에 상부전극으로서 TiN(이하 TiN-상부전극)(41)을 증착한다.As shown in FIG. 2D, TiN (hereinafter referred to as TiN-upper electrode) 41 is deposited on the double dielectric film of the TaON / tantalum oxide film 40a / 40b as an upper electrode.
이 때, TiN은 TiCl4와 암모니아(NH3)를 이용한 화학기상증착법(CVD)으로 500℃∼550℃에서 100Å∼300Å의 두께로 증착하거나, 또는 물리기상증착법(PVD)에 의해 700Å∼900Å의 두께로 증착한다.At this time, TiN was deposited by a chemical vapor deposition method (CVD) using TiCl 4 and ammonia (NH 3 ) at a thickness of 100 Pa to 300 Pa at 500 ° C. to 550 ° C., or 700 Pa to 900 Pa by physical vapor deposition (PVD). Deposit to thickness.
전술한 공정을 완료하면 오목(Concave) 구조의 캐패시터가 형성되며, 캐패시터산화막을 딥아웃(dip out)하여 실린더형(Cylinder) 캐패시터를 형성할 수도 있다.When the above-described process is completed, a capacitor having a concave structure is formed, and the capacitor oxide film may be diped out to form a cylindrical capacitor.
본 발명은 탄탈륨산화막을 유전막으로 이용하고, 상하부전극으로 금속을 이용하는 캐패시터에 적용가능하며, 아울러 BST[(BaxSr1-x)TiO3]와 같은 고유전체를 유전막으로 사용하는 모든 DRAM 및 PZT와 같은 강유전체를 유전막으로 사용하는 모든 강유전체 메모리(FeRAM)에 적용가능하다.The present invention is applicable to a capacitor using a tantalum oxide film as a dielectric film and a metal using an upper and lower electrode, and all DRAM and PZT using a high-k dielectric such as BST [(Ba x Sr 1-x ) TiO 3 ] as a dielectric film. It is applicable to all ferroelectric memories (FeRAM) using ferroelectrics as dielectric films.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 TiN 하부전극상에 TaON/Ta2O5의 이중구조로 유전막을 형성하므로써 후속 열처리시 하부전극과 유전막의 계면반응을 억제하여 전체 정전용량의 감소없이 누설전류 특성을 향상시킬 수 있는 효과가 있다.As described above, the present invention forms a dielectric layer having a double structure of TaON / Ta 2 O 5 on the TiN lower electrode, thereby suppressing the interfacial reaction between the lower electrode and the dielectric layer during subsequent heat treatment, thereby improving leakage current characteristics without reducing the total capacitance. It can be effected.
또한, 이중구조의 유전막 형성시, 동일 소스물질을 이용하고 반응가스만 달리하여 증착이 이루어지므로 동일 챔버내에서 인시튜로 증착할 수 있어 공정을 단순화시킬 수 있는 효과가 있다.In addition, since the deposition is performed by using the same source material and only reacting gases when forming a dielectric layer having a dual structure, deposition can be performed in situ in the same chamber, thereby simplifying the process.
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| US7314806B2 (en) | 2004-04-12 | 2008-01-01 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with separate seed |
| KR100791334B1 (en) * | 2006-07-26 | 2008-01-07 | 삼성전자주식회사 | Method of forming a metal oxide by atomic layer deposition |
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| JP2000058789A (en) * | 1998-08-13 | 2000-02-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JP3768357B2 (en) * | 1998-12-01 | 2006-04-19 | 富士通株式会社 | Manufacturing method of high dielectric capacitor |
| JP2000208720A (en) * | 1999-01-13 | 2000-07-28 | Lucent Technol Inc | Electronic device, mom capacitor, mos transistor, and diffusion barrier layer |
| JP2000216360A (en) * | 1999-01-26 | 2000-08-04 | Hitachi Ltd | Semiconductor memory element |
| KR100403611B1 (en) * | 2000-06-07 | 2003-11-01 | 삼성전자주식회사 | Metal-insulator-metal capacitor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7314806B2 (en) | 2004-04-12 | 2008-01-01 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with separate seed |
| KR100791334B1 (en) * | 2006-07-26 | 2008-01-07 | 삼성전자주식회사 | Method of forming a metal oxide by atomic layer deposition |
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