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US20040063275A1 - Capacitor of a semiconductor memory device and method of forming the seme - Google Patents

Capacitor of a semiconductor memory device and method of forming the seme Download PDF

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US20040063275A1
US20040063275A1 US10/674,377 US67437703A US2004063275A1 US 20040063275 A1 US20040063275 A1 US 20040063275A1 US 67437703 A US67437703 A US 67437703A US 2004063275 A1 US2004063275 A1 US 2004063275A1
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layer
capacitor
forming
dielectric layer
tin
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Kyong-Min Kim
Han-Sang Song
Ki-Seon Park
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Definitions

  • the present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of the semiconductor memory device.
  • a Dynamic Random Access Memory (DRAM) cell is a semiconductor memory device typically having one transistor and one capacitor, in which one bit of data is stored in a cell using an electric charge.
  • DRAM Dynamic Random Access Memory
  • a capacitor has a lower electrode, a dielectric layer, and an upper electrode.
  • One electrode of the lower electrode and the upper electrode is connected to the source/drain junction of the transistor, and the other electrode is connected to a reference voltage line.
  • the dielectric layer of a conventional capacitor is formed with a SiO 2 layer, a nitride-oxide (NO) layer or an oxide-nitride-oxide (ONO) layer.
  • the NO layer and the ONO layer are formed with a Si 3 N 4 layer of which the dielectric constant is two times as high as that of the SiO 2 layer.
  • dielectric layers such as (Ba, Sr) TiO 3 (hereinafter referred as BST) layer, (Pb, Zr) TiO 3 (hereinafter referred as PZT) layer and Ta 2 O 5 layer, having high dielectric constant are used as a dielectric layer of the capacitor.
  • the dielectric constant of the Ta 2 O 5 is about 20 to 25, which is three times as high as that of the Si 3 N 4 , and it is relatively easier to etch the Ta 2 O 5 layer than to etch the BST layer and PZT layer. Furthermore, the Ta 2 O 5 layer formed by the chemical vapor deposition (CVD) method has a good characteristic of step coverage. However, it is difficult to compose the Ta 2 O 5 layer with the proper stoichiometry. Therefore, recently, a TaON layer has been suggested to overcome the stoichiometry problem of the Ta 2 O 5 layer.
  • the characteristic of the Ta 2 O 5 layer depends on the electrodes of the capacitor.
  • a capacitor having a Ta 2 O 5 layer as a dielectric layer has a MIS structure.
  • M is a metal layer for forming the plate line
  • I is an insulating layer i.e., the dielectric layer of the capacitor
  • S is a polysilicon layer for forming a storage electrode.
  • the plate line of the capacitor having the Ta 2 O 5 layer may also be formed with stacked layers of polysilicon layer/TiN layer or polysilicon layer/WN layer, and the storage electrode may also be formed with a polysilicon layer of which surface is treated with nitrogen by the rapid thermal nitration (RTN) process.
  • RTN rapid thermal nitration
  • the thickness of Ta 2 O 5 can be reduced to secure proper capacitance needed in the highly integrated circuit device.
  • the thermal treatment performed after the formation of the capacitor is important in reducing the thickness of the Ta 2 O 5 layer. That is, if the thermal burdens of subsequent processes are relative low, then it is possible to make the Ta 2 O 5 layer relatively thinner.
  • the minimum thickness of the Ta 2 O 5 layer has not clearly been proved, but the limit is presumed to be about 20-30 ⁇ . If the thickness of the Ta 2 O 5 layer is decreased more than the limit, the problem of increasing leakage current occurs.
  • the lower electrode may be formed with a metal layer instead of a polysilicon layer.
  • the native oxide which becomes a disturbance to reduce the thickness of dielectric layer, is not formed on the surface of the lower electrode. Accordingly, it is possible to reduce the thickness of Ta 2 O 5 layer by forming the lower electrode with metal instead of polysilicon.
  • a barrier layer should be formed under the lower electrode to prevent the reaction between the metal layer and a polysilicon plug (or a silicon substrate) and to prevent the diffusion of the oxygen used as a source for forming a dielectric layer.
  • the dielectric characteristic of the tantalum-contained-oxide layer depends on the material of the upper electrode.
  • a Titanium-Nitride (TiN) layer is relatively stable among the conductive materials, and the TiN layer has good step coverage because the TiN layer can be formed by the chemical vapor deposition method. Therefore, a TiN layer is widely used to form the upper electrode.
  • a good electric characteristic of the capacitor can be obtained when the TiN layer is formed at a relatively low temperature rather than a relatively high temperature.
  • the tantalum-contained-dielectric layer such as Ta 2 O 5 and TiON, is damaged by Cl radicals generated by the source material TiCl 4 .
  • the structure of the TiN layer formed at a low temperature is not dense, whereby deoxidized Ta elements remain at the interface between the tantalum-contained-oxide layer and the TiN layer, and the leakage current caused by the Ta elements deteriorates the electric characteristic of the capacitor.
  • a method of forming a capacitor of a semiconductor device including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing Ta element on the lower electrode; forming a first TiN layer of an upper electrode on the dielectric layer by using atomic layer deposition; forming an oxidized TiN layer by performing an oxidation process on the dielectric layer; and forming a second TiN layer of the upper electrode on the oxidized TiN layer by using a physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • a capacitor of a semiconductor device including: a lower electrode formed over a semiconductor substrate; a dielectric layer containing a Ta element formed on the lower electrode; and an upper electrode formed on the dielectric layer.
  • the upper electrode has an oxidized layer and a titanium containing layer. The oxidized layer is between the TiN layer and the dielectric layer.
  • the dielectric layer has an absorption region where the dielectric layer has absorbed a precursor such as TiCl 4 during atomic vapor deposition (AVD)
  • FIGS. 1 to 6 are cross sectional views showing a method for forming a capacitor according to the present invention.
  • a preferred embodiment of the present invention relates to a capacitor and method of fabricating a capacitor having a lower electrode, a Ta-contained-dielectric layer, such as Ta 2 O 5 and TaON, and an upper electrode.
  • a lower electrode a Ta-contained-dielectric layer, such as Ta 2 O 5 and TaON
  • an upper electrode is a charge storage electrode and a cell plate.
  • the lower electrode may be formed in various structures, such as a simple stack structure, a cylinder structure, a multi-fin structure and a concave structure.
  • FIG. 6 One embodiment of a capacitor formed by the method of fabricating a capacitor according to one embodiment of the present invention as shown in FIG. 6.
  • the structure of the capacitor includes a semiconductor substrate 100 over which a polysilicon plug 105 is formed.
  • a lower electrode 110 is formed over the polysilicon plug 105 , and a dielectric layer 115 is formed over the lower electrode 110 .
  • An upper electrode is formed over the dielectric layer 105 and includes a TiN layer 130 formed over a TiON layer 125 .
  • An upper electrode of a capacitor may be formed, according to one embodiment of the present invention, as follows.
  • a first TiN layer is formed with the atomic layer deposition (ALD) method.
  • the TiN layer is oxidized with plasma of an O 2 gas to form a TiON layer.
  • a second TiN layer is formed on the TiON layer using a process such as the physical vapor deposition method.
  • the first TiN layer and the TiON layer may be formed in-situ, namely in the same chamber.
  • the upper electrode formed with the above-mentioned method it is possible to reduce leakage current generated by deoxidized Ta elements remaining at the interface between the tantalum-contained-dielectric layer and the TiN layer. Moreover, it is possible to prevent the tantalum-contained-dielectric layer from being deteriorated by Cl radicals because the first TiN layer, which is contacting the tantalum-contained-dielectric, is formed with ALD, and thus the Cl radicals are not contained in the first TiN layer. Therefore, the electric characteristic of tantalum-contained dielectric layer may be improved.
  • a polysilicon plug 105 is formed on a semiconductor substrate 100 having a predetermined lower structure, and a TiN lower electrode 110 connected to the polysilicon plug 105 is formed.
  • the predetermined lower structure includes an isolation layer and a MOSFET transistor including a gate oxide, gate electrode and source/drain.
  • the surface of the polysilicon plug is etched with a HF solution or a buffered oxide etchant (BOE) solution to remove a native oxide.
  • BOE buffered oxide etchant
  • the lower electrode 110 may be formed after forming a Ti layer as a glue layer and a TiN layer as a diffusion barrier on the polysilicon plug 105 .
  • the dielectic layer 115 is formed with a TaON layer, which is formed in the following conditions.
  • a reaction source Ta (OC 2 H 5 ) 5 for forming TaON is vaporized in a vaporizer maintaining a temperature of about 170-190° C., because the state of the Ta(OC 2 H 5 ) 5 source is liquid at the room temperature.
  • An NH 3 reaction gas is flowed at rates of 10-1000 sccm and the pressure of the chamber is maintained at the ranges of 0.1-2 Torr.
  • the dielectric layer 115 is formed on a wafer heated to 300-400° C.
  • the dielectric layer 115 is annealed in an ambient of oxygen.
  • a plasma treatment is performed at a temperature of about 300-500° C. for about 1-5 minutes using a N 2 gas and an O 2 gas, to remove oxygen vacancies and carbon in the dielectric layer 115 .
  • the plasma treatment can be replaced with other treatments such as an ultraviolet-ozone (UV-O 3 ) treatment.
  • UV-O 3 ultraviolet-ozone
  • a rapid thermal oxidation (RTO) process is performed at a temperature of about 500-650° C. for about 30-60 seconds using a N 2 gas and a O 2 gas, for the purpose of stabilizing the interface of the dielectric layer 115 and the lower electrode 110 and increasing the inductive capacity of the dielectric layer 115 by crystallizing the dielectric layer 115 .
  • a first TiN layer 120 is deposited on the dielectric layer 115 using ALD.
  • the ALD is similar to conventional chemical vapor deposition (CVD). However, the ALD differs from CVD, in that precursors of the ALD react on the surface of a substrate and precursors of the CVD react in a vapor state.
  • a first type of precursor is supplied into a reaction chamber and is absorbed at chemically absorbable sites on a substrate, which in this embodiment includes the dielectric layer 115 , and the remnants of the first precursor are purged from the reaction chamber.
  • a second type of precursor is supplied in the reaction chamber and absorbed at sites on the substrate. Therefore, a layer may be deposited with uniform growth rate.
  • an ALD cycle may include the steps of supplying precursor A; purging with N 2 gas or Ar gas; supplying precursor B and purging with N 2 gas or Ar gas, which are performed repeatedly to deposit a layer.
  • the growth rate is determined by a thickness of a layer deposited for one cycle. Accordingly, it is possible to obtain uniform thickness and good step coverage with ALD using the surface reaction.
  • one deposition cycle of the ALD includes, for example, the steps of flowing TiCl 4 gas; purging with N 2 gas or Ar gas; flowing NH 4 gas; and purging with N 2 gas or Ar gas.
  • the reaction chamber is maintained at a temperature of 200-400° C. and a pressure of 10 mTorr-10 Torr.
  • the delivery time of the TiCl 4 gas is controlled at about 0.1-60 seconds, and the NH 4 gas is flowed for about 0.1-60 seconds.
  • the first TiN layer 120 is oxidized in order to form a TiON layer 125 .
  • O 2 gas at about 10-1000 sccm is flowed into a chamber and excited to form plasma.
  • the pressure of the chamber is maintained at 0.1-2 Torr, and the RF power is maintained at about 30-400 watts.
  • the first TiN layer 120 is oxidized for a few seconds to several hundreds of seconds. All or portions of the first TiN layer 120 may be oxidized by controlling the thickness of the first TiN layer or the process time for oxidizing.
  • the process for forming the first TiN layer 120 and the process for oxidizing may be performed in-situ.
  • a second TiN layer 130 is formed on the TiON layer 125 with physical vapor deposition (PVD). If portions of the first TiN layer 120 are oxidized, the second TiN layer 130 may be in contact with the first TiN layer 120 .
  • PVD physical vapor deposition
  • both lower and upper electrodes are formed of TiN, however the lower electrode may be formed of Ru, Pt, Ir, Os, W, Mo, Co, Ni, Au, Ag, RuO 2 or IrO 2 , etc. Also, the lower electrode may be formed with a doped polysilicon layer to form a capacitor having the MIS structure.
  • the present invention it is possible to prevent the tantalum-contained dielectric layer from deteriorating, because the tantalum-contained dielectric layer is in contact with the first TiN deposited by ALD and all or portions of the first TiN layer are oxidized with O 2 plasma to form the TiON layer which is capable of suppressing the leakage current generated by the deoxidized Ta elements.
  • the step coverage problem which occurs by the increase of the capacitor height, may be solved, and the damage of the tantalum-contained dielectric layer owing to Cl radicals may be reduced.

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Formation Of Insulating Films (AREA)

Abstract

A capacitor having a tantalum-contained-dielectric layer is formed by a fabrication method including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing Ta element on the lower electrode; forming a first TiN layer of an upper electrode on the dielectric layer by using atomic layer deposition; forming an oxidized TiN layer by performing an oxidation process on the dielectric layer; and forming a second TiN layer of the upper electrode on the oxidized TiN layer by using a plasma vapor deposition (PVD).

Description

  • This application is a divisional application of application Ser. No. 10/166,632 filed on Jun. 12, 2002, the entire contents of which are hereby incorporated by reference.[0001]
    • FIELD OF THE INVENTION
  • The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of the semiconductor memory device. [0002]
    • DESCRIPTION OF THE PRIOR ART
  • A Dynamic Random Access Memory (DRAM) cell is a semiconductor memory device typically having one transistor and one capacitor, in which one bit of data is stored in a cell using an electric charge. [0003]
  • A capacitor has a lower electrode, a dielectric layer, and an upper electrode. One electrode of the lower electrode and the upper electrode is connected to the source/drain junction of the transistor, and the other electrode is connected to a reference voltage line. [0004]
  • As the integration of the DRAM is increased, the size of the memory cell is decreased. However, it is impossible to reduce the size of the memory cell in proportion to the reduction of the DRAM size, because an adequate amount of the capacitance is needed to prevent soft error and to maintain stable operation. There have been efforts to obtain adequate capacitance by reducing the thickness of the dielectric layer, increasing the effective area and using material having a high dielectric constant. [0005]
  • The dielectric layer of a conventional capacitor is formed with a SiO[0006] 2 layer, a nitride-oxide (NO) layer or an oxide-nitride-oxide (ONO) layer. The NO layer and the ONO layer are formed with a Si3N4 layer of which the dielectric constant is two times as high as that of the SiO2 layer.
  • However, it is impossible to obtain high capacitance from the SiO[0007] 2 layer, Si3N4 layer, NO layer and ONO layer because of the low dielectric constant of the dielectric layers, even when the thicknesses of the dielectric layers are reduced and the areas are increased. Therefore, dielectric layers, such as (Ba, Sr) TiO3 (hereinafter referred as BST) layer, (Pb, Zr) TiO3 (hereinafter referred as PZT) layer and Ta2O5 layer, having high dielectric constant are used as a dielectric layer of the capacitor.
  • The dielectric constant of the Ta[0008] 2O5 is about 20 to 25, which is three times as high as that of the Si3N4, and it is relatively easier to etch the Ta2O5 layer than to etch the BST layer and PZT layer. Furthermore, the Ta2O5 layer formed by the chemical vapor deposition (CVD) method has a good characteristic of step coverage. However, it is difficult to compose the Ta2O5 layer with the proper stoichiometry. Therefore, recently, a TaON layer has been suggested to overcome the stoichiometry problem of the Ta2O5 layer.
  • The characteristic of the Ta[0009] 2O5 layer depends on the electrodes of the capacitor. A capacitor having a Ta2O5 layer as a dielectric layer has a MIS structure. Herein, “M” is a metal layer for forming the plate line; “I” is an insulating layer i.e., the dielectric layer of the capacitor; and “S” is a polysilicon layer for forming a storage electrode. The plate line of the capacitor having the Ta2O5 layer may also be formed with stacked layers of polysilicon layer/TiN layer or polysilicon layer/WN layer, and the storage electrode may also be formed with a polysilicon layer of which surface is treated with nitrogen by the rapid thermal nitration (RTN) process.
  • In a Metal/Insulator/Silicon (MIS) structure, the thickness of Ta[0010] 2O5 can be reduced to secure proper capacitance needed in the highly integrated circuit device. The thermal treatment performed after the formation of the capacitor is important in reducing the thickness of the Ta2O5 layer. That is, if the thermal burdens of subsequent processes are relative low, then it is possible to make the Ta2O5 layer relatively thinner. The minimum thickness of the Ta2O5 layer has not clearly been proved, but the limit is presumed to be about 20-30 Å. If the thickness of the Ta2O5 layer is decreased more than the limit, the problem of increasing leakage current occurs.
  • To reduce the thickness of the dielectric layer, the lower electrode may be formed with a metal layer instead of a polysilicon layer. When forming the lower electrode with a metal, the native oxide, which becomes a disturbance to reduce the thickness of dielectric layer, is not formed on the surface of the lower electrode. Accordingly, it is possible to reduce the thickness of Ta[0011] 2O5 layer by forming the lower electrode with metal instead of polysilicon.
  • However, the characteristic of the leakage current is influenced greatly by the quality of the lower electrode when the lower electrode is made with metal. Accordingly, a barrier layer should be formed under the lower electrode to prevent the reaction between the metal layer and a polysilicon plug (or a silicon substrate) and to prevent the diffusion of the oxygen used as a source for forming a dielectric layer. [0012]
  • In the meantime, the dielectric characteristic of the tantalum-contained-oxide layer, such as Ta[0013] 2O5 and TiON, depends on the material of the upper electrode.
  • A Titanium-Nitride (TiN) layer is relatively stable among the conductive materials, and the TiN layer has good step coverage because the TiN layer can be formed by the chemical vapor deposition method. Therefore, a TiN layer is widely used to form the upper electrode. When forming the upper electrode with TiN, a good electric characteristic of the capacitor can be obtained when the TiN layer is formed at a relatively low temperature rather than a relatively high temperature. However, if the TiN layer is formed at a low temperature, the tantalum-contained-dielectric layer, such as Ta[0014] 2O5 and TiON, is damaged by Cl radicals generated by the source material TiCl4. In addition, the structure of the TiN layer formed at a low temperature is not dense, whereby deoxidized Ta elements remain at the interface between the tantalum-contained-oxide layer and the TiN layer, and the leakage current caused by the Ta elements deteriorates the electric characteristic of the capacitor.
    • SUMMARY OF THE INVENTION
  • It is, therefore, an object of the present invention to provide a method of fabricating a capacitor having a tantalum-contained-dielectric layer. [0015]
  • It is, therefore, another object of the present invention to provide a method of fabricating a capacitor capable of obtaining good electric characteristics and reducing damages from Cl radicals. [0016]
  • According to one embodiment of the present invention, there is provided a method of forming a capacitor of a semiconductor device, including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing Ta element on the lower electrode; forming a first TiN layer of an upper electrode on the dielectric layer by using atomic layer deposition; forming an oxidized TiN layer by performing an oxidation process on the dielectric layer; and forming a second TiN layer of the upper electrode on the oxidized TiN layer by using a physical vapor deposition (PVD). [0017]
  • According to a second embodiment of the present invention, there is provided a capacitor of a semiconductor device including: a lower electrode formed over a semiconductor substrate; a dielectric layer containing a Ta element formed on the lower electrode; and an upper electrode formed on the dielectric layer. The upper electrode has an oxidized layer and a titanium containing layer. The oxidized layer is between the TiN layer and the dielectric layer. Additionally, the dielectric layer has an absorption region where the dielectric layer has absorbed a precursor such as TiCl[0018] 4 during atomic vapor deposition (AVD)
  • These and other objects of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.[0019]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention and wherein: [0020]
  • FIGS. [0021] 1 to 6 are cross sectional views showing a method for forming a capacitor according to the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A preferred embodiment of the present invention relates to a capacitor and method of fabricating a capacitor having a lower electrode, a Ta-contained-dielectric layer, such as Ta[0022] 2O5 and TaON, and an upper electrode. Each of the lower electrode and the upper electrode is a charge storage electrode and a cell plate. The lower electrode may be formed in various structures, such as a simple stack structure, a cylinder structure, a multi-fin structure and a concave structure.
  • One embodiment of a capacitor formed by the method of fabricating a capacitor according to one embodiment of the present invention as shown in FIG. 6. The structure of the capacitor includes a [0023] semiconductor substrate 100 over which a polysilicon plug 105 is formed. A lower electrode 110 is formed over the polysilicon plug 105, and a dielectric layer 115 is formed over the lower electrode 110. An upper electrode is formed over the dielectric layer 105 and includes a TiN layer 130 formed over a TiON layer 125.
  • An upper electrode of a capacitor may be formed, according to one embodiment of the present invention, as follows. A first TiN layer is formed with the atomic layer deposition (ALD) method. The TiN layer is oxidized with plasma of an O[0024] 2 gas to form a TiON layer. A second TiN layer is formed on the TiON layer using a process such as the physical vapor deposition method. Preferably, the first TiN layer and the TiON layer may be formed in-situ, namely in the same chamber.
  • With the upper electrode formed with the above-mentioned method, it is possible to reduce leakage current generated by deoxidized Ta elements remaining at the interface between the tantalum-contained-dielectric layer and the TiN layer. Moreover, it is possible to prevent the tantalum-contained-dielectric layer from being deteriorated by Cl radicals because the first TiN layer, which is contacting the tantalum-contained-dielectric, is formed with ALD, and thus the Cl radicals are not contained in the first TiN layer. Therefore, the electric characteristic of tantalum-contained dielectric layer may be improved. [0025]
  • Hereinafter, a semiconductor memory device fabrication method according to embodiments of the present invention will be described in detail referring to the accompanying Figures. [0026]
  • First, Referring to FIG. 1, a [0027] polysilicon plug 105 is formed on a semiconductor substrate 100 having a predetermined lower structure, and a TiN lower electrode 110 connected to the polysilicon plug 105 is formed. The predetermined lower structure includes an isolation layer and a MOSFET transistor including a gate oxide, gate electrode and source/drain. After forming the polysilcon silicon plug 105, the surface of the polysilicon plug is etched with a HF solution or a buffered oxide etchant (BOE) solution to remove a native oxide. The lower electrode 110 may be formed after forming a Ti layer as a glue layer and a TiN layer as a diffusion barrier on the polysilicon plug 105.
  • Referring to FIG. 2, a [0028] dielectric layer 115 including Ta element, such as a TaON layer and a Ta2O5 layer, is formed on the lower electrode 110. In the preferred embodiment of the present invention, the dielectic layer 115 is formed with a TaON layer, which is formed in the following conditions. A reaction source Ta (OC2H5)5 for forming TaON is vaporized in a vaporizer maintaining a temperature of about 170-190° C., because the state of the Ta(OC2H5)5 source is liquid at the room temperature. An NH3 reaction gas is flowed at rates of 10-1000 sccm and the pressure of the chamber is maintained at the ranges of 0.1-2 Torr. The dielectric layer 115 is formed on a wafer heated to 300-400° C.
  • Subsequently, the [0029] dielectric layer 115 is annealed in an ambient of oxygen. For example, a plasma treatment is performed at a temperature of about 300-500° C. for about 1-5 minutes using a N2 gas and an O2 gas, to remove oxygen vacancies and carbon in the dielectric layer 115. The plasma treatment can be replaced with other treatments such as an ultraviolet-ozone (UV-O3) treatment. After the plasma treatment or the UV-O3, a rapid thermal oxidation (RTO) process is performed at a temperature of about 500-650° C. for about 30-60 seconds using a N2 gas and a O2 gas, for the purpose of stabilizing the interface of the dielectric layer 115 and the lower electrode 110 and increasing the inductive capacity of the dielectric layer 115 by crystallizing the dielectric layer 115.
  • Thereafter, as shown in FIG. 4, a [0030] first TiN layer 120 is deposited on the dielectric layer 115 using ALD. The ALD is similar to conventional chemical vapor deposition (CVD). However, the ALD differs from CVD, in that precursors of the ALD react on the surface of a substrate and precursors of the CVD react in a vapor state. In ALD, a first type of precursor is supplied into a reaction chamber and is absorbed at chemically absorbable sites on a substrate, which in this embodiment includes the dielectric layer 115, and the remnants of the first precursor are purged from the reaction chamber. A second type of precursor is supplied in the reaction chamber and absorbed at sites on the substrate. Therefore, a layer may be deposited with uniform growth rate. For example, an ALD cycle may include the steps of supplying precursor A; purging with N2 gas or Ar gas; supplying precursor B and purging with N2 gas or Ar gas, which are performed repeatedly to deposit a layer. The growth rate is determined by a thickness of a layer deposited for one cycle. Accordingly, it is possible to obtain uniform thickness and good step coverage with ALD using the surface reaction.
  • In one embodiment of the present invention, one deposition cycle of the ALD includes, for example, the steps of flowing TiCl[0031] 4 gas; purging with N2 gas or Ar gas; flowing NH4 gas; and purging with N2 gas or Ar gas. The reaction chamber is maintained at a temperature of 200-400° C. and a pressure of 10 mTorr-10 Torr. The delivery time of the TiCl4 gas is controlled at about 0.1-60 seconds, and the NH4 gas is flowed for about 0.1-60 seconds.
  • Referring to FIG. 5, the [0032] first TiN layer 120 is oxidized in order to form a TiON layer 125. At this time, O2 gas at about 10-1000 sccm is flowed into a chamber and excited to form plasma. During oxidation, the pressure of the chamber is maintained at 0.1-2 Torr, and the RF power is maintained at about 30-400 watts. The first TiN layer 120 is oxidized for a few seconds to several hundreds of seconds. All or portions of the first TiN layer 120 may be oxidized by controlling the thickness of the first TiN layer or the process time for oxidizing. The process for forming the first TiN layer 120 and the process for oxidizing may be performed in-situ.
  • Referring to FIG. 6, a [0033] second TiN layer 130 is formed on the TiON layer 125 with physical vapor deposition (PVD). If portions of the first TiN layer 120 are oxidized, the second TiN layer 130 may be in contact with the first TiN layer 120.
  • In the meantime, in the above-mentioned embodiment showing the formation method of the capacitor having a MIN structure, both lower and upper electrodes are formed of TiN, however the lower electrode may be formed of Ru, Pt, Ir, Os, W, Mo, Co, Ni, Au, Ag, RuO[0034] 2 or IrO2, etc. Also, the lower electrode may be formed with a doped polysilicon layer to form a capacitor having the MIS structure.
  • With the present invention mentioned above, it is possible to prevent the tantalum-contained dielectric layer from deteriorating, because the tantalum-contained dielectric layer is in contact with the first TiN deposited by ALD and all or portions of the first TiN layer are oxidized with O[0035] 2 plasma to form the TiON layer which is capable of suppressing the leakage current generated by the deoxidized Ta elements.
  • Moreover, by forming the first TiN layer with ALD, the step coverage problem, which occurs by the increase of the capacitor height, may be solved, and the damage of the tantalum-contained dielectric layer owing to Cl radicals may be reduced. [0036]
  • The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims. [0037]

Claims (4)

What is claimed is:
1. A capacitor of a semiconductor device, comprising:
a lower electrode formed over a semiconductor substrate;
a dielectric layer containing a Ta element formed on the lower electrode; and
an upper electrode formed on the dielectric layer, the upper electrode having an oxidized layer and a titanium containing layer,
wherein the oxidized layer is between the TiN layer and the dielectric layer.
2. The capacitor of claim 1, wherein the lower electrode is formed of Ru, Pt, Ir, Os, W, Mo, Co, Ni, Au, Ag, RuO2 or IrO2.
3. The capacitor of claim 1, wherein the dielectric layer is formed of TaON or Ta2O5.
4. The capacitor of claim 1, wherein the oxidized layer is TiON.
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US6673668B2 (en) 2004-01-06

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