KR20020071349A - Semiconductor device having contact plug capable of preventing lifting-off of metal layer provided thereon and method for manufacturing the same - Google Patents
Semiconductor device having contact plug capable of preventing lifting-off of metal layer provided thereon and method for manufacturing the same Download PDFInfo
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- KR20020071349A KR20020071349A KR1020010011474A KR20010011474A KR20020071349A KR 20020071349 A KR20020071349 A KR 20020071349A KR 1020010011474 A KR1020010011474 A KR 1020010011474A KR 20010011474 A KR20010011474 A KR 20010011474A KR 20020071349 A KR20020071349 A KR 20020071349A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
Description
본 발명은 콘택 플러그 상에 제공되는 반도체 소자의 배선층 형성 기술에 관한 것으로, 특히 배선층의 박리를 방지할 수 있는 콘택 플러그를 구비한 반도체 소자 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring layer forming technology of a semiconductor device provided on a contact plug, and more particularly, to a semiconductor device having a contact plug capable of preventing peeling of a wiring layer and a method of manufacturing the same.
반도체 소자의 집적도가 증가함에 따라 배선구조도 다층화되고 있다. 다층 배선 구조에서, 하부 배선층은 그 상부에 형성된 절연층 내에 제공된 콘택 플러그를 통해 절연층 상부에 형성된 상부 배선층에 연결된다. 또한, 반도체 장치의 고집적화에 따른 RC 지연을 개선하기 위해, 상부 및 하부 배선층 또는 콘택 플러그를 구성하는 물질로 비저항이 낮은 금속을 채용하고 있다. 종래에 배선층 또는 콘택 플러그로 사용하던 알루미늄은 비저항이 2.66(μΩ㎝)인데 반해 구리는 1.59로 낮으며, 저렴하고 전자-이동(electro-migration)의 수명도 길어 구리가 차세대 배선 재료로 각광받고 있다.As the degree of integration of semiconductor devices increases, wiring structures are also becoming multilayered. In the multilayer wiring structure, the lower wiring layer is connected to the upper wiring layer formed on the insulating layer through a contact plug provided in the insulating layer formed thereon. In addition, in order to improve the RC delay due to the high integration of the semiconductor device, a metal having a low specific resistance is used as a material for forming upper and lower wiring layers or contact plugs. Aluminum, which has been used as a wiring layer or a contact plug in the past, has a specific resistance of 2.66 (μΩ㎝), while copper is low at 1.59, and is inexpensive and has long lifespan for electro-migration. .
그러나, 구리는 사진 식각 공정을 적용하기 어려워, 다마신 공정을 이용하여 구리 배선층 또는 콘택 플러그를 형성하고 있다. 즉, 층간 절연층을 형성한 뒤, 층간 절연층의 소정 부분을 식각하여 콘택 플러그 또는 배선층이 형성될 영역을 결정한다. 다음, 전기 도금 방식을 이용하여 절연층 내에 제공된 개구부를 채우도록 층간 절연층 상면에 구리층을 형성한다. 그리고, 기계 및 화학적 연마를 실시하여, 각각의 콘택 플러그 또는 배선층을 분리시킨다.However, copper is difficult to apply a photolithography process to form a copper wiring layer or a contact plug using a damascene process. That is, after the interlayer insulating layer is formed, a predetermined portion of the interlayer insulating layer is etched to determine a region where the contact plug or the wiring layer is to be formed. Next, a copper layer is formed on the upper surface of the interlayer insulating layer so as to fill the opening provided in the insulating layer using an electroplating method. Then, mechanical and chemical polishing are performed to separate each contact plug or wiring layer.
그런데, 하부 배선층과 상부 배선층을 연결하는 콘택 플러그를 형성하기 위한 비아의 크기가 작아지면, 비아 내부를 구리로 채울때 보이드가 발생할 가능성이 증가하게된다. 비아 내에 생성된 보이드에 의한 상부 배선층의 박리 현상을 도 1a 내지 도 1d를 참고로 설명한다.However, when the size of the via for forming the contact plug connecting the lower wiring layer and the upper wiring layer is small, the possibility of voids is increased when the via is filled with copper. The peeling phenomenon of the upper wiring layer due to the voids generated in the via will be described with reference to FIGS. 1A to 1D.
도 1a에서, 트랜지스터(도시되지 않음) 및/또는 캐패시터(도시되지 않음)가 형성된 반도체 기판(도시되지 않음) 상에 절연층(10)을 형성한다. 절연층(10)내에는 하부 배선층(12)이 형성되어 있다. 하부 배선층(12)은, 알루미늄, 폴리실리콘 또는 구리 등으로 구성될 수 있다.In FIG. 1A, an insulating layer 10 is formed on a semiconductor substrate (not shown) on which transistors (not shown) and / or capacitors (not shown) are formed. The lower wiring layer 12 is formed in the insulating layer 10. The lower wiring layer 12 may be made of aluminum, polysilicon, copper, or the like.
하부 배선층(12)이 제공된 절연층(10) 상부에 확산 방지막(도시되지않음) 및산화물층(도시되지 않음)을 순차적으로 형성한 뒤, 소정 부분을 식각하여 확산 방지막 패턴(14) 및 절연막 패턴(16)과 개구부(비아)를 형성한다.After the diffusion barrier layer (not shown) and the oxide layer (not shown) are sequentially formed on the insulating layer 10 provided with the lower wiring layer 12, a predetermined portion is etched to etch the diffusion barrier layer pattern 14 and the insulation layer pattern. An opening 16 (via) is formed.
비아를 채우면서 절연막 패턴(16) 상부에 구리 또는 텅스텐을 증착한다. 그런데, 비아의 크기는 반도체 집적도의 증가와 함께 감소하게되어, 구리 또는 텅스텐에 의해 채워지는 비아 내부에는 보이드(20)가 생기게된다.Copper or tungsten is deposited on the insulating layer pattern 16 while filling the vias. However, the size of the via decreases with increasing semiconductor density, resulting in voids 20 inside the via filled with copper or tungsten.
그런데, 콘택 플러그(18)를 분리시키기 위해, 절연막 패턴(16) 상부에 위치하는 구리 또는 텅스텐층은 기게 및 화학적 연마에 의해 제거되어 보이드(20)는 노출되게 된다.However, in order to separate the contact plug 18, the copper or tungsten layer disposed on the insulating film pattern 16 is removed by mechanical and chemical polishing, thereby exposing the void 20.
도 1b에서, 보이드(20)가 노출된 절연막 패턴(16) 상부에 식각 저지막(22)과 층간 절연막(24)을 순차적으로 형성한다. 식각 저지막(22)이 형성되지 않고 바로 층간 절연막(24)이 형성될 수도 있다.In FIG. 1B, an etch stop layer 22 and an interlayer insulating layer 24 are sequentially formed on the insulating layer pattern 16 on which the voids 20 are exposed. The etch stop layer 22 may not be formed, and the interlayer insulating layer 24 may be formed immediately.
다음, 도 1c에서, 층간 절연막(24)의 상에 패터닝된 포토레지스트막(26)을 형성하고, 이를 이용하여, 층간 절연막(24)과 식각 저지막(22)을 식각하여 보이드(20)와 콘택 플러그(18)를 노출시키는 개구부(28)를 형성한다.Next, in FIG. 1C, the patterned photoresist film 26 is formed on the interlayer insulating film 24, and the interlayer insulating film 24 and the etch stop layer 22 are etched using the voids 20 and the interlayer insulating film 24. An opening 28 is formed to expose the contact plug 18.
다음, 패터닝된 포토레지스트막(26)을 제거한 뒤, 전기 도금 방법을 사용하여 구리를 개구부(28)에 채워 상부 배선층(30)을 형성한다.Next, after the patterned photoresist film 26 is removed, the upper wiring layer 30 is formed by filling copper in the opening 28 using an electroplating method.
그런데, 전기 도금 방법을 사용하여 구리를 증착할때, 전해질 용액이 보이드(20)를 채우게 된다. 한편, 상부 배선층(30)의 형성 이후에 어닐링 공정을 진행하면 보이드를 채운 전해질 용액이 기화되어 보이드의 부피가 팽창하게 된다. 따라서, 비아를 채운 콘택 플러그와 상부 금속 배선 사이의 접합력이 약해져서 상부 배선층이 박리되기도 하여, 결과적으로 반도체 소자의 신뢰성이 저하되게 된다.However, when depositing copper using an electroplating method, the electrolyte solution fills the voids 20. On the other hand, when the annealing process is performed after the formation of the upper wiring layer 30, the electrolyte solution filled with the voids is vaporized to expand the volume of the voids. Therefore, the bonding force between the contact plug filled with the via and the upper metal wiring is weakened, and the upper wiring layer is peeled off, resulting in a lower reliability of the semiconductor device.
따라서, 본 발명이 이루고자 하는 기술적 과제는 상부 배선층과 하부 배선층을 연결하는 콘택 플러그 내에 생성된 보이드에 의한 상부 배선층의 박리를 방지할 수 있는 반도체 장치 및 그러한 반도체 장치의 제조 방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a semiconductor device capable of preventing peeling of an upper wiring layer by voids generated in a contact plug connecting the upper wiring layer and the lower wiring layer, and a method of manufacturing the semiconductor device.
도 1a 내지 도 1d는 종래 기술에 따라 콘택 플러그 상에 상부 배선층을 형성하는 과정을 보여주는 단면도들이다.1A to 1D are cross-sectional views illustrating a process of forming an upper wiring layer on a contact plug according to the related art.
도 2a 내지 도 2e는 본 발명에 따라 콘택 플러그 상에 상부 배선층을 형성하는 과정을 보여주는 단면도들이다.2A through 2E are cross-sectional views illustrating a process of forming an upper wiring layer on a contact plug according to the present invention.
본 발명의 기술적 과제를 달성하기 위해, 보이드가 생성된 콘택 플러그 상부에 층간 절연층 또는 식각 저지막을 형성하기 이전에 보이드를 캐핑막으로 채워, 이후의 상부 배선층 형성을 위한 전기 도금 공정 시, 전해질 용액이 보이드 내에 채워지지않게한다.In order to achieve the technical object of the present invention, the voids are filled with a capping film before forming the interlayer insulating layer or the etch stop layer on the contact plug is generated, the electrolyte solution during the electroplating process for the subsequent upper wiring layer formation Do not fill this void.
구체적인 예로써 살펴보면, 먼저, 비아를 구비한 층간 절연층을 준비한다. 층간 절연층 내의 비아를 도전성 물질로 채워 콘택 플러그를 형성한다. 콘택 플러그내에는 보이드가 생성되어 있다. 콘택 플러그를 포함하는 층간 절연층 상면에 캐핑막을 형성하여 보이드를 캐핑막으로 채운다. 캐핑막 상면에 제 2 층간 절연층을 형성하고, 제 2 층간 절연층의 소정 부분을 제거하여 콘택 플러그의 상면을 노출시키는 개구부를 형성한다. 개구부 내부를 전기 도금법을 이용하여 구리로 채워 배선층을 형성하여 상부 배선층을 완성한다. 여기서, 콘택 플러그는 구리 또는 텅스텐으로 구성될 수 있다. 캐핑막은 SiN, SiC, SiOC, SiOF, TEOS(TetraEthylOrthoSilicate), HDP(High Plasma Density)산화막. USG(Undoped Silicate Glass), PSG(PhosporeSilicateGlass), HSQ(Hydrogen SilsesQuioxane)계물질, MSQ(MethylSilsesQuioxane)계 물질 또는 BCB(BenzoCycloButene)계 물질로 이루어지거나, Al, Ti, TiN, Ta, TaN, 또는 TaSiN으로 이루어질 수 있다.As a specific example, first, an interlayer insulating layer having vias is prepared. Vias in the interlayer insulating layer are filled with a conductive material to form a contact plug. A void is generated in the contact plug. A capping film is formed on the upper surface of the interlayer insulating layer including the contact plug to fill the void with the capping film. A second interlayer insulating layer is formed on the upper surface of the capping film, and a predetermined portion of the second interlayer insulating layer is removed to form an opening that exposes the upper surface of the contact plug. The inside of the opening is filled with copper using an electroplating method to form a wiring layer to complete the upper wiring layer. Here, the contact plug may be made of copper or tungsten. The capping film is SiN, SiC, SiOC, SiOF, TEE (TetraEthylOrthoSilicate), HDP (High Plasma Density) oxide film. Made of USG (Undoped Silicate Glass), PSG (PhosporeSilicate Glass), HSQ (Hydrogen SilsesQuioxane) material, MSQ (MethylSilsesQuioxane) material or BCB (BenzoCycloButene) material, Al, Ti, TiN, Ta, TaN, or TaSiN Can be done.
한편, 층간 절연층을 형성하기 이전에, 콘택 플러그와 접촉하는 하부 배선층을 더 형성할 수 있으며, 하부 배선층은 알루미늄, 폴리실리콘 또는 구리로 이루어질 수 있다.Meanwhile, before forming the interlayer insulating layer, a lower wiring layer in contact with the contact plug may be further formed, and the lower wiring layer may be made of aluminum, polysilicon, or copper.
보이드가 전해질 용액이 아닌 캐핑막으로 채워지므로, 상부 배선층 형성 이후의 어닐링 공정에 의한 보이드의 부피 팽창은 억제된다. 따라서 상부 배선층과 콘택 플러그 간의 박리 현상은 억제될 수 있다.Since the voids are filled with the capping film rather than the electrolyte solution, the volume expansion of the voids by the annealing process after the upper wiring layer formation is suppressed. Therefore, the peeling phenomenon between the upper wiring layer and the contact plug can be suppressed.
이하 첨부된 도면을 참고로 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a에서, 트랜지스터(도시되지 않음) 및/또는 캐패시터(도시되지 않음)가 형성된 반도체 기판(도시되지 않음) 상에 절연층(50)을 형성한다. 절연층(50)내에는 알루미늄, 폴리실리콘 또는 구리 등으로 구성되는 하부 배선층(52)이 형성되어 있다. 하부 배선층(52)이 제공된 절연층(50) 상부에 식각 저지막 패턴(54) 및 절연막 패턴(56)과 개구부(비아)를 형성하는 과정은 도 1a에서 설명한 내용이 적용된다.In FIG. 2A, an insulating layer 50 is formed on a semiconductor substrate (not shown) on which transistors (not shown) and / or capacitors (not shown) are formed. In the insulating layer 50, a lower wiring layer 52 made of aluminum, polysilicon, copper, or the like is formed. The process of forming the etch stop layer pattern 54, the insulation layer pattern 56, and the openings (vias) on the insulating layer 50 provided with the lower wiring layer 52 is applied to the description of FIG. 1A.
비아를 채우면서 절연막 패턴(56) 상부에 구리를 증착하여 콘택 플러그(58)를 형성한다. 한편, 구리 이외에 텅텐을 사용할 수도 있다. 이때 콘택 플러그(58) 내부에는 보이드(60)가 형성될 수 있다. 이후, 콘택 플러그(58)를 분리시키기 위해, 절연막 패턴(56) 상부에 위치하는 구리 또는 텅스텐층은 기게 및 화학적 연마에 의해 제거되고 이에 의해 보이드(60)는 노출되게 된다.While filling the vias, copper is deposited on the insulating layer pattern 56 to form a contact plug 58. In addition, tungsten can also be used other than copper. In this case, a void 60 may be formed in the contact plug 58. Then, in order to separate the contact plug 58, the copper or tungsten layer located on the insulating film pattern 56 is removed by mechanical and chemical polishing, whereby the void 60 is exposed.
이러한 상태에서, 보이드(60)를 채우도록 절연막 패턴(56)의 상부에 캐핑막(62)을 형성한다. 캐핑막(62)은, SiN, SiC, SiOC, SiOF, TEOS(TetraEthylOrthoSilicate), HDP(High Plasma Density)산화막. USG(Undoped Silicate Glass), PSG(PhosporeSilicateGlass), HSQ(Hydrogen SilsesQuioxane)계 물질, MSQ(MethylSilsesQuioxane)계 물질 또는 BCB(BenzoCycloButene)계 물질 또는 Al, Ti, TiN, Ta, TaN, 또는 TaSiN으로 이루어질 수 있다. 보이드는 반드시 전부 채워지는 것이 아니고 일부만 채워져도 본 발명의 사상을 달성할 수 있다.In this state, the capping film 62 is formed on the insulating film pattern 56 so as to fill the void 60. The capping film 62 is SiN, SiC, SiOC, SiOF, TEOS (TetraEthylOrthoSilicate), HDP (High Plasma Density) oxide film. USG (Undoped Silicate Glass), PSG (PhosporeSilicateGlass), HSQ (Hydrogen SilsesQuioxane) material, MSQ (MethylSilsesQuioxane) material or BCB (BenzoCycloButene) material or Al, Ti, TiN, Ta, TaN, or TaSiN . The voids are not necessarily all filled, but only partially filled to achieve the spirit of the present invention.
도 2b에서, 캐핑막(62)은 절연막 패턴(56)의 상면이 노출될때까지 기계 및 화학적연마를 받아 또는 에치백등을 이용하여, 일부가 제거되고 오직 보이드를 채우는 부분(62a)이 남게 된다.In FIG. 2B, the capping film 62 is subjected to mechanical and chemical polishing until the top surface of the insulating film pattern 56 is exposed, or by using etch back, and the like, and a part of the capping film 62 is removed, leaving only the portion 62a filling the void. .
도 2c에서, 보이드(60)를 캐핑막을 구성하는 물질로 채운뒤, 결과물 상부에 식각 저지막(64)과 층간 절연막(66)을 순차적으로 형성한다. 식각 저지막(64)이 형성되지 않고 바로 층간 절연막(66)이 형성될 수도 있다.In FIG. 2C, after the voids 60 are filled with the material constituting the capping layer, the etch stop layer 64 and the interlayer insulating layer 66 are sequentially formed on the resultant. The interlayer insulating layer 66 may be formed without forming the etch stop layer 64.
다음, 도 2d에서, 층간 절연막(66)의 상에 패터닝된 포토레지스트막(68)을 형성하고, 이를 이용하여, 층간 절연막(66)과 식각 저지막(64)을 식각하여 보이드를 채운 캐핑막(62a)과 콘택 플러그(58)를 노출시키는 개구부(70)를 형성한다.Next, in FIG. 2D, a patterned photoresist film 68 is formed on the interlayer insulating film 66, and the capping film in which the interlayer insulating film 66 and the etch stop layer 64 are etched to fill the voids is formed. An opening 70 which exposes the 62a and the contact plug 58 is formed.
다음, 페터닝된 포토레지스트막(68)을 제거한 뒤, 전기 도금 방법을 사용하여 구리를 개구부(70)에 채워 상부 배선층(72)을 형성한다. 구체적으로, 상부 배선층(72)을 형성하기 위해서는, 먼저 개구부(70)를 포함하여 층간 절연막 패턴(66a) 상부에 구리층(도시되지 않음)을 형성한다. 다음, 그 구리층을 층간 절연막패턴(66a)의 상면이 노출될때까지 기계 및 화학적으로 연마하여, 상부 배선층(72)을 형성한다.Next, after the patterned photoresist film 68 is removed, the upper wiring layer 72 is formed by filling copper in the opening 70 using an electroplating method. Specifically, in order to form the upper wiring layer 72, a copper layer (not shown) is first formed on the interlayer insulating layer pattern 66a including the opening 70. Next, the copper layer is mechanically and chemically polished until the upper surface of the interlayer insulating film pattern 66a is exposed to form the upper wiring layer 72.
본 발명에서는 크기가 작은 콘택 플러그 내에 보이드가 존재하더라도, 보이드가 캐핑막으로 채워지므로, 콘택 플러그와 접촉하는 상부 배선층을 전기 도금법으로 증착할때에 사용되는 전해질 용액이 보이드에 채워지지 않는다. 따라서, 상부 배선층 형성 이후의 어닐링 공정에 의한 보이드의 부피 팽창은 일어나지 않게 되어, 상부 배선층이 콘택 플러그로부터 박리되는 문제는 발생하지 않게 된다.In the present invention, even if a void is present in the small contact plug, the void is filled with the capping film, so that the electrolyte solution used when the upper wiring layer in contact with the contact plug is deposited by electroplating is not filled in the void. Therefore, the volume expansion of the voids by the annealing process after the formation of the upper wiring layer does not occur, so that the problem that the upper wiring layer is peeled from the contact plug does not occur.
Claims (13)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100790293B1 (en) * | 2002-10-09 | 2007-12-31 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabrication method thereof |
| KR100909176B1 (en) * | 2002-12-27 | 2009-07-22 | 매그나칩 반도체 유한회사 | Metal wiring formation method of semiconductor device |
| KR20090090623A (en) * | 2008-02-21 | 2009-08-26 | 주식회사 하이닉스반도체 | Semiconductor device and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100790293B1 (en) * | 2002-10-09 | 2007-12-31 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabrication method thereof |
| KR100909176B1 (en) * | 2002-12-27 | 2009-07-22 | 매그나칩 반도체 유한회사 | Metal wiring formation method of semiconductor device |
| KR20090090623A (en) * | 2008-02-21 | 2009-08-26 | 주식회사 하이닉스반도체 | Semiconductor device and manufacturing method thereof |
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