[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

KR20020056379A - method for forming insulator film of semiconductor device - Google Patents

method for forming insulator film of semiconductor device Download PDF

Info

Publication number
KR20020056379A
KR20020056379A KR1020000085728A KR20000085728A KR20020056379A KR 20020056379 A KR20020056379 A KR 20020056379A KR 1020000085728 A KR1020000085728 A KR 1020000085728A KR 20000085728 A KR20000085728 A KR 20000085728A KR 20020056379 A KR20020056379 A KR 20020056379A
Authority
KR
South Korea
Prior art keywords
film
forming
semiconductor device
bpsg film
bpsg
Prior art date
Application number
KR1020000085728A
Other languages
Korean (ko)
Inventor
이동호
김연수
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1020000085728A priority Critical patent/KR20020056379A/en
Publication of KR20020056379A publication Critical patent/KR20020056379A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating an insulation layer of a semiconductor device is provided to improve a gap-fill capacity and to prevent a void, by simultaneously performing an etch process and a deposition process while using high density plasma(HDP) equipment. CONSTITUTION: A plurality of metal interconnections(22) having regular intervals are formed on an insulated substrate(21). A diffusion barrier layer(23) is formed on the insulated substrate including the metal interconnection. An etch process and a deposition process are simultaneously performed regarding the entire surface of the insulated substrate including the diffusion barrier layer to deposit a boron phosphorous silicate glass(BPSG) layer(24) by using the HDP equipment. The BPSG layer is flowed at a temperature not higher than 900 deg.C.

Description

반도체 소자의 절연막 형성방법{method for forming insulator film of semiconductor device}Method for forming insulator film of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 소자의 신뢰성을 향상시키는데 적당한 반도체 소자의 절연막 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an insulating film of a semiconductor device suitable for improving the reliability of the device.

집적회로 구조의 형성에 있어서, 기판 상부에 트랜지스터와 같은 능동소자와, 저항과 같은 수동소자 및 소자의 상호 연결하기 위한 금속 배선을 형성하기 위한 층들의 패터닝은 평탄하지 않은 표면을 형성하는 원인이 될 수 있다.In the formation of an integrated circuit structure, patterning of layers for forming active wiring such as transistors, passive components such as resistors, and metal wiring for interconnecting the components on top of the substrate will cause an uneven surface. Can be.

일반적으로 실리콘 산화막과 같은 절연 물질층은 더욱 패턴화된 층을 형성하기 위하여, 비평탄한 표면 상부에 적용된다.In general, an insulating material layer, such as a silicon oxide film, is applied over the non-flat surface to form a more patterned layer.

그러나, 이 실리콘 산화막은 비 평탄하고 또는 단차가 있는 표면의 형성에서, 굴곡을 갖는 결과물 하부에 고르게 증착되는 경향이 있다.However, this silicon oxide film tends to be deposited evenly under the curvilinear result in the formation of an uneven or stepped surface.

이것은 비평탄화된 표면 상부에 일반적인 포토리소그래피 공정을 이용하여, 층을 패턴화하기 매우 어렵게 하는 요인이 된다.This is a factor that makes the layer very difficult to pattern using a common photolithography process on top of the unplanarized surface.

그러므로, 평탄한 층을 제공하기 위하여, 비평탄한 면 상부에 유기물에 기초를 둔 글래스 물질 예를 들어, SOG(Spin On Glass)와 같은 막과, B 또는 P와 같은 도펀트가 포함된 글래스 물질 예를 들어, BPSG(Boron Phosphrous Silicate Glass), PSG(Phosphrous Silicate Glass)등이 이용된다.Therefore, in order to provide a flat layer, a glass material based on an organic material, for example, a film such as spin on glass (SOG), and a glass material including a dopant such as B or P, is provided on top of the non-flat surface. , BPSG (Boron Phosphrous Silicate Glass), PSG (Phosphrous Silicate Glass) and the like are used.

이와 같은 평탄화막 중 3 내지 5wt%의 붕소(B)와 인(P)을 포함하는 BPSG막은 약 400 ~ 450℃의 저온에서 증착되고, 즉시, 800 ~ 850℃의 온도에서 플로우되어, 평탄한 표면이 제공된다.The BPSG film containing 3 to 5 wt% of boron (B) and phosphorus (P) in the planarization film is deposited at a low temperature of about 400 to 450 ° C., and immediately flows at a temperature of 800 to 850 ° C. Is provided.

즉, BPSG막은 증착할 때 붕소(B)나 인(P)을 함유하는 반응물을 첨가하여 증착된 SiO2-B2O3-P2O5혼합 산화막으로서 금속배선 이전의 배선 층간 절연막으로 사용된다.That is, the BPSG film is a SiO 2 -B 2 O 3 -P 2 O 5 mixed oxide film deposited by adding a reactant containing boron (B) or phosphorus (P) during deposition, and is used as an interlayer insulating film before metal wiring. .

한편, BPSG막의 증착법은 사용 반응물에 따라 SiH4계 BPSG 및 TEOS(Tetra Ethyl Otho Silicate)계 BPSG가 있으며 리플로우(Reflow) 공정에서 평탄도의 조정은 BPSG내의 붕소 혹은 인 농도나 리플로우 온도의 조절을 통해 이루어지며 붕소 혹은 인의 농도가 높을수록, 리플로우 온도가 높을수록 평탄도는 우수해진다.Meanwhile, the deposition method of BPSG film includes SiH 4 -based BPSG and TEOS (Tetra Ethyl Otho Silicate) -based BPSG depending on the reactants used. The higher the concentration of boron or phosphorus, the higher the reflow temperature, the better the flatness.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 절연막 형성방법을 설명하면 다음과 같다.Hereinafter, an insulating film forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1은 종래의 반도체 소자의 절연막 형성방법을 나타낸 공정단면도이다.1 is a process cross-sectional view showing a method of forming an insulating film of a conventional semiconductor device.

도 1에 도시된 바와 같이, 절연 기판(11)상에 금속막을 증착한 후 선택적으로 패터닝하여 일정한 간격을 갖는 복수개의 금속배선(12)을 형성하고, 상기 금속배선(12)을 포함한 절연 기판(11)의 전면에 확산 방지막(13)을 형성한다.As shown in FIG. 1, a metal film is deposited on the insulating substrate 11 and then selectively patterned to form a plurality of metal wirings 12 having a predetermined interval, and the insulating substrate including the metal wiring 12 ( A diffusion barrier 13 is formed on the entire surface of 11).

이어, 상기 확산 방지막(13)을 포함한 절연 기판(11)의 전면에 평탄화를 이루기 위하여 APCVD(Atmospheric Pressure Chemical Vapor Deposition)방식에 의하여 BPSG막(14)을 증착한다.Subsequently, the BPSG film 14 is deposited by APCVD (Atmospheric Pressure Chemical Vapor Deposition) in order to planarize the entire surface of the insulating substrate 11 including the diffusion barrier layer 13.

이때, 상기 BPSG막(14)의 평탄화 특성을 향상시키기 위하여 B 및 P의 농도를 높게 유지한다.At this time, in order to improve the planarization characteristics of the BPSG film 14, the concentrations of B and P are kept high.

그리고 상기 BPSG막(14)을 850℃ 이상의 온도 범위로 약 20분간 플로우(flow)를 위한 열처리 공정을 진행하여 표면을 평탄화시킨다.In addition, the BPSG film 14 is subjected to a heat treatment process for about 20 minutes in a temperature range of 850 ° C. or more to planarize the surface.

한편, 상기 BPSG막(14)을 증착한 후 850℃ 이상의 온도에서 플로우를 시키더라도 종횡비가 3.6이상인 경우에는 금속배선(12) 사이에 보이드(void)(15)가 발생한다.On the other hand, even if the flow is performed at a temperature of 850 ° C. or higher after the deposition of the BPSG film 14, when the aspect ratio is 3.6 or more, voids 15 are generated between the metal wires 12.

그러나 상기와 같은 종래의 반도체 소자의 절연막 형성방법은 종횡비(aspect ratio)가 3.6이상을 가지는 토폴로지(topology)를 갭-필(gap-fill) 및 평탄화하는데 있어 보이드(void)가 발생하여 다음과 같은 문제점이 있었다.However, in the method of forming an insulating film of a conventional semiconductor device as described above, voids occur in gap-fill and planarization of a topology having an aspect ratio of 3.6 or more, as follows. There was a problem.

첫째, 종횡비가 큰 곳을 매립하기 위하여 B와 P의 함유량이 많을수록 원자간의 결합 에너지의 결합력이 약해 후속 공정의 콘택 형성시 콘택 부분의 보잉(bowing) 및 크리닝(cleaning) 공정시에도 많은 막실의 손실을 가져와 프로파일(profile)의 불량을 가져온다.First, in order to fill a large aspect ratio, the higher the content of B and P, the weaker the binding energy between atoms, so that the loss of the membrane during the bowing and cleaning of the contact part during contact formation of the subsequent process To get a bad profile.

둘째, 종횡비가 큰 곳을 매립하기 위하여 BPSG막의 플로우 온도를 높게 가져감으로서 높은 열비(thermal budget)로 인하여 소자 특성 확보가 어렵다.Second, it is difficult to secure device characteristics due to a high thermal budget by having a high flow temperature of the BPSG film in order to fill a large aspect ratio.

셋째, BPSG막의 플로우를 위한 고온 열공정시 BPSG막의 B와 P의 상부 배선층으로의 외부 확산(out diffusion)이 일어난다.Third, out diffusion occurs in the upper wiring layer of B and P of the BPSG film during the high temperature thermal process for the flow of the BPSG film.

넷째, 높은 도펀트(dopant)의 BPSG막을 증착한 후 CMP 공정을 진행할 경우 빠른 이동비(removal rate)로 인하여 CMP 공정의 균일성을 제어하기가 어렵다.Fourth, when the CMP process is performed after the deposition of a high dopant BPSG film, it is difficult to control the uniformity of the CMP process due to the rapid removal rate.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 갭-필 능력을 향상시키어 보이드의 발생을 방지함으로서 소자의 특성을 확보하도록 한 반도체 소자의 절연막 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of forming an insulating film of a semiconductor device, which is designed to solve the above-mentioned problems and to secure device characteristics by improving gap-fill capability and preventing voids.

도 1은 종래의 반도체 소자의 절연막 형성방법을 나타낸 공정단면도1 is a process cross-sectional view showing a method of forming an insulating film of a conventional semiconductor device

도 2는 본 발명에 의한 반도체 소자의 절연막 형성방법을 나타낸 공정단면도2 is a process cross-sectional view showing a method for forming an insulating film of a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 절연 기판 22 : 금속배선21: insulated substrate 22: metal wiring

23 : 확산 방지막 24 : BPSG막23: diffusion barrier film 24: BPSG film

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 절연막 형성방법은 절연 기판상에 일정한 간격을 갖는 복수개의 금속배선을 형성하는 단계와, 상기 금속배선을 포함한 절연 기판의 전면에 확산 방지막을 형성하는 단계와, 상기 확산 방지막을 포함한 절연 기판의 전면에 HDP 장비를 이용하여 식각과 증착을 동시에 진행하여 BPSG막을 증착하는 단계와, 상기 BPSG막을 900℃이하의 온도에서 플로우시키는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming an insulating film for a semiconductor device, the method including: forming a plurality of metal wires having a predetermined interval on an insulating substrate, and forming a diffusion barrier on the entire surface of the insulating substrate including the metal wires. And forming a BPSG film by simultaneously etching and depositing an HDP device on the front surface of the insulating substrate including the diffusion barrier layer, and flowing the BPSG film at a temperature of 900 ° C. or less. It is characterized by.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 절연막 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, an insulating film forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 의한 반도체 소자의 절연막 형성방법을 나타낸 공정단면도이다.2 is a process cross-sectional view showing a method for forming an insulating film of a semiconductor device according to the present invention.

도 2에 도시한 바와 같이, 절연 기판(21)상에 금속막을 증착한 후 선택적으로 패터닝하여 일정한 간격을 갖는 복수개의 금속배선(22)을 형성하고, 상기 금속배선(22)을 포함한 절연 기판(21)의 전면에 확산 방지막(23)을 형성한다.As shown in FIG. 2, a metal film is deposited on the insulating substrate 21 and then selectively patterned to form a plurality of metal wirings 22 having a predetermined interval, and the insulating substrate including the metal wiring 22 ( A diffusion barrier 23 is formed on the entire surface of the 21.

이어, 상기 확산 방지막(23)을 포함한 절연 기판(21)의 전면에 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방법으로서 HDP(High Density Plasma) 장비를 이용하여 식각(etch)과 증착(deposition)이 동시에 진행되도록 하여 BPSG막(24)을 증착한다.Subsequently, etching and deposition are simultaneously performed using HDP (High Density Plasma) as a Plasma Enhanced Chemical Vapor Deposition (PECVD) method on the entire surface of the insulating substrate 21 including the diffusion barrier 23. The BPSG film 24 is deposited as necessary.

즉, 상기 BPSG막(24)을 증착할 때 아르곤(Ar) 가스를 사용하여 식각과 증착을 동시에 진행하고, 이후 Ar 가스를 중단한 후 일반적인 CVD(Chemical Vapor Deposition)방법으로 BPSG막(24)을 계속해서 증착한다.That is, when the BPSG film 24 is deposited, etching and deposition are performed simultaneously using argon (Ar) gas, and then the Ar gas is stopped and then the BPSG film 24 is formed by a general chemical vapor deposition (CVD) method. Continuing deposition.

그리고 상기 BPSG막(24)을 800℃ 이하의 온도 범위에서 플로우시키거나 RTP로 900℃이하의 온도에서 30초 미만으로 플로우시킨다.The BPSG film 24 is then flowed in a temperature range of 800 ° C. or less, or in RTP for less than 30 seconds at a temperature of 900 ° C. or less.

한편, 상기 BPSG막(24)의 전면에 CMP(Chemical Mechanical Polishing) 공정을 추가로 진행하여 평탄화시킬 수도 있다.On the other hand, a CMP (Chemical Mechanical Polishing) process may be further performed on the entire surface of the BPSG film 24 to planarize it.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 절연막 형성방법은 다음과 같은 효과가 있다.As described above, the insulating film forming method of the semiconductor device according to the present invention has the following effects.

첫째, HDP 장비를 이용하여 식각과 증착을 동시에 진행하여 BPSG막을 증착함으로서 갭-필 능력을 향상시키어 보이드의 발생을 방지할 수 있다.First, by performing the etching and deposition at the same time using the HDP equipment to deposit the BPSG film can improve the gap-fill ability to prevent the generation of voids.

둘째, BPSG막을 증착한 후 900℃이하의 낮은 플로우 온도로 공정을 진행함으로서 낮은 열비를 통해 소자의 특성을 확보할 수 있다.Second, by depositing a BPSG film and proceeding at a low flow temperature of less than 900 ℃ can secure the characteristics of the device through a low heat ratio.

셋째, 낮은 도펀트의 BPSG막을 증착하여 플로우시킴으로서 소자의 평탄화를 형성하고 후속 고온 열공정시의 B와 P 함유량이 적어 상부 배선층으로의 외부 확산을 방지할 수 있다.Third, by depositing and flowing a low dopant BPSG film, the planarization of the device is formed and the B and P content during the subsequent high temperature thermal process is low, thereby preventing external diffusion into the upper wiring layer.

넷째, 낮은 도펀트의 BPSG막을 증착함으로서 후속 CMP 공정을 진행할 경우 느린 이동비로 인하여 CMP 공정의 균일성을 제어하기가 용이하다.Fourth, in the subsequent CMP process by depositing a low dopant BPSG film, it is easy to control the uniformity of the CMP process due to the slow moving ratio.

Claims (5)

절연 기판상에 일정한 간격을 갖는 복수개의 금속배선을 형성하는 단계;Forming a plurality of metal wires having a predetermined distance on the insulating substrate; 상기 금속배선을 포함한 절연 기판의 전면에 확산 방지막을 형성하는 단계;Forming a diffusion barrier on an entire surface of the insulating substrate including the metal wires; 상기 확산 방지막을 포함한 절연 기판의 전면에 HDP 장비를 이용하여 식각과 증착을 동시에 진행하여 BPSG막을 증착하는 단계;Depositing a BPSG film by simultaneously performing etching and deposition on the front surface of the insulating substrate including the diffusion barrier using HDP equipment; 상기 BPSG막을 900℃이하의 온도에서 플로우시키는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 절연막 형성방법.And forming the BPSG film at a temperature of 900 ° C. or less. 제 1 항에 있어서, 상기 BPSG막은 Ar 분위기에서 식각과 증착을 동시에 진행하고 CVD법에 의해 증착하는 것을 특징으로 하는 반도체 소자의 절연막 형성방법.The method of claim 1, wherein the BPSG film is simultaneously etched and deposited in an Ar atmosphere and deposited by CVD. 제 1 항에 있어서, 상기 BPSG막을 800℃ 이하의 온도 또는 RTP로 900℃이하의 온도에서 플로우시키는 것을 특징으로 하는 반도체 소자의 절연막 형성방법.The method for forming an insulating film of a semiconductor device according to claim 1, wherein the BPSG film is flowed at a temperature of 800 ° C or lower or a RTP at a temperature of 900 ° C or lower. 제 1 항에 있어서, 상기 BPSG막을 플로우시킨 후 CMP 공정을 실시하여 평탄화시키는 단계를 더 포함하여 형성함을 특징으로 하는 반도체 소자의 절연막 형성방법.The method of claim 1, further comprising planarization by flowing the BPSG film and performing a CMP process. 제 3 항에 있어서, 상기 RTP는 30초미만으로 실시하는 것을 특징으로 하는반도체 소자의 절연막 형성방법.4. The method according to claim 3, wherein the RTP is performed in less than 30 seconds.
KR1020000085728A 2000-12-29 2000-12-29 method for forming insulator film of semiconductor device KR20020056379A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000085728A KR20020056379A (en) 2000-12-29 2000-12-29 method for forming insulator film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000085728A KR20020056379A (en) 2000-12-29 2000-12-29 method for forming insulator film of semiconductor device

Publications (1)

Publication Number Publication Date
KR20020056379A true KR20020056379A (en) 2002-07-10

Family

ID=27688876

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000085728A KR20020056379A (en) 2000-12-29 2000-12-29 method for forming insulator film of semiconductor device

Country Status (1)

Country Link
KR (1) KR20020056379A (en)

Similar Documents

Publication Publication Date Title
KR0159177B1 (en) Manufacturing method of semiconductor device with insulation film
JP3712356B2 (en) Film-forming method and semiconductor device manufacturing method
US6348706B1 (en) Method to form etch and/or CMP stop layers
US20020052119A1 (en) In-situ flowing bpsg gap fill process using hdp
JPH04167429A (en) Semiconductor device and its manufacture
US5567661A (en) Formation of planarized insulating film by plasma-enhanced CVD of organic silicon compound
KR100430114B1 (en) Method for forming an interlayer insulating film, and semiconductor device
JPH11204645A (en) Interlayer insulating film of semiconductor device and manufacture thereof
JPH06177120A (en) Deposition of interlayer dielectric film
US20170148676A1 (en) Low-K Dielectric Layer and Porogen
US6136688A (en) High stress oxide to eliminate BPSG/SiN cracking
KR20040070879A (en) Method of forming metal line of semiconductor device
KR20020056379A (en) method for forming insulator film of semiconductor device
KR0149468B1 (en) A method for forming a semiconductor device
KR100228348B1 (en) Semiconductor apparatus and its fabricating method
KR100623595B1 (en) Method for planarize dielectric layer in semiconductor device
KR100367499B1 (en) Method for manufacturing semiconductor device
KR100678007B1 (en) Method for forming pre metal dielectric in a semiconductor
KR20010045429A (en) Method for forming inter-dielectric layer in semiconductor device
KR100459063B1 (en) Method for manufacturing intermetal dielectric layer of semiconductor device
KR20050000871A (en) Gap fill enhancing method using high density plasma
JP2001244264A (en) Formation method for interlayer insulating film of semiconductor element
KR0125782B1 (en) Flatening method for metal line formation
KR100547242B1 (en) A method of forming intermetal dielectric layer for preventing void
KR100588636B1 (en) Method for manufacturing inter-metal dielectric layer of the semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination