KR100459063B1 - Method for manufacturing intermetal dielectric layer of semiconductor device - Google Patents
Method for manufacturing intermetal dielectric layer of semiconductor device Download PDFInfo
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- KR100459063B1 KR100459063B1 KR10-2002-0027874A KR20020027874A KR100459063B1 KR 100459063 B1 KR100459063 B1 KR 100459063B1 KR 20020027874 A KR20020027874 A KR 20020027874A KR 100459063 B1 KR100459063 B1 KR 100459063B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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Abstract
본 발명은 반도체 소자의 금속 배선의 층간 절연막 제조 방법에 관한 것으로, 특히 반도체 기판의 하부 구조물에 하부 층간 절연막을 형성하고 그 위에 금속 배선을 형성하고, 금속 배선이 있는 결과물 전면에 3% 이상의 O3 농도를 포함한 절연체박막을 형성하되, 금속 배선의 측면 및 모서리는 두껍고 금속 배선의 상부 및 하부 층간 절연막 표면에는 얇게 형성한 후에, O3 절연체박막 상부에 HDP CVD에 의한 상부 층간 절연막을 형성한다. 그러므로, 본 발명은 HDP CVD로 층간 절연막을 형성하기 전에, 금속 배선의 보호막으로서 O3를 포함한 절연체박막을 형성함으로써 HDP CVD 층간 절연의 제조 공정시 금속 배선의 모서리에 클리핑(clipping) 현상과 HDP 피트(pit) 및 보이드(void)가 없도록 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an interlayer insulating film of a metal wiring of a semiconductor device. In particular, a lower interlayer insulating film is formed on a lower structure of a semiconductor substrate and a metal wiring is formed thereon, and an O3 concentration of 3% or more on the entire surface of the resultant metal wiring After forming an insulator thin film, the side and the corners of the metal wiring is thick and formed on the upper and lower interlayer insulating film surface of the metal wiring, and then forming an upper interlayer insulating film by HDP CVD on the O3 insulator thin film. Therefore, according to the present invention, before forming the interlayer insulating film by HDP CVD, an insulator thin film containing O3 is formed as a protective film of the metal wiring, so that the phenomenon of clipping and HDP pits (in the edge of the metal wiring during the manufacturing process of the HDP CVD interlayer insulation) There should be no pit and void.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 고밀도 플라즈마 화학기상증착법(High Density Plasma Chemical Vapor Deposition: 이하 HDP CVD라 함)으로 반도체 소자의 금속 배선의 층간 절연막 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an interlayer insulating film of a metal wiring of a semiconductor device by High Density Plasma Chemical Vapor Deposition (HDP CVD).
반도체 제조 기술의 발달에 따른 소자의 고집적화로, 회로상의 금속 배선은점차 미세한 선폭으로 형성되며 그 배선 간의 간격 또한 미세화되는 추세이다. 그리고 소자의 크기를 줄이기 위해 다층 배선을 형성한다. 이러한 다층 배선은 배선 사이를 층간 절연시키기 위하여 층간 절연막을 필요로 한다. 따라서 배선의 전기적 분리를 위한 층간 절연막은 USG(Undoped Silicate Glass), SOG(Silicon-on-Glass)을 이용한 산화막, 플라즈마인핸스드 화학기상증착법(Plasma Enhanced Chemical Vapor Deposition: 이하 PE CVD라함)에 의한 TEOS(Tetraethylorthosilicate), 실리콘질화막(SiH4)을 증착하거나, HDP CVD로 산화막을 증착한 후에 화학적기계적연마(Chemical Mechanical Polishing : 이하 CMP라 함) 공정을 이용하여 평탄화시킨다.Due to the high integration of devices according to the development of semiconductor manufacturing technology, metal wirings on a circuit are gradually formed with a fine line width, and the spacing between the wirings is also miniaturized. And to reduce the size of the device to form a multi-layer wiring. Such multilayer wiring requires an interlayer insulating film in order to insulate between the wirings. Therefore, the interlayer insulating film for the electrical separation of the wiring is USS (Undoped Silicate Glass), SOG (Silicon-on-Glass) oxide film, TEOS by Plasma Enhanced Chemical Vapor Deposition (hereinafter referred to as PE CVD) (Tetraethylorthosilicate), a silicon nitride film (SiH4) is deposited, or an oxide film is deposited by HDP CVD and then planarized using a chemical mechanical polishing (CMP) process.
한편, HDP CVD는 전기장과 자기장을 인가하여 높은 밀도의 플라즈마 이온을 형성, 소스 가스를 분해하여 증착하는 방식의 CVD이다. 특히 HDP CVD는 높은 플라즈마 이온 밀도와 동시에 DC 바이어스(bias)를 증착 진행중에 인가함으로써 증착(Deposition) 및 식각(Etch)이 인시튜(in-situ)로 진행되는 특징을 갖고 있는 바, 보이드(Void) 없이 배선 사이를 층간 절연막을 채울 수 있다는 이점이 있다. 더욱이 증착 및 식각 비율이 낮을수록 즉, 식각 속도가 크면 클수록 보이드없이 배선 사이를 채우는데 유리하다.HDP CVD, on the other hand, is a CVD method in which an electric field and a magnetic field are applied to form plasma ions having a high density, and decompose and deposit a source gas. In particular, HDP CVD is characterized in that deposition and etching proceed in-situ by applying a DC bias during deposition in parallel with high plasma ion density. There is an advantage that the interlayer insulating film can be filled between the wirings without the " Furthermore, the lower the deposition and etching rate, i.e., the higher the etching rate, the better the void filling between the wirings.
도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 금속 배선의 층간 절연막 제조 공정을 나타낸 공정 순서도로서, 이를 참조하여 종래 제조 방법에 대해 설명한다.1A to 1C are process flowcharts illustrating a process for manufacturing an interlayer insulating film of a metal wiring of a semiconductor device according to the prior art, and a conventional manufacturing method will be described with reference to this.
도 1a에 도시된 바와 같이, 반도체 기판(10)으로서 실리콘 기판에 소정의 반도체 소자(미도시함)를 형성하고, 그 위에 하부 층간 절연막(12)을 형성한다. 그리고 하부 층간 절연막(12) 위에 금속 배선(14)을 형성한다. 이때 금속 배선(14)은 장벽 금속(14a), 금속(14b), 장벽 금속(14c)이 적층된 구조일 수 있다.As shown in FIG. 1A, a semiconductor device (not shown) is formed on a silicon substrate as the semiconductor substrate 10, and a lower interlayer insulating film 12 is formed thereon. Then, the metal wiring 14 is formed on the lower interlayer insulating film 12. In this case, the metal wire 14 may have a structure in which the barrier metal 14a, the metal 14b, and the barrier metal 14c are stacked.
도 1b에 도시된 바와 같이, 금속 배선(14)이 있는 결과물 전면에 배선 보호막(16)을 형성하는데, HDP CVD 공정 조건을 증착 및 식각 비율이 높게, 즉 증착 속도를 빠르게 해서 배선 보호막(16)용 산화막을 형성한다.As shown in FIG. 1B, the wiring protection film 16 is formed on the entire surface of the resultant having the metal wiring 14, and the wiring protection film 16 is formed by increasing the deposition and etching rate of HDP CVD process conditions, that is, increasing the deposition rate. A molten oxide film is formed.
그리고 도 1c에 도시된 바와 같이, HDP CVD 공정 조건을 증착 및 식각 비율이 낮게, 즉 증착 속도가 느리게 해서 산화막을 두껍게 증착하여 층간 절연막(18)을 형성한다. 그리고 층간 절연막(18)에 CMP 공정을 실시하여 그 표면을 평탄화시킨다.As illustrated in FIG. 1C, the oxide layer is deposited to have a high deposition rate and a lower etching rate, that is, a slower deposition rate, to form an interlayer insulating layer 18. The interlayer insulating film 18 is subjected to a CMP process to planarize its surface.
종래 기술에 의한 층간 절연막 제조 공정시 배선 보호막(16)의 HDP CVD 증착 초기부터 증착 및 식각 비율이 낮게 하여 층간 절연막(18)을 형성할 경우 식각량이 과도하게 되어 금속 배선(14)의 표면, 특히 배선의 모서리 부분(20)을 식각하여 클리핑(clipping)을 발생시키거나 넓은 공간에 인접한 영역에 HDP 피트(pit)(22)가 발생하게 된다.In the interlayer insulating film manufacturing process according to the prior art, when the interlayer insulating film 18 is formed by lowering the deposition and etching rate from the initial HDP CVD deposition of the wiring protection film 16, the etching amount is excessive, so that the surface of the metal wiring 14, in particular, The edge portion 20 of the wiring is etched to cause clipping or the HDP pit 22 is generated in an area adjacent to a large space.
이러한 배선 모서리(20)의 클리핑 및 HDP 피트(22)는 금속 배선(14)의 전기적 저항을 증가시켜 소자의 성능을 악화시키고 층간 절연막(18)의 평탄화를 위한 CMP 공정 후에도 층간 절연막(18)이 국부적으로 평탄화되지 않아 잔여물을 발생시켜 수율을 저하시키는 원인으로 작용한다.The clipping of the wiring edge 20 and the HDP pits 22 increase the electrical resistance of the metal wiring 14 to deteriorate the performance of the device and to maintain the interlayer insulating film 18 even after the CMP process for planarization of the interlayer insulating film 18. It is not locally planarized, causing residues and lowering the yield.
이러한 현상을 방지하기 위하여 종래에는 배선 보호막(16)으로써 증착 및 식각 속도가 높은, 즉 증착 속도가 매우 빠른 공정을 이용하여 일정 두께의 산화막을 형성한 후에, 다시 증착 및 식각 속도가 느린 공정을 이용하여 층간 절연막(18)인 산화막을 형성하였다.In order to prevent such a phenomenon, conventionally, after forming the oxide film having a predetermined thickness by using a process of having a high deposition and etching rate, that is, a very high deposition rate, as the wiring protection layer 16, a process of using a slow deposition and etching rate is used again. An oxide film, which is an interlayer insulating film 18, was formed.
그러나 HDP CVD 공정은 스텝 커버리지(Step Coverage)가 매우 우수하기 때문에 배선의 상하부 및 측면에 균일하게 증착되어 배선 간격을 더욱더 좁히는 효과가 있기 때문에 증착 및 식각 비율이 낮은 공정을 사용하더라도 보이드 및 배선 모서리의 클리핑이 없는 층간 절연막을 형성하기 어렵다는 문제점이 있다. 이를 방지하기 위하여 배선 보호막(16)의 두께를 높이게 되면 배선 간격이 너무 높아져 층간 절연막(18)의 제조 공정시 HDP CVD 산화막내 보이드가 발생하게 되는 문제점이 있다.However, since HDP CVD process has very good step coverage, it is uniformly deposited on the upper and lower sides and the side of the wiring, thereby further narrowing the wiring gap. Therefore, even when using a process with low deposition and etching rate, There is a problem that it is difficult to form an interlayer insulating film without clipping. In order to prevent this, increasing the thickness of the wiring protection film 16 may cause the wiring gap to be too high, thereby causing voids in the HDP CVD oxide film during the manufacturing process of the interlayer insulating film 18.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 HDP CVD로 층간 절연막을 형성하기 전에, 금속 배선의 보호막으로서 O3를 포함한 절연체박막을 형성함으로써 금속 배선의 모서리에 클리핑 현상 및 보이드가 없도록 하는데 적합한 반도체 소자의 금속 배선의 층간 절연막 제조 방법을 제공하는데 있다.An object of the present invention is to avoid the phenomenon of clipping and voids at the edge of the metal wiring by forming an insulator thin film containing O3 as a protective film of the metal wiring, before forming the interlayer insulating film by HDP CVD to solve the problems of the prior art as described above. The present invention provides a method for producing an interlayer insulating film of a metal wiring of a semiconductor device.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자의 금속 배선을 절연하는 층간 절연막을 제조하는 방법에 있어서, 반도체 기판의 하부 구조물에 하부 층간 절연막을 형성하고 그 위에 금속 배선을 형성하는 단계와, 금속 배선이 있는 결과물 전면에 3%이상인 O3 농도를 포함한 절연체박막을 형성하되, 절연체박막이 하부 층간 절연막 부위에서는 얇게, 금속 배선 부위에서는 두껍게 하는 단계와, O3 절연체박막 상부에 HDP CVD에 의한 상부 층간 절연막을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing an interlayer insulating film for insulating a metal wiring of a semiconductor device, the method comprising the steps of: forming a lower interlayer insulating film on the lower structure of the semiconductor substrate and forming a metal wiring thereon; Forming an insulator thin film containing an O3 concentration of 3% or more on the entire surface of the resultant, wherein the insulator thin film is made thin in the lower interlayer insulating film region and thickened in the metal wiring region, and the upper interlayer insulating film by HDP CVD is formed on the O3 insulator thin film. Forming a step.
도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 금속 배선의 층간 절연막 제조 공정을 나타낸 공정 순서도,1A to 1C are process flowcharts showing a step of manufacturing an interlayer insulating film of a metal wiring of a semiconductor device according to the prior art;
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 배선의 층간 절연막 제조 공정을 나타낸 공정 순서도.2A to 2C are process flowcharts showing a process for manufacturing an interlayer insulating film of a metal wiring of a semiconductor device according to the present invention;
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 반도체 기판 102 : 하부 층간 절연막100 semiconductor substrate 102 lower interlayer insulating film
104 : 금속 배선 104a, 104c : 장벽 금속104: metal wiring 104a, 104c: barrier metal
106 : O3 절연체박막 108 : 상부 층간 절연막106: O3 insulator thin film 108: upper interlayer insulating film
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 배선의 층간 절연막 제조 공정을 나타낸 공정 순서도로서, 이를 참조하여 본 발명의 제조 방법에 대해 설명한다.2A through 2C are process flowcharts illustrating a process for manufacturing an interlayer insulating film of a metal wiring of a semiconductor device according to the present invention, with reference to which a manufacturing method of the present invention will be described.
우선 도 2a에 도시된 바와 같이, 반도체 기판(100)으로서 실리콘 기판에 소정의 반도체 소자(미도시함)를 형성하고, 그 위에 하부 층간 절연막(102)을 형성한다. 그리고 하부 층간 절연막(102) 위에 금속 배선(104)을 형성한다. 이때 금속 배선(104)은 장벽 금속(104a), 금속(104b), 장벽 금속(104c)이 적층된 구조일 수 있다.First, as shown in FIG. 2A, a semiconductor device (not shown) is formed on a silicon substrate as the semiconductor substrate 100, and a lower interlayer insulating film 102 is formed thereon. Then, the metal wire 104 is formed on the lower interlayer insulating film 102. In this case, the metal wire 104 may have a structure in which the barrier metal 104a, the metal 104b, and the barrier metal 104c are stacked.
도 2b에 도시된 바와 같이, 금속 배선(104)이 있는 결과물 전면에 O3를 포함한 절연체박막(106)을 형성하는데, O3 절연체박막(106)은 O3 농도가 3%이상인 O3-TEOS(Tetraethylorthosilicate) 또는 O3-HMDS(Hexamethyldisilazane)를 사용한다. 이때 O3 절연체박막(106)의 두께는 갭필을 하고자 하는 금속배선 간의 간격보다 작아야 하므로 1000Å이하로 증착하는 것이 바람직하다.As shown in FIG. 2B, an insulator thin film 106 containing O3 is formed on the entire surface of the resultant having the metal wiring 104. The O3 insulator thin film 106 is formed of O3-TEOS (Tetraethylorthosilicate) having an O3 concentration of 3% or more. Hexamethyldisilazane (O3-HMDS) is used. At this time, since the thickness of the O3 insulator thin film 106 should be smaller than the gap between the metal wirings to be gap-filled, it is preferable to deposit it at 1000 Å or less.
O3 절연체박막(106)의 증착은 APCVD(Atmospheric Pressure CVD) 또는 SACVD(Sub-Atmospheric CVD)로 형성한다. APCVD의 공정은 상압에서 O3/O2와 TEOS를 N2 또는 He 캐리어 가스와 함께 흘려 300℃∼600℃ 온도범위에서 증착한다.SACVD는 100Torr∼760Torr의 압력하에서 APCVD와 같은 공정조건에서 진행한다.The deposition of the O 3 insulator thin film 106 is formed by Atmospheric Pressure CVD (APCVD) or Sub-Atmospheric CVD (SACVD). The APCVD process deposits O 3 / O 2 and TEOS with N 2 or He carrier gas at atmospheric pressure in the temperature range of 300 ° C. to 600 ° C. SACVD is performed under the same process conditions as APCVD under a pressure of 100 Torr to 760 Torr.
한편 본 발명의 따른 O3 농도가 높은 O3-TEOS 박막의 경우 하부 구조물의 막 종류에 따라 증착 속도가 다르기 때문에 금속 배선(104)에 사용되는 Ti 및 TiN과 같은 장벽 금속(104a, 104c)에서는 중간 속도, Al과 같은 금속(104b)에서는 빠른 속도, 산화막과 같은 하부 층간 절연막(102)에서는 매우 느린 속도로 형성된다. 그러므로, 본 발명은 하부 구조물의 막 종류에 따라서 증착 속도가 다른 특성을 보이는 O3 절연체박막(106)을 층간 절연막 아래 증착함으로써 하부 층간 절연막(102) 에서는 상대적으로 얇게, 금속 배선(104)의 모서리에서는 상대적으로 두껍게 증착된다.Meanwhile, in the case of the O3-TEOS thin film having a high O3 concentration according to the present invention, since the deposition rate is different according to the type of the lower structure film, the intermediate speed is used in the barrier metals 104a and 104c such as Ti and TiN used in the metal wiring 104. , A high speed in the metal 104b such as Al, and a very slow speed in the lower interlayer insulating film 102 such as the oxide film. Therefore, the present invention is relatively thin in the lower interlayer insulating film 102 by depositing the O3 insulator thin film 106 having a different deposition rate according to the film type of the lower structure under the interlayer insulating film, and at the corners of the metal wiring 104. It is deposited relatively thick.
계속해서 도 2c에 도시된 바와 같이, O3 절연체박막(106) 상부에 HDP CVD에 의한 상부 층간 절연막(108)을 형성한다. 이때 HDP CVD 공정은 증착 및 식각 비율이 낮게, 즉 증착 속도가 느리게 해서 층간 절연막(108)을 형성한다. 그리고 층간 절연막(108)에 CMP 공정을 실시하여 그 표면을 평탄화시킨다.Subsequently, as shown in FIG. 2C, an upper interlayer insulating film 108 by HDP CVD is formed on the O3 insulator thin film 106. At this time, in the HDP CVD process, the deposition and etching rate is low, that is, the deposition rate is slow to form the interlayer insulating film 108. The interlayer insulating film 108 is subjected to a CMP process to planarize its surface.
이와 같이 HDP CVD로 상부 층간 절연막(108)을 형성할 때 O3 절연체박막(106)이 금속 배선(104)의 모서리에 두껍게 증착되기 때문에 HDP의 증착 및 식각 비율이 낮은 조건에 따라 식각 속도가 빠르더라도 클리핑 현상없이 배선 사이에 보이드가 없는 층간 절연막(108)을 형성할 수 있다.As described above, when the upper interlayer insulating film 108 is formed by HDP CVD, since the O3 insulator thin film 106 is thickly deposited on the corners of the metal wiring 104, the etching rate is high due to the low deposition and etching ratio of the HDP. An interlayer insulating film 108 without voids may be formed between the lines without clipping.
따라서, 본 발명은 종래의 기술과 달리 배선 보호막으로 사용되는 HDP CVD 산화막 대신에 하부 구조물에 대해 선택적 증착이 가능한 O3 절연체박막(106)을 형성함으로써 금속 배선(104)의 측면 및 모서리에만 주로 두껍게 증착하고 금속 배선(104)의 상부와 하부 층간 절연막(102)에는 얇게 증착되도록 하여 높은 식각속도를 갖는 HDP CVD로 층간 절연막(108)을 증착할 때에 배선의 모서리에 클리핑 현상이 발생되지 않도록 함과 동시에 넓은 영역에서 도면 부호 110과 같이 HDP 피트를 제거할 수 있고 좁은 영역에서 보이드가 발생되지 않도록 할 수 있다.Accordingly, the present invention mainly thickly deposited only on the side and corners of the metal wiring 104 by forming the O3 insulator thin film 106, which is capable of selectively depositing on the underlying structure, instead of the HDP CVD oxide film used as the wiring protection film, unlike the conventional technology. The thin film is deposited on the upper and lower interlayer insulating film 102 of the metal wiring 104 to prevent the occurrence of clipping at the edges of the wiring when the interlayer insulating film 108 is deposited by HDP CVD with a high etching rate. In a large area, as shown by reference numeral 110, the HDP pit may be removed and voids may not be generated in a narrow area.
이상 설명한 바와 같이, 본 발명은 HDP CVD로 상부 층간 절연막을 형성하기 전에, 금속 배선의 보호막으로서 3% 이상의 O3 농도를 포함한 절연체박막을 형성함으로써 HDP CVD 층간 절연막의 제조 공정시 금속 배선의 모서리에 클리핑 현상과 HDP 피트 및 보이드가 없도록 하여 반도체 소자의 성능 향상과 수율을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, before forming the upper interlayer insulating film by HDP CVD, forming an insulator thin film containing an O 3 concentration of 3% or more as a protective film of the metal wiring, thereby clipping the corners of the metal wiring during the manufacturing process of the HDP CVD interlayer insulating film. By eliminating the phenomenon and HDP pits and voids, it is possible to improve performance and yield of semiconductor devices.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07273194A (en) * | 1994-03-30 | 1995-10-20 | Nec Corp | Fabrication of semiconductor device |
| JPH11219951A (en) * | 1997-11-25 | 1999-08-10 | Sony Corp | Semiconductor manufacturing method and apparatus |
| JPH11330237A (en) * | 1998-05-14 | 1999-11-30 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2001110804A (en) * | 1999-10-07 | 2001-04-20 | Matsushita Electronics Industry Corp | Semiconductor device and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07273194A (en) * | 1994-03-30 | 1995-10-20 | Nec Corp | Fabrication of semiconductor device |
| JPH11219951A (en) * | 1997-11-25 | 1999-08-10 | Sony Corp | Semiconductor manufacturing method and apparatus |
| JPH11330237A (en) * | 1998-05-14 | 1999-11-30 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2001110804A (en) * | 1999-10-07 | 2001-04-20 | Matsushita Electronics Industry Corp | Semiconductor device and its manufacturing method |
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