KR20010005223A - a manufacturing method of a thin film transistor array panel for liquid crystal displays and a structure of align keys thereof - Google Patents

Abstract

A gate wiring such as a gate line, a gate electrode, and a gate pad is formed on the substrate, and a gate insulating film, an ohmic contact layer, a semiconductor layer, and a metal film for data wiring are successively deposited on the substrate, and then partially formed in a single photographing process. A thin film transistor substrate for a liquid crystal display device which forms a data line, a source and drain electrode, a data line such as a data pad, and an alignment key by patterning a lower metal layer for data wiring, a semiconductor layer, and a contact layer using another photoresist pattern. In the manufacturing method, in the step of forming the gate wiring, the auxiliary metal pattern and the auxiliary alignment key are formed on the substrate under the data pad and the alignment key with the gate wiring metal, respectively. As such, in this structure in which the sub-metal pattern and the sub-alignment key cover the semiconductor pattern having low reflectance under the alignment key and the data pad, the data wiring, the contact layer and the semiconductor layer under the pattern are simultaneously patterned using a single mask. Even in this case, the data pad and the alignment key can be used to measure the alignment position.

Description

A manufacturing method of a thin film transistor array panel for liquid crystal displays and a structure of align keys according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same, and more particularly, to a method of forming an alignment key used for aligning a liquid crystal display device and various equipment in a manufacturing process of a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured by a photolithography process using a mask, and five or six masks are usually used. Since masks are expensive consumables, it is desirable to use fewer masks to reduce production costs. Therefore, in recent years, research on the manufacturing method using the number of masks of four or less has been active.

Each photolithography process using a mask includes aligning a mask with a thin film transistor substrate coated with a photoresist film, exposing a photoresist film applied to the substrate, and then developing the photoresist film. In particular, the alignment of the mask and the substrate is performed by irradiating light in the vicinity of the alignment key formed in the gate pad or data pad region of the substrate, and detecting the reflected light to determine the alignment position. Therefore, the alignment key should be opaque and excellent in reflectivity. For this purpose, it is common to form the alignment key in the step of forming the gate wiring or the data wiring with the metal for the gate wiring or the metal for the data wiring.

In addition to the photolithography process using a mask, alignment using an alignment key can be performed in addition to array inspection of various thin film transistor substrates, application of alignment layers, application of seal materials, matching of thin film transistor substrates to opposing substrates, substrate cutting and It is also used to align substrates and substrates in processes such as grinding, attaching polarizers, and outer lead bonding (OLB) that connects a tape carrier package (TCP) to a liquid crystal display substrate.

In particular, since the OLB process is a process in which an external signal line is connected to a wire in the liquid crystal display, more precise alignment is required.

An object of the present invention is to provide a new method that can reduce the number of masks when manufacturing a thin film transistor substrate for a liquid crystal display device.

An object of the present invention is to provide a method of forming an alignment key for precisely aligning a liquid crystal display device and an external device without a separate process.

1 is a layout view schematically illustrating a liquid crystal display device;

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3 to 6 are cross-sectional views of the thin film transistor substrate for the liquid crystal display device shown in FIG. 2 taken along lines III-III ', IV-IV', V-V 'and VI-VI', respectively.

7A is a layout view of a thin film transistor substrate in a first stage of manufacture in accordance with an embodiment of the invention,

7B, 7C, 7D, and 7E are cross-sectional views taken along lines VIIb-VIIb ', VIIc-VIIc', VIId-VIId ', and VIIe-VIIe', respectively, in FIG. 7A;

8A, 8B, 8C, and 8D are cross-sectional views taken along the lines VIIb-VIIb ', VIIc-VIIc', VIId-VIId ', and VIIe-VIIe' in FIG. 7A, respectively, and FIGS. 7B, 7C, and 7D. And 7e is a cross sectional view in the next step,

9A is a layout view of a thin film transistor substrate in the next steps of FIGS. 8A, 8B, 8C, and 8D;

9B, 9C, 9D, and 9E are cross-sectional views taken along the lines IXb-IXb ', IXc-IXc', IXd-IXd ', and IXe-IXe' in FIG. 9A, respectively.

10A, 10B, 10C, and 10D are cross-sectional views taken along the lines IXb-IXb ', IXc-IXc', IXd-IXd ', and IXe-IXe' in FIG. 9A, respectively, and FIGS. 9B, 9C, and 9D. And 9e the following steps are shown in order of process;

11A, 11B, 11C, and 11D are cross-sectional views taken along the lines IXb-IXb ', IXc-IXc', IXd-IXd ', and IXe-IXe' in FIG. 9A, respectively. The steps 10b, 10c and 10d are shown in the order of the process,

12A and 12B are cross-sectional views illustrating a state in which light is irradiated to an alignment key.

In order to achieve the above object, in the present invention, an auxiliary alignment key and an auxiliary metal pattern are provided below the alignment key formed of the data wiring metal and the low reflectance semiconductor pattern under the data pad to prevent the reflectance of the measurement light for alignment from being lowered. .

In the method for manufacturing a thin film transistor substrate for a liquid crystal display device according to the present invention, a gate wiring metal film is first deposited on an insulating substrate, and the gate wiring metal film is etched to form a gate line, a gate electrode connected to the gate line, and a gate connected to the end of the gate line. A gate wiring including a pad and a first metal pattern are formed. Next, the gate insulating film, the semiconductor layer, the ohmic contact layer, and the data wiring metal film are successively deposited on the gate wiring, the first metal pattern and the substrate, and then the first portion having the first thickness on the data wiring metal film through a photolithography process. And a photosensitive film pattern having a second portion having a thickness thicker than the first thickness and a third portion having no thickness. Subsequently, the metal layer for data wiring, the ohmic contact layer, and the semiconductor layer are patterned by using a photoresist pattern to form a source and drain electrode that are separated from each other, a data line connected to the source electrode, and an end of the data line. After forming a data line including a data pad formed on the first metal pattern, a contact layer pattern and a semiconductor pattern below the data line, the photoresist pattern is removed. In this case, the first portion and the second portion correspond to portions between the source and drain electrodes and data lines, respectively, so that the semiconductor pattern is not removed from the portions between the source and drain electrodes. Next, a passivation layer pattern covering the data line and having a first contact hole exposing the drain electrode is formed, and a pixel electrode connected to the drain electrode is formed through the first contact hole.

The data wiring, the contact layer pattern, and the semiconductor pattern can be formed using a single mask, in which the mask used is the first part where only part of the light can be transmitted, the second part where the light can be completely transmitted, and the light completely transmitted. It is preferable to include a third portion that cannot be formed, and to arrange the first, second, and third portions of the mask to correspond to the first, second, and third portions of the photoresist pattern, respectively, during the exposure process.

The first part of the mask may comprise a pattern that is smaller in size than the resolution of the light source used in the translucent film or the exposure step.

A plurality of first alignment keys may be formed near the gate pad or the data pad by etching the gate wiring metal layer.

Further, after forming the plurality of second alignment keys in the vicinity of the gate pad or the data pad in the etching of the gate wiring metal film, the upper portion of the second alignment key in the etching of the data wiring metal film, the contact layer, and the semiconductor layer. A plurality of corresponding third alignment keys and a contact layer pattern and a semiconductor pattern positioned between the third and second alignment keys may be formed.

On the other hand, the thin film transistor substrate formed by this method includes a display area and a pad area located outside the display area, and an alignment key is formed in the pad area. This alignment key has a stacking order of a first metal layer pattern, an insulating film layer pattern, a semiconductor layer pattern, and a second metal layer pattern.

Here, the semiconductor layer pattern may be composed of an amorphous silicon layer and a doped amorphous silicon layer.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, the structure of a liquid crystal display will be described with reference to FIG. 1.

1 is a layout view schematically illustrating a liquid crystal display.

As illustrated in FIG. 1, a plurality of gate lines 22 are formed in the lower thin film transistor substrate 10 in a horizontal direction, and gate pads 24 are formed at ends of the gate lines 22, respectively. Here, the gate pads 24 are formed in a plurality to form a gate pad block. In addition, a plurality of data lines 62 are insulated from the gate lines 22 in the vertical direction, and data pads 64 are formed at ends of the data lines 62, respectively. A large number of them form a data pad block. The gate line 22 and the data line 62 cross each other to form a plurality of pixel regions, and the plurality of pixel regions gather to form an active area (A / A), which is an area for displaying a liquid crystal display. . In each pixel region, a thin film transistor is formed in which respective terminals are connected to the gate line 22, the data line 62, and a pixel electrode (not shown). In addition, on both sides of the gate pad block and the data pad block, a plurality of alignment keys (A) may be used for inspecting an array of thin film transistor substrates, applying an actual coating, matching a thin film transistor substrate with an opposing substrate, and connecting a tape carrier package. / K) is formed of a metal for gate wiring or a metal for data wiring.

A counter substrate 11 having a transparent electrode (not shown) formed on its entire surface corresponds to face an active area A / A of the thin film transistor substrate 10. The opposing substrate 11 may be formed with a color filter.

A liquid crystal layer (not shown) is injected between the thin film transistor substrate 10 and the counter substrate 11, and a voltage applied between the pixel electrode of the thin film transistor substrate 10 and the transparent common electrode of the counter substrate 11 is applied. As a result, the light transmittance of the liquid crystal layer is changed to implement display.

Although not shown, a tape carrier package in which integrated circuits are mounted on the gate pad 24 and the data pad 64 of the liquid crystal display device is attached in units of gate and data pad blocks so that scan signals and image signals may be respectively provided. Supply to gate line and data line.

In order to manufacture such a liquid crystal display, the counter substrate 11 and the tape carrier package are aligned with the thin film transistor substrate 10, and the alignment key A / K is used for the alignment. In particular, in the case where the tape carrier package is connected to the pads 24 and 64, the pads 24 and 64 may be used after the alignment using the alignment keys A / K. Secondary alignment to find the correct alignment point and connect the tape carrier package.

However, in the case of a method of reducing the number of masks used for manufacturing a thin film transistor substrate to four by simultaneously patterning a lower contact layer and a semiconductor layer simultaneously with data wiring, an alignment key (A / K) formed of a data wiring or a metal for data wiring Alternatively, it is preferable to add a pattern having a high reflectance to the lower layer of the semiconductor layer having a low reflectance below the data pad 64.

Then, the structure of the thin film transistor substrate for a liquid crystal display according to the exemplary embodiment of the present invention having the alignment key A / K formed of the data wiring metal and the auxiliary pattern formed of the gate wiring metal under the data pad 64. Explain.

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 3 to 6 are lines III-III ', IV-IV', VV ', and VI-VI' of FIG. 2. It is sectional drawing cut along the line.

2 to 6, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta) on the insulating substrate 10 A gate wiring made of a metal or a conductor such as) is formed. The gate wiring is connected to the scan signal line or the gate line 22 extending in the horizontal direction and the gate line 22 and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 22. A gate electrode 26 of the thin film transistor that is part of the line 22, and a sustain electrode 28 that is parallel to the gate line 22 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. . The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, It may not be formed when the holding capacity generated by the overlap of (22) is sufficient.

A first alignment key made of metal for gate wiring in the edge portion A1 of the substrate 10 on which the gate pad 24 is formed or in the edge portion A2 of the substrate 10 on which the data pad 64 is to be formed, that is, the pad region. 21, the auxiliary alignment key 23 and the auxiliary metal pattern 25 are formed. The first alignment key 21 is arbitrarily formed at the outer side of the gate pad block (see FIG. 1) or the data pad block (see FIG. 1), and the auxiliary alignment key 23 is also formed on the gate pad block or the data pad block. A plurality of arbitrary ones are formed outside, and the auxiliary metal patterns 25 are formed to correspond to the lower portions of the data pads 64, which will be described later.

A gate insulating layer 30 made of silicon nitride (SiN _x ) is formed on the gate wirings 22, 24, 26, 28, the first alignment key 21, the auxiliary alignment key 23, and the auxiliary metal pattern 25. The gate wirings 22, 24, 26, 28, the alignment key 21, the auxiliary alignment key 23, and the auxiliary metal pattern 25 are covered.

On the gate insulating layer 30, semiconductor patterns 42, 43 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and n such as phosphorus (P) is formed on the semiconductor patterns 42, 43 and 48. An ohmic contact layer pattern 53, 55, 56, 58 made of amorphous silicon doped at high concentration with a type impurity is formed.

On the contact layer patterns 53, 55, 56, and 58, a data line made of a conductive material such as Mo or MoW alloy, Cr, Al or Al alloy, Ta, and a second alignment key 63 are formed. The data line is located above the data line 62 formed in the vertical direction and the auxiliary metal pattern 25 formed of the metal for gate wiring, and is connected to one end of the data line 62 to apply an image signal from the outside. A data line portion consisting of a receiving data pad 64 and a source electrode 65 of a thin film transistor, which is a branch of the data line 62, and is separated from the data line portions 62, 64, and 65, and is a gate electrode 26; Or the conductive capacitor pattern 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor, which is located opposite the source electrode 65 with respect to the channel portion C of the thin film transistor. do. In the case where the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed. The second alignment key 63 is formed on the auxiliary alignment key 25 formed of the metal for gate wiring.

Here, the contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. This has the same shape as the data wires 62, 64, 65, 66 and 68. That is, the data line part contact layer pattern 55 is the same as the data line parts 62, 64, and 65, and the drain electrode contact layer pattern 56 is the same as the drain electrode 66, and the contact layer pattern for the storage capacitor ( 58 is the same as the conductor pattern 68 for the storage capacitor. In addition, the contact layer pattern 53 under the second alignment key 63 has the same shape as the second alignment key 63.

Meanwhile, except for the channel portion C of the thin film transistor, the semiconductor patterns 42, 43, and 48 may include the data lines 62, 64, 65, 66, 68, the second alignment key 63, and the contact layer pattern ( 53, 55, 56, and 57). Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, and the second alignment key 63 and the contact layer thereunder. The pattern 53 and the semiconductor pattern 43 have the same shape, but the semiconductor pattern 42 for the thin film transistor is slightly different from the rest of the data wiring and the contact layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the data line contact layer pattern 55 contacts the drain electrode. Although the layer pattern 56 is also separated, the semiconductor pattern 42 for thin film transistors is connected here without disconnection to generate a channel of the thin film transistor.

The passivation layer 70 is formed on the data lines 62, 64, 65, 66, 68, and the second alignment key 63, and the passivation layer 70 includes the drain electrode 66, the data pad 64, and the storage capacitor. It has contact holes 71, 73 and 74 which expose the existing conductor pattern 68, and also has the contact hole 72 which exposes the gate pad 24 together with the gate insulating film 30. As shown in FIG.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO) or indium-zinc-oxide (IZO). The pixel electrode 82 is physically and electrically connected to the drain electrode 66 through the contact hole 71 so that an image Receive a signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the storage capacitor conductor pattern 68 through the contact hole 74 to transmit an image signal to the conductor pattern 68. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 connected to the gate pad 24 and the data pad 64 through the contact holes 72 and 73, respectively, are formed. , 64) and to protect the pads and the adhesion of the external circuit device, it is not essential, and their application is optional.

Although transparent ITO has been used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

As described above, in the exemplary embodiment of the present invention, the auxiliary metal pattern 25 is formed under the data pad 64 via the contact layer pattern 56, the semiconductor pattern 42, and the gate insulating layer 30. Since the auxiliary alignment key 23 is formed under the second alignment key 63 formed of the wiring metal via the contact layer pattern 53, the semiconductor pattern 43, and the gate insulating film 30, the gate is formed. It is possible to use not only the alignment key 21 formed of the wiring metal, but also the second alignment key 63 and the data pad 64 having the semiconductor patterns 43 and 42 formed thereon for alignment. That is, even if the second alignment key 63 and the data pad 64 are irradiated with light from either the front or the rear of the substrate 10, the amount of reflected light is not significantly different. ) And other external fixtures and substrates are possible.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7A to 11D and FIGS. 2 to 6.

First, as illustrated in FIGS. 7A to 7E, a conductive layer such as a metal is deposited to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and first, dry or wet etch using a mask to form a gate on the substrate 10. A gate wiring including a line 22, a gate pad 24, a gate electrode 26, and a storage electrode 28, a first alignment key 21, an auxiliary alignment key 24, an auxiliary metal pattern 25, and the like. To form.

Next, as shown in FIGS. 8A and 8D, the gate insulating film 30, the semiconductor layer 40, and the contact layer 50 are respectively 1,500 mV to 5,000 mV, 500 mV to 2,000 mV, 300 using chemical vapor deposition. Continuous deposition to a thickness of Å to 600 Å, and then a conductive layer 60 such as metal was deposited to a thickness of 1,500 Å to 3,000 Å by sputtering or the like, and then the photosensitive film 110 was deposited thereon from 1 μm to 2 μm. Apply to thickness.

Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 9A to 9E. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, may include the data wires 62, 64, and 65. , 66, 68, and the second alignment key 63 to be smaller in thickness than the second portion 112 positioned in the portion A to be formed, and the photosensitive film of the other portion B is removed. At this time, the thickness of the photoresist film 114 remaining in the channel portion C, and the photoresist film remaining in the portion A in which the data lines 62, 64, 65, 66, 68 and the second alignment key 63 are to be formed. The ratio of the thickness of the (112) should be different depending on the process conditions in the etching process to be described later, it is preferable to make the thickness of the first portion 114 to 1/2 or less of the thickness of the second portion 112, For example, it is good that it is 4,000 Pa or less.

As described above, a method of varying the thickness of the photoresist film according to the position includes a method of forming a pattern smaller than the resolution, for example, a slit or lattice pattern, or adjusting a dose of light by placing a translucent film.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the contact layer 50, and the semiconductor layer 40. In this case, the data wires 63, 64, 65, 66, 68 and the second alignment key (A) in which the data wires 62, 64, 65, 66, 68 and the second alignment key 63 are to be formed. 63) and the films below it, and only the semiconductor layer 40 remains in the channel portion C, and the upper three layers 60, 50, and 40 are all removed in the remaining portion B. The insulating film 30 should be exposed.

In more detail, first, as shown in FIGS. 10A and 10B, when the exposed conductor layer 60 of the other portion B is removed, the channel portion C, the data wiring, and the alignment key are formed. The conductor layer of the part A, i.e., the conductor pattern for the source / drain and the conductor pattern 68 for the storage capacitor and the pattern of the second alignment key 63 remain, and the conductor layer 60 of the other part B All are removed to reveal the underlying contact layer 50.

Subsequently, the exposed contact layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. The etching may be performed under the condition that the photoresist patterns 112 and 114, the contact layer 50, and the semiconductor layer 40 are simultaneously etched and the gate insulating layer 30 is not etched. ) And the etching ratio of the semiconductor layer 40 is preferably the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the contact layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, and removing the contact layer 50 and the semiconductor layer 40 of the other portion B. As a result, the lower gate insulating layer 30 is exposed to complete the semiconductor pattern. On the other hand, since the second portion 112 of the portion A on which the data line and the second alignment key are to be formed is also etched, the thickness becomes thin.

Next, the photoresist film residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C is removed through ashing, and then the source / drain conductor pattern 67 and the contact layer thereunder are removed. When the pattern 50 is etched, as illustrated in FIGS. 11A through 11D, the data wirings 62, 64, 65, 66, and 68 including the source electrode 65 and the drain electrode 66, and lower portions thereof may be formed. The contact layer patterns 55, 56, and 58, the semiconductor patterns 42 and 48, the second alignment key 63, and the contact layer pattern 53 and the semiconductor pattern 43 below are completed.

Finally, the remaining photoresist second portion 112 is removed.

After the data wirings 62, 64, 65, 66, 68 and the second alignment key 63 are formed in this manner, a protective film 70 having a thickness of 3,000 Pa or more is formed of silicon nitride or the like. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor, respectively. The exposed contact holes 71, 72, 73, 74 are formed.

Lastly, as shown in FIGS. 2 to 6, an ITO layer or an IZO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to etch the pixel electrode 82, the auxiliary gate pad 84, and An auxiliary data pad 86 is formed.

As described above, in the method of manufacturing the thin film transistor substrate for the liquid crystal display device according to the present exemplary embodiment, the data lines 62, 64, 65, 66, and 68 and the second alignment key 63 and the contact layer patterns 53 and 55 thereunder. , 56, 58, and semiconductor patterns 42, 43, and 48 are formed using one mask, and the source electrode 65 and the drain electrode 66 are separated in this process, thereby using only four masks. It is possible to manufacture transistor substrates. In addition, the auxiliary alignment key 23 and the auxiliary metal pattern 25 covering the semiconductor patterns 43 and 42 having low reflectivity are hidden on the lower layer of the second alignment key 63 and the gate pad 64 in the step of forming the gate wiring. ), It is possible to align not only the first alignment key 21 but also the front and rear surfaces of the thin film transistor substrate 10 using the second alignment key 63 and the data pad 64. Do.

This will be described in more detail with reference to FIGS. 12A and 12B.

FIG. 12A is a cross-sectional view of a first alignment key structure formed of a metal for gate wiring, and FIG. 12B is a cross-sectional view of a second alignment key structure formed of a data wiring metal and a metal for gate wiring, in which light is irradiated to each alignment key. Shows.

First, as shown in FIG. 12A, the gate insulating film 30 and the protective film 70 are covered only on the first alignment key 21 formed of the gate wiring metal and have a high reflectance. Since no low film exists, the measurement lights f and g irradiated from the front and the rear of the thin film transistor substrate 10 are respectively reflected at the front and rear of the first alignment key 21. Therefore, the exact position of the first alignment key 21 can be measured.

Next, in FIG. 12B, the passivation layer 70 is covered on the upper portion of the second alignment key 63 formed of the data wiring metal, and the contact layer pattern 53 having the same pattern as the second alignment key 63 is disposed on the lower portion. A lower semiconductor pattern 43 is formed, and an auxiliary alignment key 23 formed of a metal for gate wiring through a gate insulating film 30 is formed below the semiconductor pattern 43.

In this case, the measurement light f irradiated from the front side of the thin film transistor substrate 10 is reflected from the front side of the second alignment key 63. In addition, the measurement light b irradiated from the rear side of the thin film transistor substrate 10 is irradiated to the secondary alignment key 23 having a high reflectance rather than the semiconductor pattern 43 having a low reflectance, which is the second alignment key 63. Although the contact layer pattern 53 and the semiconductor pattern 43 with low reflectance are formed below, the auxiliary alignment key 23 is formed with the metal for gate wiring with high reflectivity in the lower layer of the semiconductor pattern 43. to be. Therefore, the alignment position can be measured relatively accurately in any of the front and rear surfaces of the substrate 10.

The structure of the data pad 64 and the subordinate metal pattern 25 underlying the same may be aligned for the OLB process in the same manner as in the structure of the second alignment key 63 and the subordinate alignment key 23 disposed thereunder. It can be used for measurement.

As mentioned above with reference to FIG. 1, for the OLB process of bonding a tape carrier package to each data pad block, each tape carrier package must first be aligned with the thin film transistor substrate 10 on a data pad block basis. . Alignment for the OLB process requires precision compared to the process of aligning other external equipment to the substrate 10, so that a plurality of first or second alignment keys 21 and 63 located outside of the data pad 64 are used. After the alignment, the data pads 64 are each aligned secondly using the alignment keys. In this case, since the auxiliary metal pattern 25 having the reflectance is formed on the lowermost layer below the data pad 64, misalignment due to the decrease of the reflectance can be prevented.

As described above, according to the present invention, not only the number of masks can be effectively reduced when the thin film transistor substrate for the liquid crystal display is manufactured, but also an alignment key for precisely aligning the liquid crystal display and the external device can be formed without a separate process. .

Claims (9)

Depositing a metal film for gate wiring on an insulating substrate, Etching the gate wiring metal layer to form a gate wiring including a gate line, a gate electrode connected to the gate line, and a gate pad connected to an end of the gate line, and a first metal pattern; Continuously depositing a gate insulating film, a semiconductor layer, an ohmic contact layer, and a metal film for data wiring on the gate wiring, the first metal pattern, and the substrate; Forming a photoresist pattern having a first portion having a first thickness, a second portion having a thickness thicker than the first thickness, and a third portion having no thickness through the photolithography process; The data wiring metal layer, the ohmic contact layer, and the semiconductor layer are patterned by using the photoresist pattern, and are formed to be separated from each other, a source and drain electrode, a data line connected to the source electrode, and an end of the data line. Forming a data line including a data pad formed on the first metal pattern, a contact layer pattern and a semiconductor pattern below the data line; Removing the photoresist pattern; Forming a passivation layer pattern covering the data line and having a first contact hole exposing the drain electrode; Forming a pixel electrode connected to the drain electrode through the first contact hole, Manufacturing the thin film transistor substrate for a liquid crystal display device wherein the first portion and the second portion correspond to portions between the source and drain electrodes and the data lines, respectively, and do not remove the semiconductor pattern from portions between the source and drain electrodes. Way. In claim 1, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the data line, the contact layer pattern, and the semiconductor pattern are formed using one mask. In claim 2, The mask used in the photolithography process includes a first part through which only part of the light can be transmitted, a second part through which light can be completely transmitted, and a third part through which light cannot be completely transmitted, and the first, second, and third parts of the mask. The portion is arranged to correspond to the first, second, and third portion of the photosensitive film pattern during the exposure process, respectively. In claim 3, The first portion of the mask comprises a semi-transparent film manufacturing method of a thin film transistor substrate for a liquid crystal display device. In claim 3, And a first portion of the mask comprises a pattern smaller in size than the resolution of the light source used in the exposing step. In claim 1, And etching the gate wiring metal layer to form a plurality of first alignment keys in the vicinity of the gate pad or the data pad. In claim 1, Etching the gate wiring metal layer to form a plurality of second alignment keys near the gate pad or the data pad; The metal layer for data wiring, the contact layer, and the semiconductor layer are etched to form a plurality of third alignment keys corresponding to an upper portion of the second alignment key, and the contact layer pattern positioned between the third and second alignment keys. And forming the semiconductor pattern. A substrate including a display area and a pad area positioned outside the display area, and An alignment key pattern positioned in the pad region, the alignment key pattern including a first metal layer pattern, an insulating layer layer pattern on the first metal layer pattern, a semiconductor layer pattern on the insulating layer layer pattern, and a second metal layer pattern on the semiconductor layer pattern Thin film transistor substrate for a liquid crystal display device comprising a. In claim 8, The semiconductor layer pattern may include an amorphous silicon layer and a doped amorphous silicon layer.