KR20000045306A - Method for fabricating tft lcd device - Google Patents
Method for fabricating tft lcd device Download PDFInfo
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- KR20000045306A KR20000045306A KR1019980061864A KR19980061864A KR20000045306A KR 20000045306 A KR20000045306 A KR 20000045306A KR 1019980061864 A KR1019980061864 A KR 1019980061864A KR 19980061864 A KR19980061864 A KR 19980061864A KR 20000045306 A KR20000045306 A KR 20000045306A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 36
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000011241 protective layer Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims description 8
- 239000012044 organic layer Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 18
- 239000011521 glass Substances 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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Abstract
Description
본 발명은 박막 트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, 박막 트랜지스터의 소오스/드레인 전극을 ITO 금속막으로 형성하는 박막 트랜지스터 액정표시소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor liquid crystal display device in which a source / drain electrode of a thin film transistor is formed of an ITO metal film.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 각 화소의 구동을 독립적으로 제어하기 위한 스위칭 소자로서 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합하다는 잇점 때문에, CRT에 필적할만한 화면의 고화질화 및 대형화, 컬러화 등을 실현하는데 크게 기여하고 있다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, a TFT LCD equipped with a thin film transistor (TFT) as a switching element for independently controlling the driving of each pixel is comparable to a CRT because of its advantages of high-speed response characteristics and its suitability for high pixel numbers. It is greatly contributing to the realization of high quality screen, large size, and color.
이러한 TFT LCD는 TFT 및 화소전극이 형성된 하부기판과, 컬러필터 및 상대전극이 형성된 상부기판이 액정의 개재하에 합착된 구조이다.The TFT LCD has a structure in which a lower substrate on which a TFT and a pixel electrode are formed, and an upper substrate on which a color filter and a counter electrode are formed are bonded to each other through liquid crystal.
도 1a 내지 도 1d는 종래 기술에 따른 TFT LCD의 하부기판 제조방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.1A to 1D are cross-sectional views illustrating a method of manufacturing a lower substrate of a TFT LCD according to the prior art, which will be described below.
우선, 도 1a에 도시된 바와 같이, 유리기판(1) 상에 게이트 전극(2)을 형성하고, 상기 게이트 전극(2)을 포함한 유리기판(1)의 전면 상에 게이트 절연막(3)을 도포한다.First, as shown in FIG. 1A, a gate electrode 2 is formed on a glass substrate 1, and a gate insulating film 3 is coated on the entire surface of the glass substrate 1 including the gate electrode 2. do.
이어서, 도 1b에 도시된 바와 같이, 게이트 절연막(3) 상에 도핑되지 않은 비정질실리콘층(이하, a-Si층 이라 칭함)을 도포하고, 상기 a-Si층에 대한 식각 공정을 수행하여 TFT의 반도체층(4)을 형성한다.Subsequently, as shown in FIG. 1B, an undoped amorphous silicon layer (hereinafter referred to as an a-Si layer) is coated on the gate insulating film 3, and an etching process is performed on the a-Si layer to perform TFT. Semiconductor layer 4 is formed.
다음으로, 도 1c에 도시된 바와 같이, 전체 상부에 투명 금속막, 예컨데, ITO 금속막을 증착하고, 상기 ITO 금속막에 대한 식각 공정을 수행하여 화소영역 상에 화소전극(5)을 형성한다. 그런 다음, 도시되지는 않았으나, 회로부와 전기적으로 연결될 전극패드 부분을 노출시키기 위한 식각 공정을 수행한다.Next, as shown in FIG. 1C, a transparent metal film, for example, an ITO metal film is deposited on the entire surface, and the pixel electrode 5 is formed on the pixel region by performing an etching process on the ITO metal film. Then, although not shown, an etching process for exposing the electrode pad portion to be electrically connected to the circuit unit is performed.
그리고 나서, 도 1d에 도시된 바와 같이, 전체 상부에 소정의 금속막을 증착하고, 이를 패터닝하여 소오스/드레인 전극(6)을 형성함으로써, TFT를 완성한다. 그런 다음, 전체 상부에 폴리이미드와 같은 유기막을 증착한 후에, 상기 유기막을 식각하여 TFT를 보호하는 보호층(7)을 형성한다.Then, as shown in Fig. 1D, a predetermined metal film is deposited on the whole and patterned to form a source / drain electrode 6, thereby completing the TFT. Then, after depositing an organic film such as polyimide on the whole, the organic film is etched to form a protective layer 7 protecting the TFT.
상기에서, 소오스/드레인 전극(6)을 형성하기 전에, 반도체층(4)과 금속막간의 접촉 특성을 향상시키기 위하여, 도핑된 비정질실리콘층(이하, N+a-Si층이라 칭함)을 형성하며, 아울러, 상기 N+a-Si층은 소오스/드레인 전극을 형성하기 위한 금속막의 식각시에 함께 식각한다.In the above, before the source / drain electrodes 6 are formed, a doped amorphous silicon layer (hereinafter referred to as N + a-Si layer) is formed in order to improve contact characteristics between the semiconductor layer 4 and the metal film. In addition, the N + a-Si layer is etched together during the etching of the metal film for forming the source / drain electrodes.
그러나, 상기와 같은 종래 기술에 따른 TFT LCD의 하부기판은 통상 6매 또는 7매 정도의 식각 마스크를 이용하여 제작하기 때문에, 공정이 복잡할 뿐만 아니라, 제조 단가를 감소시키는데, 그 한계가 있는 문제점이 있었다.However, since the lower substrate of the TFT LCD according to the related art is usually manufactured using an etching mask having about 6 or 7 sheets, the process is not only complicated, but also reduces the manufacturing cost. There was this.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 공정 수를 감소시킴으로써, 공정의 단순화 및 제조 단가를 낮출 수 있는 TFT LCD의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a TFT LCD which can simplify the process and lower the manufacturing cost by reducing the number of processes.
도 1a 내지 도 1d는 종래 기술에 따른 박막 트랜지스터 액정표시소자의 하부기판의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a lower substrate of a thin film transistor liquid crystal display device according to the prior art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 박막 트랜지스터 액정표시소자의 하부기판의 제조방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a lower substrate of a thin film transistor liquid crystal display device according to an exemplary embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 유리기판 12 : 게이트 전극11 glass substrate 12 gate electrode
13 : 게이트 절연막 14 : a-Si층13 gate insulating film 14 a-Si layer
15 : N+a-Si층 16 : 불투명 금속막15: N + a-Si layer 16: opaque metal film
17a : 소오스 전극 17b : 드레인 전극17a: source electrode 17b: drain electrode
18 : 화소전극 19 : 보호층18 pixel electrode 19 protective layer
상기와 같은 목적을 달성하기 위한 본 발명의 TFT LCD의 제조방법은, 절연기판 상에 게이트 전극을 형성하는 단계; 상기 게이트 전극을 포함한 절연기판의 전면 상에 게이트 절연막, a-Si층, N+a-Si층 및 불투명 금속막을 순차적으로 형성하는 단계; TFT의 반도체층이 형성되도록, 상기 불투명 금속막과 N+a-Si층 및 a-Si층을 식각하는 단계; 전체 상부에 투명 금속막을 증착하고, 상기 투명 금속막을 식각하여 TFT의 소오스 전극 및 드레인 전극과 화소전극을 형성하는 단계; 및 전체 상부에 유기막을 증착하고, 상기 유기막을 식각하여 TFT를 보호하는 보호층을 형성하는 단계를 포함하여 이루어지며, 상기 화소전극과 TFT의 소오스 전극은 일체형으로 형성된 것을 특징으로 한다.A method of manufacturing a TFT LCD of the present invention for achieving the above object comprises the steps of forming a gate electrode on an insulating substrate; Sequentially forming a gate insulating film, an a-Si layer, an N + a-Si layer, and an opaque metal film on the entire surface of the insulating substrate including the gate electrode; Etching the opaque metal film, the N + a-Si layer and the a-Si layer so that a semiconductor layer of a TFT is formed; Depositing a transparent metal film over the whole, and etching the transparent metal film to form a source electrode, a drain electrode, and a pixel electrode of the TFT; And forming a protective layer protecting the TFT by etching the organic layer and etching the organic layer, wherein the pixel electrode and the source electrode of the TFT are integrally formed.
본 발명에 따르면, TFT의 소오스/드레인 전극과 화소전극을 ITO 금속막으로 동시에 형성하기 때문에, 공정의 단순화는 물론, 제조 단가를 절감시킬 수 있다.According to the present invention, since the source / drain electrodes and the pixel electrodes of the TFT are simultaneously formed with the ITO metal film, the manufacturing cost can be reduced as well as the simplification of the process.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 TFT LCD의 하부기판 제조방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.2A to 2D are cross-sectional views illustrating a method of manufacturing a lower substrate of a TFT LCD according to an exemplary embodiment of the present invention.
우선, 도 2a에 도시된 바와 같이, 절연기판, 예컨데, 유리기판(11) 상에 게이트용 도전막을 증착하고, 상기 게이트용 도전막에 대한 1차 식각 공정을 수행하여 유리기판(11)의 적소에 게이트 전극(12) 및 스토리지 전극(도시안됨)을 형성한다. 그런 다음, 게이트 전극(12)과 이후에 형성될 소오스/드레인 전극간의 전기적 분리를 위하여, 유리기판(11)의 전면 상에 게이트 절연막(13)을 증착하고, 상기 게이트 절연막(13) 상에 a-Si층(14), N+a-Si층(15), 및 불투명 금속막(16)을 순차적으로 증착한다. 여기서, 불투명 금속막(16)은 통상 전극의 재질로 사용되는 금속막, 예컨데, 알루미늄막이다. 또한, N+a-Si층(15)은 a-Si층(14)과 불투명 금속막(16)간의 접촉 특성을 향상시키기 위한 층이다.First, as shown in FIG. 2A, a gate conductive film is deposited on an insulating substrate, for example, the glass substrate 11, and a primary etching process is performed on the gate conductive film to appropriately position the glass substrate 11. A gate electrode 12 and a storage electrode (not shown) are formed on the substrate. Then, a gate insulating film 13 is deposited on the entire surface of the glass substrate 11 for electrical separation between the gate electrode 12 and the source / drain electrodes to be formed later, and a on the gate insulating film 13 -Si layer 14, N + a-Si layer 15, and opaque metal film 16 are sequentially deposited. Here, the opaque metal film 16 is a metal film usually used as a material of an electrode, for example, an aluminum film. In addition, the N + a-Si layer 15 is a layer for improving the contact property between the a-Si layer 14 and the opaque metal film 16.
다음으로, 도 2b에 도시된 바와 같이, 2차 식각 공정을 통해 불투명 금속막(16), N+a-Si층(15) 및 a-Si층(14)을 식각하여, TFT의 반도체층(14a)을 형성한다.Next, as shown in FIG. 2B, the opaque metal film 16, the N + a-Si layer 15, and the a-Si layer 14 are etched through the secondary etching process to form a semiconductor layer of the TFT ( 14a).
이어서, 도 2c에 도시된 바와 같이, 전체 상부에 투명 금속막, 예컨데, ITO 금속막을 증착하고, 상기 ITO 금속막에 대한 3차 식각 공정을 수행하여 TFT의 소오스/드레인 전극(17a, 17b)과 화소전극(18)을 동시에 형성한다. 이때, TFT의 소오스 전극(17a)과 화소전극(18)은 일체형으로 형성된다.Subsequently, as shown in FIG. 2C, a transparent metal film, for example, an ITO metal film is deposited on the entire surface, and a third etching process is performed on the ITO metal film to perform source / drain electrodes 17a and 17b of the TFT. The pixel electrode 18 is formed at the same time. At this time, the source electrode 17a and the pixel electrode 18 of the TFT are integrally formed.
한편, TFT의 소오스/드레인 전극(17a, 17b)을 ITO 금속막으로만으로 형성할 경우에는 상기 ITO 금속막이 저항 높은 것에 기인하여, 구동 속도의 감소를 초래하게 된다. 따라서, TFT LCD의 구동 속도가 감소되는 것을 방지하기 위하여, 본 발명의 실시예에서는 ITO 금속막의 증착 이전에, 통상의 전극 재질로 사용되는 알루미늄막과 같은 불투명 금속막을 미리 형성하여, 불투명 금속막과 ITO 금속막의 적층 구조로 소오스/드레인 전극(17a, 17b)이 형성되도록 함으로써, 상기한 구동 속도의 감소를 방지한다. 또한, 도시하지는 않았으나, 데이터 라인의 경우도 적층 구조로 형성한다.On the other hand, when the source / drain electrodes 17a and 17b of the TFT are formed only of the ITO metal film, the ITO metal film is high in resistance, resulting in a decrease in driving speed. Therefore, in order to prevent the driving speed of the TFT LCD from decreasing, in the embodiment of the present invention, before the deposition of the ITO metal film, an opaque metal film such as an aluminum film used as a conventional electrode material is formed in advance, so that The source / drain electrodes 17a and 17b are formed in a laminated structure of the ITO metal film, thereby preventing the above-mentioned reduction in driving speed. Although not shown, data lines are also formed in a stacked structure.
다음으로, 도 2d에 도시된 바와 같이, TFT 및 화소전극(18)이 형성된 유리기판(11)의 전면 상에 폴리이미드막과 같은 유기막을 증착하고, 상기 유기막에 대한 4차 식각 공정을 수행하여 액정층으로부터 TFT를 보호하기 위한 보호층(19)을 형성한다. 이때, 4차 식각 공정시에는, 도시되지는 않았으나, 회로부와 연결될 전극패드 부분도 함께 노출시킨다.Next, as shown in FIG. 2D, an organic film, such as a polyimide film, is deposited on the entire surface of the glass substrate 11 on which the TFT and the pixel electrode 18 are formed, and a fourth etching process is performed on the organic film. Thus, the protective layer 19 for protecting the TFT from the liquid crystal layer is formed. In this case, in the fourth etching process, although not shown, the electrode pad portion to be connected to the circuit unit is also exposed.
이상에서와 같이, 본 발명은 4매의 식각 마스크를 사용하여 TFT LCD의 하부기판을 제작할 수 있기 때문에, 종래 방법에 비해 공정의 단순화를 얻을 수 있고, 아울러, TFT LCD의 제조 단가를 낮출 수 있다.As described above, since the lower substrate of the TFT LCD can be manufactured using four etching masks, the process can be simplified compared with the conventional method, and the manufacturing cost of the TFT LCD can be lowered. .
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (3)
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| KR1019980061864A KR20000045306A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating tft lcd device |
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| KR1019980061864A KR20000045306A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating tft lcd device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100446384B1 (en) * | 2001-05-31 | 2004-09-01 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing of tft array |
| KR100744449B1 (en) * | 2000-03-13 | 2007-08-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
| US7781759B2 (en) | 2005-11-17 | 2010-08-24 | Samsung Electronics Co., Ltd. | Display device and method for manufacturing the same |
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| JPH0695149A (en) * | 1992-09-11 | 1994-04-08 | Sharp Corp | Active matrix substrate and its production |
| JPH08262492A (en) * | 1995-03-27 | 1996-10-11 | Toshiba Corp | Liquid crystal display device |
| KR19980072230A (en) * | 1997-03-03 | 1998-11-05 | 김광호 | Method of manufacturing thin film transistor |
| KR100237673B1 (en) * | 1996-05-30 | 2000-01-15 | 윤종용 | Liquid crystal display device and manufacturing method |
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| JPH0695149A (en) * | 1992-09-11 | 1994-04-08 | Sharp Corp | Active matrix substrate and its production |
| JPH08262492A (en) * | 1995-03-27 | 1996-10-11 | Toshiba Corp | Liquid crystal display device |
| KR100237673B1 (en) * | 1996-05-30 | 2000-01-15 | 윤종용 | Liquid crystal display device and manufacturing method |
| KR19980072230A (en) * | 1997-03-03 | 1998-11-05 | 김광호 | Method of manufacturing thin film transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100744449B1 (en) * | 2000-03-13 | 2007-08-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
| KR100744441B1 (en) * | 2000-03-13 | 2007-08-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
| KR100446384B1 (en) * | 2001-05-31 | 2004-09-01 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing of tft array |
| US7781759B2 (en) | 2005-11-17 | 2010-08-24 | Samsung Electronics Co., Ltd. | Display device and method for manufacturing the same |
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