KR100375734B1 - Method of manufacturing TFT array substrate - Google Patents
Method of manufacturing TFT array substrate Download PDFInfo
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- KR100375734B1 KR100375734B1 KR10-1999-0023745A KR19990023745A KR100375734B1 KR 100375734 B1 KR100375734 B1 KR 100375734B1 KR 19990023745 A KR19990023745 A KR 19990023745A KR 100375734 B1 KR100375734 B1 KR 100375734B1
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- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 34
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 230000001681 protective effect Effects 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 claims abstract 4
- 230000007547 defect Effects 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 50
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical class N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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Abstract
본 발명은 ITO 에천트에 의한 데이터 라인의 오픈 불량을 방지하면서 공정 단순화 및 비용 절감을 이룰 수 있는 티에프티 어레이 기판의 제조방법을 개시하며, 개시된 본 발명의 방법은, 유리기판 상에 게이트용 금속막을 증착하는 단계; 상기 게이트용 금속막에 대한 제1식각 공정을 수행하여 게이트 전극을 형성하는 단계; 상기 게이트 전극을 덮도록 상기 유리기판의 전면 상에 게이트 절연막을 증착하는 단계; 상기 게이트 절연막 상에 a-Si층, n+a-Si층 및 소오스/드레인 전극용 금속막을 차례로 증착하는 단계; 상기 소오스/드레인 전극용 금속막과 n+a-Si층 및 a-Si층에 대한 제2식각 공정을 수행하여 상기 a-Si층으로 이루어진 반도체층을 형성하는 단계; 상기 기판 결과물 상에 ITO 금속막을 증착하는 단계; 상기 ITO 금속막과 식각된 소오스/드레인 전극용 금속막 및 n+a-Si층에 대한 제3식각 공정을 수행하여 화소전극을 형성함과 동시에 소오스/드레인 전극 및 오믹층을 형성하는 단계; 상기 단계까지의 기판 결과물 상에 보호막을 증착하는 단계; 및 상기 보호막에 대한 제4식각 공정을 수행하여 보호막을 기판의 일부분 상에만 잔류시키는 단계를 포함한다.The present invention discloses a method for manufacturing a TFT array substrate which can achieve a process simplification and a cost reduction while preventing an open defect of a data line by an ITO etchant, and the disclosed method of the present invention provides a method for manufacturing a gate metal on a glass substrate. Depositing a film; Forming a gate electrode by performing a first etching process on the gate metal film; Depositing a gate insulating film on an entire surface of the glass substrate to cover the gate electrode; Sequentially depositing an a-Si layer, an n + a-Si layer, and a metal film for source / drain electrodes on the gate insulating film; Forming a semiconductor layer including the a-Si layer by performing a second etching process on the metal layer for the source / drain electrode, the n + a-Si layer, and the a-Si layer; Depositing an ITO metal film on the substrate resultant; Forming a pixel electrode and forming a source / drain electrode and an ohmic layer by performing a third etching process on the source / drain electrode metal film and the n + a-Si layer etched with the ITO metal film; Depositing a protective film on the substrate resultant up to this step; And performing a fourth etching process on the passivation layer to leave the passivation layer only on a portion of the substrate.
Description
본 발명은 박막 트랜지스터 액정표시소자에 관한 것으로, 특히, 공정 단계를 감소시키기 위한 티에프티 어레이 기판(TFT Array substrate)의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor liquid crystal display devices, and more particularly, to a method of manufacturing a TFT array substrate for reducing process steps.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 각 화소의 구동을 독립적으로 제어하기 위한 스위칭 소자로서 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합하다는 잇점 때문에, CRT에 필적할만한 화면의 고화질화 및 대형화, 컬러화 등을 실현하는데 크게 기여하고 있다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, a TFT LCD equipped with a thin film transistor (TFT) as a switching element for independently controlling the driving of each pixel is comparable to a CRT because of its advantages of high-speed response characteristics and its suitability for high pixel numbers. It is greatly contributing to the realization of high quality screen, large size, and color.
이러한 TFT LCD는 개략적으로 TFT 및 화소전극이 형성된 TFT 어레이 기판과 컬러필터 및 상대전극이 형성된 컬러필터 기판, 및 상기 기판들 사이에 개재되는 액정층을 포함하여 이루어진다.Such a TFT LCD generally includes a TFT array substrate on which TFTs and pixel electrodes are formed, a color filter substrate on which color filters and counter electrodes are formed, and a liquid crystal layer interposed between the substrates.
한편, 상기와 같은 구조의 TFT LCD를 제조함에 있어서, TFT 어레이 기판의 제조 공정수, 즉, 식각 마스크의 수를 감소시키는 것은 매우 중요하다. 이것은 제조 비용을 낮추기 위한 것으로서, 현 시점에서는 5 마스크 공정이 제안되고 있다.On the other hand, in manufacturing a TFT LCD having the above structure, it is very important to reduce the number of manufacturing steps of the TFT array substrate, that is, the number of etching masks. This is to lower the manufacturing cost, and a five mask process is proposed at this time.
도 1a 내지 도 1d는 5 마스크 공정을 이용한 종래 기술에 따른 TFT 어레이 기판의 제조방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.1A to 1D are cross-sectional views illustrating a method of manufacturing a TFT array substrate according to the related art using a five mask process, which will be described below.
도 1a를 참조하면, 절연기판, 즉, 유리기판(1) 상에 게이트용 금속막을 증착하고, 이어서, 제1식각 마스크를 이용한 식각 공정으로 상기 게이트용 금속막을 패터닝하여 게이트 전극(2)을 형성한다. 그런다음, 상기 게이트 전극(2)이 덮혀지도록 유리기판(1)의 전면 상에 게이트 절연막(3)을 도포한다.Referring to FIG. 1A, a gate metal film is deposited on an insulating substrate, that is, a glass substrate 1, and then the gate metal film is patterned by an etching process using a first etching mask to form a gate electrode 2. do. Then, the gate insulating film 3 is coated on the entire surface of the glass substrate 1 so that the gate electrode 2 is covered.
도 1b를 참조하면, 게이트 절연막(3) 상에 도핑되지 않은 비정질실리콘층(이하, a-Si층 이라 칭함)과 도핑된 비정질실리콘층(이하, n+a-Si층이라 칭함)을 차례로 도포한다. 그런다음, 제2식각 마스크를 이용한 식각 공정으로 상기 n+a-Si층과 a-Si층을 식각하여 TFT의 반도체층(4)을 형성한다.Referring to FIG. 1B, an undoped amorphous silicon layer (hereinafter referred to as an a-Si layer) and a doped amorphous silicon layer (hereinafter referred to as an n + a-Si layer) are sequentially applied on the gate insulating film 3. do. Then, the n + a-Si layer and the a-Si layer are etched by an etching process using a second etching mask to form a semiconductor layer 4 of the TFT.
도 1c를 참조하면, 반도체층(4)이 형성된 결과물의 상부에 소오스/드레인 전극을 형성하기 위한 금속막을 형성하고, 이어서, 제3식각 마스크를 이용한 식각 공정으로 상기 금속막과 n+a-Si층을 연속적으로 식각하여 소오스/드레인 전극(6a, 6b) 및 오믹층(5)을 형성하며, 이 결과로서, TFT를 형성한다.Referring to FIG. 1C, a metal film for forming a source / drain electrode is formed on an upper portion of the resultant on which the semiconductor layer 4 is formed. Then, the metal film and n + a-Si are etched by an etching process using a third etching mask. The layer is continuously etched to form source / drain electrodes 6a and 6b and an ohmic layer 5, as a result of which a TFT is formed.
도 1d를 참조하면, TFT를 보호하기 위하여, 상기 결과물의 상부에 보호막(7)을 형성하고, 이어서, 제4식각 마스크를 이용한 식각 공정으로 상기 보호막(7)에 TFT의 소오스 전극(6a)을 노출시키는 콘택홀(C)을 형성한다. 그리고나서, 보호막(7) 상에 투명 금속막, 예컨데, ITO 금속막을 증착하고, 제5식각 마스크를 이용한 식각 공정으로 상기 ITO 금속막을 식각하여, TFT의 소오스 전극(6a)과 콘택되는 화소전극(8)을 형성한다.Referring to FIG. 1D, in order to protect the TFT, a protective film 7 is formed on the resultant, and then, the source electrode 6a of the TFT is placed on the protective film 7 by an etching process using a fourth etching mask. The contact hole C to be exposed is formed. Then, a transparent metal film, for example, an ITO metal film, is deposited on the protective film 7, and the ITO metal film is etched by an etching process using a fifth etching mask to contact the source electrode 6a of the TFT ( 8) form.
그러나, 상기와 같은 종래 기술에 따른 TFT 어레이 기판의 제조방법은, 5매의 식각 마스크를 이용하기 때문에, 통상, 6매 또는 7매 정도의 식각 마스크를 이용하는 제조 공정에 비해서는 그 공정이 단순하고, 특히, 제조비용을 절감시킬 수 있지만, 화소전극을 형성하기 위한 ITO 금속막의 식각시에, 식각액, 즉, ITO 에천트에 의해, 소오스/드레인 전극을 포함한 데이터 라인의 오픈과 같은 불량이 발생되는 문제점이 있다.However, since the TFT array substrate manufacturing method according to the prior art as described above uses five etching masks, the process is generally simpler than the manufacturing process using six or seven etching masks. In particular, although the manufacturing cost can be reduced, a defect such as opening of a data line including a source / drain electrode is generated by the etching solution, that is, the ITO etchant, during the etching of the ITO metal film for forming the pixel electrode. There is a problem.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 데이터 오픈과 같은 불량을 방지함과 동시에, 식각 공정 수를 더욱 감소시킬 수 있는 TFT 어레이 기판의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to provide a method of manufacturing a TFT array substrate that can prevent the defects such as data open, and further reduce the number of etching process, the object is have.
도 1a 내지 도 1d는 종래 기술에 따른 티에프이 어레이 기판의 제조방법을 설명하기 위한 공정 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a TFT array substrate according to the related art.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 티에프티 어레이 기판의 제조방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a TFT array substrate according to an exemplary embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 유리기판 12 : 게이트 전극11 glass substrate 12 gate electrode
13 : 게이트 절연막 14 : a-Si층13 gate insulating film 14 a-Si layer
15 : n+a-Si층 15a : 오믹층15: n + a-Si layer 15a: ohmic layer
16 : 소오스/드레인 전극용 금속막16: metal film for source / drain electrodes
16a : 소오스/드레인 전극 17 : 화소전극16a: source / drain electrode 17: pixel electrode
18 : 보호막 20 : 박막 트랜지스터18: protective film 20: thin film transistor
상기와 같은 목적을 달성하기 위하여, 본 발명은, 유리기판 상에 게이트용 금속막을 증착하는 단계; 상기 게이트용 금속막에 대한 제1식각 공정을 수행하여 게이트 전극을 형성하는 단계; 상기 게이트 전극을 덮도록 상기 유리기판의 전면 상에 게이트 절연막을 증착하는 단계; 상기 게이트 절연막 상에 a-Si층, n+a-Si층 및 소오스/드레인 전극용 금속막을 차례로 증착하는 단계; 상기 소오스/드레인 전극용 금속막과 n+a-Si층 및 a-Si층에 대한 제2식각 공정을 수행하여 상기 a-Si층으로 이루어진 반도체층을 형성하는 단계; 상기 기판 결과물 상에 ITO 금속막을 증착하는 단계; 상기 ITO 금속막과 식각된 소오스/드레인 전극용 금속막 및 n+a-Si층에 대한 제3식각 공정을 수행하여 화소전극을 형성함과 동시에 소오스/드레인 전극 및 오믹층을 형성하는 단계; 상기 단계까지의 기판 결과물 상에 보호막을 증착하는 단계; 및 상기 보호막에 대한 제4식각 공정을 수행하여 보호막을 기판의 일부분 상에만 잔류시키는 단계를 포함하는 TFT 어레이 기판의 제조방법을 제공한다.In order to achieve the above object, the present invention, the step of depositing a metal film for the gate on a glass substrate; Forming a gate electrode by performing a first etching process on the gate metal film; Depositing a gate insulating film on an entire surface of the glass substrate to cover the gate electrode; Sequentially depositing an a-Si layer, an n + a-Si layer, and a metal film for source / drain electrodes on the gate insulating film; Forming a semiconductor layer including the a-Si layer by performing a second etching process on the metal layer for the source / drain electrode, the n + a-Si layer, and the a-Si layer; Depositing an ITO metal film on the substrate resultant; Forming a pixel electrode and forming a source / drain electrode and an ohmic layer by performing a third etching process on the source / drain electrode metal film and the n + a-Si layer etched with the ITO metal film; Depositing a protective film on the substrate resultant up to this step; And performing a fourth etching process on the protective film to leave the protective film only on a portion of the substrate.
본 발명에 따르면, ITO 금속막으로 이루어진 화소전극의 형성을 소오스/드레인 전극 및 오믹층의 형성과 동시에 수행하기 때문에 ITO 에천트에 의한 데이터 라인의 오픈을 방지할 수 있으며, 아울러, 식각 공정 수를 감소시킬 수 있다.(실시예)According to the present invention, since the pixel electrode made of the ITO metal film is formed at the same time as the source / drain electrode and the ohmic layer, the opening of the data line by the ITO etchant can be prevented and the number of etching processes can be prevented. Can be reduced.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 TFT 어레이 기판의 제조방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.2A through 2D are cross-sectional views illustrating a method of manufacturing a TFT array substrate according to an exemplary embodiment of the present invention.
우선, 도 2a에 도시된 바와 같이, 절연기판, 예컨데, 유리기판(11) 상에 게이트용 금속막을 증착하고, 상기 게이트용 금속막에 대한 제1식각 공정을 수행하여 유리기판(11) 상에 게이트 전극(12)을 형성한다.First, as shown in FIG. 2A, a gate metal film is deposited on an insulating substrate, for example, the glass substrate 11, and a first etching process is performed on the gate metal film. The gate electrode 12 is formed.
그 다음, 도 2b에 도시된 바와 같이, 게이트 전극(12)과 이후에 형성될 소오스/드레인 전극을 포함한 데이터 라인간의 전기적 분리를 위하여 게이트 전극(12)이 형성된 유리기판(11)의 전면 상에 게이트 절연막(13)을 증착하고, 이어서, 상기 게이트 절연막(13) 상에 a-Si층(14), n+a-Si층(15) 및 소오스/드레인 전극용 금속막(16)을 차례로 증착한다. 그런다음, 소오스/드레인 전극용 금속막(16)과 n+a-Si층(15) 및 a-Si층(14)에 대한 제2식각 공정을 수행하여 상기한 적층물의 최하부에 상기 a-Si층(14)으로 이루어진 반도체층을 형성한다. 여기서, 도시하지는 않았으나, 상기 게이트 절연막(13)은 실리콘질산화막과 실리콘질화막의 적층 구조로 형성하는 것이 바람직하다.Next, as shown in FIG. 2B, on the front surface of the glass substrate 11 on which the gate electrode 12 is formed for electrical separation between the gate electrode 12 and the data line including a source / drain electrode to be formed later. A gate insulating film 13 is deposited, and then an a-Si layer 14, an n + a-Si layer 15, and a metal film 16 for source / drain electrodes are sequentially deposited on the gate insulating film 13. do. Then, a second etching process is performed on the metal film 16 for the source / drain electrodes, the n + a-Si layer 15 and the a-Si layer 14, and the a-Si is formed at the bottom of the laminate. The semiconductor layer consisting of the layer 14 is formed. Although not shown, the gate insulating layer 13 may be formed in a stacked structure of a silicon nitride oxide film and a silicon nitride film.
다음으로, 도 2c에 도시된 바와 같이, 상기 결과물의 상부에 ITO 금속막을 증착한다. 그런다음, 상기 ITO 금속막과 소오스/드레인용 금속막 및 n+a-Si층에 대한 제3식각 공정을 수행하여 ITO 금속막으로 이루어진 화소전극(17)을 형성하고, 아울러, 소오스/드레인 전극(16a)을 형성하며, n+a-Si층으로 이루어진 오믹층(15a)을 형성한다. 이 결과, 유리기판(11) 상에 TFT(20)가 형성된다.Next, as shown in Figure 2c, an ITO metal film is deposited on top of the resultant. Thereafter, a third etching process is performed on the ITO metal film, the source / drain metal film, and the n + a-Si layer to form a pixel electrode 17 made of the ITO metal film, and at the same time, the source / drain electrode (16a) is formed and an ohmic layer (15a) composed of n + a-Si layers is formed. As a result, the TFT 20 is formed on the glass substrate 11.
한편, 본 발명의 실시예에서, ITO 금속막으로된 화소전극(17)은 소오스/드레인 전극(16a)과 직접 콘택된다. 따라서, 종래에는 소오스/드레인 전극을 포함한 데이터 라인을 형성한 후에, ITO 금속막에 대한 식각 공정을 수행하기 때문에, ITO 에천트에 의한 데이터 라인의 오픈이 발생되지만, 본 발명의 실시예에서는 ITO 금속막과 소오스/드레인 전극용 금속막에 대한 식각 공정을 동시에 수행하기 때문에, ITO 에천트에 의한 데이터 라인의 오픈 결함을 방지할 수 있게 된다.On the other hand, in the embodiment of the present invention, the pixel electrode 17 made of the ITO metal film is in direct contact with the source / drain electrode 16a. Thus, since the etching process for the ITO metal film is conventionally performed after the data line including the source / drain electrode is formed, opening of the data line by the ITO etchant occurs, but in the embodiment of the present invention, the ITO metal Since the etching process is performed on the film and the metal film for the source / drain electrodes at the same time, it is possible to prevent the open defect of the data line by the ITO etchant.
계속해서, 도 2d에 도시된 바와 같이, 전체 상부에 TFT(20)를 보호하기 위한 보호막(18)을 도포하고, 이러한 보호막(18)이 TFT(20) 상에만 잔류되도록, 상기 보호막(18)에 대한 제4식각 공정을 수행하고, 이 결과로서, 본 발명에 따른 TFT 어레이 기판의 제조를 완성한다.Subsequently, as shown in FIG. 2D, a protective film 18 for protecting the TFT 20 is applied to the entire upper portion, and the protective film 18 is such that the protective film 18 remains only on the TFT 20. Performing a fourth etching process, thereby completing the fabrication of the TFT array substrate according to the invention.
본 발명의 실시예에 따른 TFT 어레이 기판은 4회의 식각 공정에 의해 제작되기 때문에, 그에 따른 식각 마스크의 수도 감소된다. 따라서, 종래 보다 식각 공정의 단순화는 물론, 식각 마스크의 수도 감소시킬 수 있다.Since the TFT array substrate according to the embodiment of the present invention is manufactured by four etching processes, the number of etching masks accordingly is reduced. Therefore, the etching process may be simplified and the number of etching masks may be reduced.
또한, 탑 ITO 구조가 아닌, 탑 보호막의 구조를 채택하기 때문에, 화소전극을 형성하기 위한 ITO 금속막의 식각시에, 데이트 라인의 오픈과 같은 결함이 발생되는 것을 방지할 수 있고, 아울러, 종래에 비해 TFT의 보호가 더 안정적이다.In addition, since the structure of the top protective film is used instead of the top ITO structure, defects such as opening of the data line can be prevented from occurring during the etching of the ITO metal film for forming the pixel electrode. In comparison, the protection of TFT is more stable.
이상에서와 같이, 본 발명은 4매의 식각 마스크를 사용하여 TFT 어레이 기판을 제작할 수 있기 때문에, 종래 보다 제조공정의 단순화는 물론, 제조비용의 절감 효과를 얻을 수 있다.As described above, since the TFT array substrate can be manufactured using four etching masks, the present invention can simplify the manufacturing process and reduce the manufacturing cost.
또한, ITO 에천트로 인한 데이터 라인의 오픈을 방지할 수 있고, 아울러, 보호막이 최상부에 배치되도록 하기 때문에, TFT 어레이 기판의 신뢰성을 향상시킬 수 있다.In addition, since the opening of the data line due to the ITO etchant can be prevented, and the protective film is arranged at the top, the reliability of the TFT array substrate can be improved.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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