KR20000045281A - Output buffer enable circuit - Google Patents

Abstract

The present invention relates to an output buffer enable circuit of a semiconductor memory device capable of improving speed and preventing malfunction.

According to the present invention, an output buffer enable circuit of a semiconductor memory device that generates an enable signal of an output buffer and provides an output signal of a sense amplifier as an external load, wherein the power supply voltage is supplied from an external device according to a chip select signal applied from the outside. A power supply level detector for detecting a level of the power generator and generating first and second detection signals in which phases are inverted from each other; When a high power supply voltage is applied, an output buffer and an output buffer enable signal are generated to the output buffer by the output signal and the first input signal and the second input signal according to the first detection signal of the power level detector. And an enable signal generator for inputting a second input signal and a third input signal according to the second detection signal of the power level detection unit to generate an output buffer enable signal to the output buffer.

Description

Output buffer enable circuit

The present invention relates to an output buffer enable circuit of a semiconductor memory device, and more particularly, to an output buffer enable circuit capable of improving processing speed and preventing malfunction.

An operation of outputting data from a general semiconductor memory device (not shown) will be described with reference to the waveform diagram of FIG. 1.

When the address signal ADD is applied through the input buffer as shown in FIG. 1A from the outside, the address transition detector detects a change in the address applied through the input buffer and generates an address transition detection pulse ADT as shown in FIG. 1B. From the address transition detection pulse ADT, a sense amplifier enable signal SAE and an output buffer enable signal POE such as those shown in FIGS. 1E and 1G are generated. Accordingly, the sense amplifier senses data from the memory cell. Amplified to generate output data as shown in Figure 1F, the output buffer outputs the data from the sense amplifier by the output buffer enable signal (POE) as shown in Figure 1H.

The output buffer circuit of the semiconductor memory device is a circuit for outputting the output signal from the sense amplifier to an external load as described above, and is output from the sense amplifier by an output buffer enable signal (POE) generated from the output buffer enable circuit. Output the applied signal. The conventional output buffer enable circuit is a circuit for generating the output buffer enable signal POE by combining the address transition detection signal ADT and the output enable signal / OE.

Referring to FIG. 2, a conventional output buffer enable circuit of a semiconductor memory device includes a delay element 35 for inverting a delay of an address transition detection signal, an output signal of the delay element 35, and an address transition detection signal ( A NOA gate 31 having ATD as two inputs, an inversion gate 32 for inverting the NOA gate 31, an output of the inversion gate 32, and an address transition detection signal ATD. A noble gate 33 serving as an input and a noble gate 34 having two outputs of the output and the output enable signal / OE of the noble gate 33 are provided.

In the conventional output buffer enable circuit, when the address transition detection signal ATD is generated as shown in FIG. 3C according to the change of the address signal applied through the input buffer, the address transition detection signal ADT is inputted and then transmitted through a delay element. After inverting the delay, the inverted delayed signal and the address transition detection signal (ATD) are logically combined through the logic gate to expand the width of the pulse, and then in combination with the output enable signal (/ OE) through the other logic gate. As shown in FIG. 3D, the output buffer enable signal POE was generated.

When the output buffer enable circuit operates normally to generate the output buffer enable signal POE, the output buffer enable signal POE is disabled for a predetermined time t as shown in FIG. The buffer 20 is disabled so that its output is in a high impedance (Hi-Z) state. Subsequently, when the sensing section in which the sensing amplifier 10 senses and amplifies the data SAi and / SAi applied from the memory cell is terminated, the sensing amplifier 10 is enabled to enable the output buffer 20. Therefore, the output buffer 20 outputs predetermined data as shown in FIG. 1H.

However, in the conventional output buffer enable circuit, the output buffer is operated because the output buffer enable signal is generated by the address transition detection signal and the output buffer is controlled even though the processing speed is improved compared to the low power supply voltage at the high power supply voltage. The peak current at the moment causes the power VCC and GND to become unstable as shown in FIG. 3B.

A malfunction of the address input buffer operating at the same power supply voltage as the output buffer occurs, thereby causing an address transition to generate an unwanted address transition detection signal as shown in FIG. 3C. The output buffer enable signal POE generated according to the address transition detection signal is also generated as shown in FIG. 3D, which causes a problem in that the output buffer malfunctions and cannot output desired data accurately. That is, by disabling the output buffer to make the output high-impedance, there is a problem that the processing speed is lowered or the semiconductor memory device malfunctions.

The present invention is to solve the problems of the prior art as described above, a semiconductor that can improve the malfunction and processing speed by generating a signal that can enable the output buffer at low power supply voltage and high power supply voltage separately It is an object of the present invention to provide an output buffer enable circuit of a memory device.

Another object of the present invention is to control the output buffer by the address transition detection pulse at the low power supply voltage, and to detect the output of the sense amplifier at the high power supply voltage, and to control the output buffer by the combination of the detection signal and the sense amplifier enable signal. The present invention provides an output buffer enable circuit for generating an output buffer enable signal.

Another object of the present invention is to control the output buffer by the address transition detection signal at the low power supply voltage, and to detect the output of the sense amplifier at the high power supply voltage and to output the output buffer by the combination of the detected signal and the word line driving signal. An output buffer enable circuit for generating an output buffer enable signal to control is provided.

It is still another object of the present invention to control an output buffer by an address transition detection signal at a low power supply voltage, and to output a buffer for output buffer enable signal for controlling an output buffer by delaying a sense amplifier enable signal at a high power supply voltage. It is to provide an enable circuit.

1A to 1H are operational waveform diagrams of a general semiconductor memory device;

2 is an operation waveform diagram of an output buffer enable circuit of a conventional semiconductor memory device;

3A to 3E are operational waveform diagrams of an output buffer enable circuit of the conventional semiconductor memory device of FIG.

4A to 4C are operational waveform diagrams of an output buffer enable circuit of the semiconductor memory device of the present invention;

5 is a block diagram of an output buffer enable circuit of a semiconductor memory device according to an embodiment of the present invention;

6 is a detailed view of an output buffer enable circuit of a semiconductor memory device according to one embodiment of the present invention;

7 is a detailed view of an output buffer enable circuit of a semiconductor memory device according to another embodiment of the present invention;

8 is a detailed view of an output buffer enable circuit of a semiconductor memory device according to another embodiment of the present invention;

(Explanation of symbols for the main parts of the drawing)

100: detection amplifier 200: output buffer

300: precharge unit 400: power level detection unit

500: enable signal generator 511, 611, 711, 721: delay means

510 and 520: first and second signal generator

512, 514, 515, 521, 523, 524: Noah gate

413, 414, 513, 522, 613, 622, 713, 722: inverted gate

311-312, 313, 411, 516, 517, 525, 526: PMOS transistors

101, 518, 519, 618, 619, 718, 719: NMOS transistors

In order to achieve the object of the present invention as described above, the present invention provides an output buffer enable circuit of a semiconductor memory device for generating an enable signal of an output buffer for providing an output signal of a sense amplifier to an external load, wherein A power level detector for detecting a level of a power supply voltage supplied from the outside according to an applied chip select signal and generating first and second detection signals whose phases are inverted from each other; When a high power supply voltage is applied, an output buffer and an output buffer enable signal are generated to the output buffer by the output signal and the first input signal and the second input signal according to the first detection signal of the power level detector. An output buffer enable circuit including an enable signal generator for inputting a second input signal and a third input signal according to the second detection signal of the power level detection unit to generate an output buffer enable signal to the output buffer; It is characterized by providing.

According to an embodiment of the present invention, the power level detection unit includes a MOS transistor to which the chip select signal is applied to a gate, a power supply voltage is applied to an external source, and a drain is connected to a node; A resistor coupled between the node and ground; A first inversion gate for inverting the potential of the node to generate a second detection signal to the enable signal generator; And a second inversion gate for inverting the output of the first inversion gate to generate a first detection signal to the enable signal generator. The first input signal is one of a sense amplifier enable signal or a word line driving signal applied from the outside, the second input signal is an output enable signal applied from the outside, and the third input signal is an address transition detection signal applied from the outside. to be.

According to an exemplary embodiment of the present invention, the enable signal generator inputs an output signal, a first input signal, and a second input signal from a sense amplifier according to a first detection signal from the power level detector to output a high power voltage. A first signal generator for generating a buffer enable signal to the output buffer; And a second signal generator for inputting a second input signal and a third input signal according to the second detection signal from the power level detection unit to generate an output buffer enable signal to the output buffer when a low power supply voltage is applied. It is done.

Detection means for detecting an output signal from the detection amplifier; And generating means for generating an output buffer enable signal for enabling the output buffer according to the detection signal generated from the detection means and the first and second detection signals of the power level detection unit. The detecting means includes: a first NAND gate having two input signals of the sense amplifier; An inversion gate for inverting the output of the first NAND gate; A second NAND gate having two inputs of the first input signal and the output signal of the inverted gate; And a NOR gate for generating a detection signal by using the output signal of the second NOR gate and the second input signal as two inputs. The generating means of the first signal generating section includes: first and second MOS transistors having an output signal of the Noah gate of the detecting means and a second detecting signal from the power supply level detecting section being applied to the gate, respectively, and connected in series between the power supply voltage and the node; The output signal of the NOR gate of the detection means and the first detection signal of the power level detection unit are respectively applied to a gate and are composed of third and fourth MOS transistors connected between ground and the node, and the output buffer is input through the node. Generates an enable signal.

According to an embodiment of the present invention, the second signal generator comprises: detection means for detecting an input of a third input signal; And generating means for generating an output buffer enable signal to the output buffer by the output signal of the detection means and the first and second detection signals of the power level detection unit. The detecting means includes delay means for inverting a delay of the third input signal; A first NOR gate having two inputs of the third input signal and the output signal of the delay means; An inverting gate for inverting the output signal of the first NOR gate; A second NOR gate having two output signals of the inverted gate and the third input signal; The NOR gate includes two output signals of the second NOR gate and a second input signal. The generating means of the second signal generator includes first and second MOS transistors having an output signal of the third NOR gate of the detecting means and a first detection signal of the power level detecting unit being applied to the gate and connected in series between the power supply voltage and the node. Wow; An output signal of the third NOA gate of the detection means and a second detection signal of the power level detection unit are respectively applied to the gate and are composed of third and fourth MOS transistors connected in series between the node and ground, and the output is performed through the node. And an output buffer enable signal for enabling the buffer.

In addition, the present invention provides an output buffer enable circuit of a semiconductor memory device that generates an enable signal of an output buffer to provide an output signal of a sense amplifier to an external load, and is supplied from an external device according to a chip select signal applied from the outside. A power supply level detecting unit for detecting a level of the power supply voltage and generating first and second detection signals whose phases are inverted from each other; When a high power supply voltage is applied, an output buffer enable signal is generated to the output buffer by a first input signal and a second input signal according to the first detection signal of the power supply level detection unit, and when the low power supply voltage is applied, the power supply level detection unit An output buffer enable circuit including an enable signal generator for generating an output buffer enable signal to the output buffer by inputting a second input signal and a third input signal according to a second detection signal.

According to another embodiment of the present invention, the first signal generator of the enable signal generator includes: detection means for detecting an output signal from the detection amplifier; And generating means for generating an output buffer enable signal for enabling the output buffer according to the detection signal generated from the detection means and the first and second detection signals of the power level detection unit. The detecting means includes delay means for delaying the first input signal; A first inversion gate for inverting the output of the delay means; A NAND gate having two inputs of the first input signal and the output signal of the first inverting gate; A second inversion gate for inverting an output signal of the NAND gate; The output signal of the second inverting gate and the second input signal are configured as two inputs, and a NOR gate generating a detection signal. The generating means includes: first and second MOS transistors having an output signal of the NOR gate of the detecting means and a second detection signal from the power supply level detecting unit being respectively applied to the gate and connected in series between the power supply voltage and the node; The output signal of the NOR gate of the detection means and the first detection signal of the power level detection unit are respectively applied to a gate and are composed of third and fourth MOS transistors connected between ground and the node, and the output buffer is input through the node. It is characterized by generating an enable signal.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of an output buffer enable circuit of a semiconductor memory device according to an embodiment of the present invention. FIG. 6 is a detailed circuit diagram of an output buffer enable circuit of the semiconductor memory device of FIG. 5. 5 and 6, the output buffer enable circuit of the semiconductor memory device of the present invention detects the level of the power supply voltage Vcc supplied from the outside according to the chip select signal / CS to detect the detection signal VDC. And detecting whether the output signals SAout and / SAout are generated from the power level detector 400 generating the inversion detection signal / VDC and the sense amplifier 100 when the high power voltage is applied. The output buffer enable signal POE is generated by the output detection signal, the first input signal and the second input signal according to the detection signal VDC from the 400, and the power level detection unit 400 when a low power supply voltage is applied. And an enable signal generator 500 for inputting a second input signal and a third input signal according to the inversion detection signal / VDC to generate an output buffer enable signal POE.

According to an embodiment of the present invention, the first input signal is a sense amplifier enable signal SAE applied from the outside, and the second input signal is an output enable signal / CS and a third input applied from the outside. The signal is an address transition detection signal ADT applied from the outside.

Referring to FIG. 6, in the output buffer enable circuit of the present invention, the power level detection unit 400 receives a chip select signal / CS applied from the outside to a gate and a power supply voltage Vcc to a source. The PMOS transistor 411 having a drain connected to the node N1, the resistor 412 connected between the node N1 and the ground, and the potential of the node N1 are inverted to generate an inversion detection signal / VDC. An inverted gate 413 generated by the enable signal generator 500 and an inverted gate generated by the output of the inverted gate 413 to generate a detection signal VDC to the enable signal generator 500. Consists of 414.

In the output buffer enable circuit of the present invention, the enable signal generator 500 outputs signals SAout and / SAout from the sense amplifier 100 according to the detection signal VDC from the power level detector 400. And a first signal generator 510 for inputting a first input signal and a second input signal to generate an output buffer enable signal POE to the output buffer 200 when a high power supply voltage is applied, and the power level detector. A second input signal and a third input signal are input according to the inversion detection signal / VDC from 400 to generate an output buffer enable signal POE to the output buffer 200 when a low power supply voltage is applied. The second signal generator 520 is included.

The first signal generator 510 of the enable signal generator 500 is a detection means for detecting the output signals SAout and / SAout from the sense amplifier 100 and outputs the sense amplifier 100. A NAND gate 521 having two signals SAout and / SAout as two inputs, an inverting gate 322 for inverting the output of the NAND gate 521, the sense amplifier enable signal SAE, and the NAND for generating a detection signal using the NAND gate 523 having two output signals of the inverted gate 322 and the input signal of the NAND gate 523 and the output enable signal / CS as two inputs. Gate 524.

The first signal generator 510 also outputs the output buffer according to the detection signal generated from the NOR gate 524 of the detection means and the detection signal VDC and the inverted detection signal / VDC of the power level detection unit 100. As a generating means for generating an output buffer enable signal (POE) for enabling (200), the output signal of the Noah gate 523 and the inverted detection signal (/ VDC) from the power level detection unit (100). PMOS transistors 525 and 526 connected to the gate and connected in series between the power supply voltage Vcc and the second node N2, the output signal of the NOR gate 523, and the power level detection unit 100, respectively. A detection signal is applied to the gate and includes NMOS transistors 527 and 528 connected in series between the node N2 and ground, respectively, and generates an output buffer enable signal POE through the second node N2.

The second signal generator 510 is provided with detection means for detecting an address transition detection signal, an output signal of the detection means, a detection signal (VDC) and an inversion detection signal (/ VDC) of the power level detection unit 400. By means of generating means for generating an output buffer enable signal POE to the output buffer 200.

The detection means of the second signal generator 520 includes delay means 511 for inverting the delay of the address transition detection signal ADT, and outputs the address transition detection signal ADT and the delay means 511. Noah gate 512 having a signal as two inputs, an inversion gate 513 for inverting the output signal of the noah gate 512, an output signal of the inversion gate 513, and the address transition detection signal ( A NOA gate 514 having two inputs of the ATD and a NOA gate 515 having two inputs of an output signal and an output enable signal / OE of the NOA gate 514 are provided.

The generating means of the second signal generator 520 is the output signal of the Noah gate 515 and the detection signal (VDC) of the power level detection unit 400 is applied to the gate, respectively, the power supply voltage (Vcc) and the node ( PMOS transistors 516 and 517 connected in series between N3), an output signal of the NOR gate 515 and an inverted detection signal / VDC of the power level detector 400 are respectively applied to a gate, and the node N3 is applied. NMOS transistors 518 and 519 connected in series between < RTI ID = 0.0 >

Referring to FIG. 6, reference numeral 300 denotes a precharge unit for precharging the output terminal of the sense amplifier 100 to a power supply voltage, and the PMOS transistors 311-313 to which the sense amplifier enable signal SAE is applied to a gate. )

The operation of the output buffer enable circuit according to the first embodiment of the present invention as described above will be described with reference to FIG.

When the sense amplifier enable signal SAE is disabled, the NMOS transistor 101 to which the sense amplifier enable signal SAE is applied to the gate is turned off to disable the sense amplifier 100. At this time, the PMOS transistors 311-313 of the precharge unit 300 are turned on to precharge the output terminal of the sense amplifier 100 to the power supply voltage Vcc.

When the sense amplifier enable signal SAE is enabled as shown in FIG. 4A, the NMOS transistor 101 is turned on so that the sense amplifier 100 is enabled and the PMOS transistors 311-313 of the precharge unit 300 are turned on. Is off. Accordingly, the sensing amplifier 100 senses and amplifies the input signals SAi and / SAi to generate the output signals SAout and / SAout to the output buffer 200.

At this time, the power level detection unit 400 is driven by the chip select signal / CS to detect the level of the power supply voltage supplied from the outside. When the low power supply voltage is applied, the node N1 becomes low level and is in a low state. The detection signal VDC and the high state inversion detection signal / VDC are generated through the inversion gates 413 and 414.

Low and high detection signals VDC and inverted detection signals / VDC of the power level detector 400 are applied to the first signal generator 510 and the second signal generator 520, respectively. The PMOS transistor 525 and the NMOS transistor 528 of the signal generator 510 are turned off, and the first signal generator 510 is disabled.

Meanwhile, the PMOS transistor 516 and the NMOS transistor 519 of the second signal generator 520 are turned on and enabled. Accordingly, the second signal generator 520 inputs an address transition detection signal ADT and an output enable signal / OE to delay means 511, logic gates 511-515, and MOS transistors 516-519. Through the output buffer enable signal (POE) is generated to the output buffer 200.

On the other hand, when the high power supply voltage is supplied from the outside, the power supply level detection unit 400 supplies a high state detection signal (/ VDC) and a low state inversion detection signal (/ VDC) of the enable signal generator 500. Generated by the first and second signal generators 510 and 520. Accordingly, the PMOS transistor 525 and the NMOS transistor 528 of the first signal generator 510 are turned on and enabled, and the PMOS transistor 516 and the NMOS transistor 519 of the second signal generator 520 are enabled. It is turned off and disabled.

The second signal generator 520 detects the generation of the output signals SAout and / SAout from the detection amplifier 100 through the NAND gate 521. That is, when the output stage is precharged, the output signals SAout and / SAout of the sense amplifier 100 are all high and their output is low, but the sense amplifier 100 is enabled and the output signal is Is generated, its output signals SAout and / SAout have different levels as shown in Fig. 4B, so that the output of the NAND gate 521 becomes high.

Accordingly, the first signal generator 510 detects an output time point of the output signals SAout and / SAout of the detection amplifier 100. At this time, when the output enable signal / OE is low, the output of the NOR gate 524 is turned low and the PMOS transistor 525 is turned on, so the first signal generator 510 outputs the output buffer as shown in FIG. 4C. The enable signal POE is generated.

Accordingly, the output buffer 200 remains enabled, and when the sense amplifier 100 is enabled, the output buffer 200 is disabled by the output buffer enable signal POE of FIG. 4C, and the sense amplifier 100 is enabled. When the sensor senses the data and generates its output signals SAout and / SAout, it is enabled again by the output buffer enable signal POE.

Here, the low power supply voltage and the high power supply voltage, when the power supply voltage Vcc is supplied from the outside, the power supply voltage has a swing width of Vcc ± 10%, the low power supply voltage (low Vcc) is a voltage of Vcc-10% High power supply voltage (high Vcc) means a voltage of Vcc + 10%.

According to the first embodiment of the present invention as described above, when the low power supply voltage is supplied, the address transition detection signal ADT and the output enable signal (/ OE) through the second signal generator 520 as in the prior art. ) Generates an output buffer enable signal POE for driving the output buffer 100. When the high power supply voltage is supplied, the output buffer 200 is connected through the first signal generator 510 by the output of the sense amplifier and the output enable signal / OE and the sense amplifier enable signal SAE. Generate an output buffer enable signal (POE) for enabling. Therefore, even when the address transition detection signal ADT is generated due to an unstable operation at a high power supply voltage, the output buffer is not disabled, but is disabled by the sense amplifier enable signal SAE, and the sense amplifier generates an output signal. I then enable it again.

7 shows a detailed view of an output buffer enable circuit according to a second embodiment of the present invention. The output buffer enable circuit according to the second embodiment of the present invention has the same configuration as the output buffer enable circuit according to the first embodiment. However, in the first embodiment, although the first signal generator 510 of the enable signal generator 500 generates the output buffer enable signal POE by the sense amplifier enable signal SAE, the second embodiment In an example, the first signal generator 510 of the enable signal generator 500 generates the output buffer enable signal POE by the word line driving signal PWL.

That is, in the second embodiment, the output buffer 200 is output by the output signals SAout and / SAout, the output enable signal / OE and the word line driving signal PWL of the sensing amplifier 100 when the high power supply voltage is supplied. Generates an output buffer enable signal (POE) for driving.

8 shows a detailed view of an output buffer enable circuit according to a third embodiment of the present invention. Referring to FIG. 8, the output buffer enable circuit according to the third embodiment of the present invention includes a power supply level detector 400 and an enable signal generator 500. The power level detection unit 400 has the same configuration as the output burr enable circuit according to the first embodiment. The enable signal generator 500 includes first and second signal generators 510 and 520, and the second signal generator 520 has the same configuration as that of the first embodiment.

However, the configuration of the first signal generator 510 is different. That is, the first signal generator 510 is a detection means, which includes a delay means 721 for delaying the sense amplifier enable signal SAE and an inversion for inverting the output of the delay means 721. NAND gate 723 having two inputs of the gate 722, the output signal of the inverted gate 722, and the sense amplifier enable signal SAE, and an inversion for inverting the output of the NAND gate 723. A gate 724 and a NOR gate having two inputs of the output and the output enable signal / OE of the inverted gate 724, and the signal generating means is the same as in the first embodiment.

Like the first embodiment, the output buffer enable circuit according to the second and third embodiments also detects the level of the power supply voltage supplied from the outside through the power supply level detection unit 400, and when the low power supply voltage is applied as a result of the detection. An output buffer enable signal POE is generated to the output buffer 200 according to the address transition detection signal ADT through a second signal generator 520, and a first signal is generated when a high power supply voltage is applied. The output buffer enable signal POE corresponding to the word line driving signal PWL or the sense amplifier enable signal SAE is generated through the unit 510 to the output buffer 200.

According to the output buffer enable circuit of the present invention as described above, it detects the power supply level supplied from the outside, generates an output buffer enable signal according to the address transition detection signal at the low power supply voltage, and detect amplifier in the high power supply voltage By generating the output buffer enable signal according to the enable signal or the word line drive signal, not only the malfunction caused by the instability of the power supply voltage due to the instantaneous peak current can be prevented, but also the influence on the noise can be reduced. There is an advantage to speed up.

Claims (21)

In the output buffer enable circuit of a semiconductor memory device for generating an enable signal of an output buffer, the output signal of the sense amplifier is supplied to an external load. A power level detection unit for detecting a level of a power supply voltage supplied from the outside according to a chip select signal applied from the outside to generate first and second detection signals having inverted phases; When a high power supply voltage is applied, an output buffer and an output buffer enable signal are generated to the output buffer by the output signal and the first input signal and the second input signal according to the first detection signal of the power level detector. And an enable signal generator for inputting a second input signal and a third input signal according to the second detection signal of the power level detector to generate an output buffer enable signal to the output buffer. Enable circuit. The method of claim 1, wherein the power level detection unit A MOS transistor having the chip select signal applied to a gate, a source voltage applied to an external source, and a drain connected to a node; A resistor coupled between the node and ground; A first inversion gate for inverting the potential of the node to generate a second detection signal to the enable signal generator; And a second inverting gate which inverts the output of the first inverting gate to generate a first detection signal to the enable signal generator. 3. The method of claim 2, wherein the first input signal is a sense amplifier enable signal applied from the outside, the second input signal is an output enable signal applied from the outside, and the third input signal is an address transition detection signal applied from the outside. Output buffer enable circuit, characterized in that. 3. The method of claim 2, wherein the first input signal is a word line driving signal applied from the outside, the second input signal is an output enable signal applied from the outside, and the third input signal is an address transition detection signal applied from the outside. Output buffer enable circuit. The method of claim 1, wherein the enable signal generator A first signal which generates an output buffer enable signal to the output buffer when a high power supply voltage is applied by inputting an output signal and a first input signal and a second input signal from a sense amplifier according to the first detection signal from the power level detector; A generator; And a second signal generator for inputting a second input signal and a third input signal according to the second detection signal from the power level detection unit to generate an output buffer enable signal to the output buffer when a low power supply voltage is applied. Output buffer enable circuit. The method of claim 5, wherein the first signal generator of the enable signal generator Detecting means for detecting an output signal from the sense amplifier; Output means for generating an output buffer enable signal for enabling the output buffer according to the detection signal generated from the detection means and the first and second detection signals of the power level detection unit Buffer enable circuit. The method of claim 6, wherein the detection means of the first signal generator A first NAND gate having two input signals of the sense amplifier; An inversion gate for inverting the output of the first NAND gate; A second NAND gate having two inputs of the first input signal and the output signal of the inverted gate; And a NOR gate generating a detection signal by using the output signal of the second NOR gate and the second input signal as two inputs. The method of claim 7, wherein the generating means of the first signal generator is First and second MOS transistors having an output signal of the NOR gate of the detection means and a second detection signal from the power supply level detector, respectively, connected in series between a power supply voltage and a node; The output signal of the NOR gate of the detection means and the first detection signal of the power level detection unit are respectively applied to a gate and are composed of third and fourth MOS transistors connected between ground and the node, and the output buffer is input through the node. An output buffer enable circuit for generating an enable signal. The method of claim 5, wherein the second signal generating unit Detecting means for detecting an input of a third input signal; And a generating means for generating an output buffer enable signal to said output buffer by the output signal of said detection means and the first and second detection signals of said power level detection part. The method of claim 9, wherein the detection means of the second signal generator Delay means for inverting a delay of the third input signal; A first NOR gate having two inputs of the third input signal and the output signal of the delay means; An inverting gate for inverting the output signal of the first NOR gate; A second NOR gate having two output signals of the inverted gate and the third input signal; An output buffer enable circuit comprising: a NOR gate having two output signals of the second NOR gate and a second input signal. The method of claim 10, wherein the generating means of the second signal generator First and second MOS transistors having an output signal of a third NOR gate of the detection means and a first detection signal of the power level detection unit respectively applied to a gate and connected in series between a power supply voltage and a node; An output signal of the third NOA gate of the detection means and a second detection signal of the power level detection unit are respectively applied to the gate and are composed of third and fourth MOS transistors connected in series between the node and ground, and the output is performed through the node. An output buffer enable circuit for generating an output buffer enable signal for enabling a buffer. In the output buffer enable circuit of a semiconductor memory device for generating an enable signal of an output buffer, the output signal of the sense amplifier is supplied to an external load. A power level detection unit for detecting a level of a power supply voltage supplied from the outside according to a chip select signal applied from the outside to generate first and second detection signals having inverted phases; When a high power supply voltage is applied, an output buffer enable signal is generated to the output buffer by a first input signal and a second input signal according to the first detection signal of the power supply level detection unit, and when the low power supply voltage is applied, the power supply level detection unit And an enable signal generator for inputting a second input signal and a third input signal according to a second detection signal to generate an output buffer enable signal to the output buffer. The method of claim 12, wherein the power level detection unit A MOS transistor having the chip select signal applied to a gate, a source voltage applied to an external source, and a drain connected to a node; A resistor coupled between the node and ground; A first inversion gate for inverting the potential of the node to generate a second detection signal to the enable signal generator; And a second inverting gate which inverts the output of the first inverting gate to generate a first detection signal to the enable signal generator. The method of claim 13, wherein the first input signal is a sense amplifier enable signal applied from the outside, the second input signal is an output enable signal applied from the outside, and the third input signal is an address transition detection signal applied from the outside. Output buffer enable circuit, characterized in that. The method of claim 12, wherein the enable signal generator A first signal generator for inputting a first input signal and a second input signal according to a first detection signal from the power level detector to generate an output buffer enable signal to the output buffer when a high power supply voltage is applied; And a second signal generator for inputting a second input signal and a third input signal according to the second detection signal from the power level detection unit to generate an output buffer enable signal to the output buffer when a low power supply voltage is applied. Output buffer enable circuit. 16. The apparatus of claim 15, wherein the first signal generator comprises the enable signal generator. Detecting means for detecting an output signal from the sense amplifier; Output means for generating an output buffer enable signal for enabling the output buffer according to the detection signal generated from the detection means and the first and second detection signals of the power level detection unit Buffer enable circuit. The method of claim 16, wherein the detecting means of the first signal generator Delay means for delaying the first input signal; A first inversion gate for inverting the output of the delay means; A NAND gate having two inputs of the first input signal and the output signal of the first inverting gate; A second inversion gate for inverting an output signal of the NAND gate; And a NOR gate generating a detection signal using the output signal of the second inverting gate and the second input signal as two inputs. 18. The apparatus of claim 17, wherein the generating means of the first signal generator is First and second MOS transistors having an output signal of the NOR gate of the detection means and a second detection signal from the power supply level detector, respectively, connected in series between a power supply voltage and a node; The output signal of the NOR gate of the detection means and the first detection signal of the power level detection unit are respectively applied to a gate and are composed of third and fourth MOS transistors connected between ground and the node, and the output buffer is input through the node. An output buffer enable circuit for generating an enable signal. The method of claim 15, wherein the second signal generating unit Detecting means for detecting an input of a third input signal; And a generating means for generating an output buffer enable signal to said output buffer by the output signal of said detection means and the first and second detection signals of said power level detection part. 20. The apparatus of claim 19, wherein the detection means of the second signal generator is Delay means for inverting a delay of the third input signal; A first NOR gate having two inputs of the third input signal and the output signal of the delay means; An inverting gate for inverting the output signal of the first NOR gate; A second NOR gate having two output signals of the inverted gate and the third input signal; An output buffer enable circuit comprising: a NOR gate having two output signals of the second NOR gate and a second input signal. 21. The apparatus of claim 20, wherein the generating means of the second signal generator is First and second MOS transistors having an output signal of a third NOR gate of the detection means and a first detection signal of the power level detection unit respectively applied to a gate and connected in series between a power supply voltage and a node; An output signal of the third NOA gate of the detection means and a second detection signal of the power level detection unit are respectively applied to the gate and are composed of third and fourth MOS transistors connected in series between the node and ground, and the output is performed through the node. An output buffer enable circuit for generating an output buffer enable signal for enabling a buffer.