KR940005692B1 - Data output driver of semiconductor memory device - Google Patents

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Description

Data output driver of semiconductor memory device

1 shows a data output driver of a conventional semiconductor memory device.

2 is a timing diagram for explaining the operation of FIG.

3 shows a data output driver of a semiconductor memory device according to the present invention.

4 shows a logic circuit diagram of the gating means of FIG.

5 is a timing diagram for explaining the operation of FIG.

The present invention relates to a semiconductor memory device, and more particularly, to a data output driver of a semiconductor memory device.

Typically, the data output of the dynamic random access memory has a data output driver for driving the output of the sense amplifier to the output terminal. The data output driver is a differential amplifier output signal (SAS, ) Is initially at "high" or "low" or mid-level (high impedance) and reads data from the memory cell to the "Data Output Enable Clock" when it is determined to be "high" or "low". Thereby buffering the signal to the output terminal Dout.

1 is a conventional data output driver, which outputs a power supply voltage supply terminal (Vcc), a ground voltage supply terminal (Vss), a data output terminal (Dout) 18, and a differential amplifier (not shown) of a sense amplifier. That is, the sense amplification signal SAS having a state of logic "1" or logic "0" And a data output driver control circuit 12 that is enabled by an input of a data output buffer enable clock ψOE (hereinafter referred to as an enable clock) to gate the two input signals and outputs the power supply voltage. Two N-MOS transistors M1 and M2 are connected in series between the terminal and the ground power supply terminal so that when two gate signals of the data output driver control signal are input to each gate, the voltage according to the logic of the two gate signals is applied. Inputting the drive means (15) for driving the data output terminal (18) through the serial connection node point (20) and the data output buffer enable clock (ψOE) to complete data output by the clock. The control voltage generating means 30 for generating the output data control pulse ψ DCP at the time point, and the predetermined voltage Vcc and the ground voltage (Vcc) by the power supply voltage terminal 14 and the ground terminal 16. Two N-MOS transistors (MU) (MD) are connected in series between Vss, and the high data generated when the output data control pulse (ψDCP) of the control pulse generating means is input to each gate of the transistor (MU) MD. And a third voltage generator circuit 31 for outputting an impedance voltage to the output terminal 18 through the series connection node 32.

The control pulse generating means 30 inverts the enable clock ψ OE and inputs an output of the inverted delay buffer 20, the output of the inverted delay buffer 20, and the enable clock ψ OE. And a negative logic gate 22 for outputting the output data control pulse? CP and a buffer 24 for buffering the output of the negative logic gate 22.

In the first intermediate current I ₃ , the N-MOS transistors MU and MD are simultaneously " turned on " by the output data control pulses ψDCP so that between the power supply voltage Vcc and the ground voltage Vss. DC current path is formed in the current flowing through.

2 is a timing diagram for explaining the operation of FIG.

ADD is the address, ψOE the enable clock, A and B are output from the data output driver, the control circuit (12), ψDCP the output data control pulse, Dout is output from the data output terminal, I ₃ is N Mohs transistor (MU) ( MD) is the current by operation.

Hang address in a conventional semiconductor memory device Becomes an active " low " to strobe the row address ROW (not shown). As shown in the second drawing, when the openings COL1 and COL2 are continuously input, the storage data of the memory cells (not shown) by addressing is accessed. Therefore, the lead data of the memory cell by the addressing is amplified by a sense amplifier (not shown) as described above with reference to FIG. Is input to the data output driver control circuit 12. At this time, an enable clock ψ OE is input to the data output driver control circuit 12.

The data output driver control circuit for inputting the enable clock ψOE may include an output signal SAS of a sense amplifier. ) Is outputted to the output terminals A and B by the clock? Therefore, the lead data by the open dress COL1 designation is input to the gates of the N-MOS transistors M1 and M2 by the enable clock ψOE, and at the voltage level of the high-impedance state of FIG. It is driven as 2a. Meanwhile, the enable clock ψ OE is input to the inverting delay unit 20 and the noble gate 22.

As described above, when the enable dress COL1 changes to the open dress COL2 while the data of the open dress COL1 is outputted, when the enable clock ψOE falls to "low" for a predetermined period, the output data control pulse. (ψDCP) is generated as the second degree. At this time, it is easy to detect the change of the open dress and enable the enable clock ψOE for a predetermined time by using an address transition detection (ATD) (not shown). Therefore, whenever the address changes, the output data control pulse? DCP is output from the NOA gate 22 and input to each gate of the N-MOS transistor MU MD.

Regardless of whether the output data voltage level of the output terminal 18 is " high " 2a or " low " 2b, while the output data control pulse? DCP is " high " (MD) is simultaneously "turned on" to form a DC current path (I ₃ ) between the power supply voltage (Vcc) and the ground voltage (Vss), resulting in a turn-on resistance ratio of the N-MOS transistor (MU) (MD) As a result, the voltage level of the output terminal 18 is formed to have the high-impedance state, that is, the voltage level at the time points t ₂ and t ₅ , and then outputs data as shown in the second degree.

However, in view of the trend of current semiconductor memory requiring high speed and low power consumption, the data output buffer of a semiconductor memory device having the same data output driver as the first diagram generates the following problems.

During the period in which the output data control pulse? DCP is "high", the N-MOS transistors MU and MD of the third voltage generator circuit 31 are independent of the previous data voltage level of the output terminal 18. Simultaneously " turned on " to form a DC current path I ₃ between the power supply voltage Vcc and the ground voltage Vss so that current flows instantaneously as in 2j and 2k of FIG. It is becoming.

Accordingly, an object of the present invention is to provide a data output driver of a semiconductor memory device, wherein the output level of the output data for a predetermined period of time when the data output driver is disabled is set to a minimum power consumption and a voltage level of high-impedance state for a minimum time. It is to provide a circuit for controlling.

The present invention for achieving the above object, the power supply voltage terminal 14, the ground voltage supply terminal 16, the data output terminal and the sense amplification signal (SAS) having a state of logic "1" or logic "0" And a data output driver control circuit 12 which is enabled by the input of a data output buffer enable clock (ψOE) to gating the two input signals, and between the power supply voltage terminal and the ground power supply terminal. Two N-MOS transistors M1 and M2 are connected in series, and when two gating signals of the data output driver control circuit are input to each gate, a voltage according to the logic of the two gating signals is inputted to the series connection node point ( 20) inputs the drive means 15 for driving to the data output terminal and the data output buffer enable clock ψ OE and generates an output data control pulse ψDCP at the time when the data output is completed by the clock. Two N-MOS transistors between the control voltage generating means 30 and the power supply voltage terminal and the ground terminal between a predetermined voltage Vcc and a ground voltage Vss. Is connected in series and the high-impedance voltage generated when the gating signal of the gating means 40 is input to the gates of the transistors MU and MD is connected to the series connection node 32. The third voltage generation circuit 31 outputs to the output terminal 18 and the output terminal and the output data through the () and generates the third voltage by generating the output data control pulse (ψDCP) of the control pulse generating means And gating means 40 for gating the transistors MU and MD of the circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 shows a data output driver according to the present invention, wherein the gating means 40 is connected to the output terminal 18 and the output data of the output terminal 18 and the control pulse generating means 30 are output. Only one of the N-MOS transistors MU and (MD) of the third voltage generator circuit 31 is turned on by the generation of the data control pulse ψDCP to raise the voltage level of the output stage 18 in a high-impedance state. Make voltage level.

In the configuration of FIG. 3, the output data control pulse ψDCP of the control pulse generating means 30 is the same pulse as the above-mentioned first degree control pulse ψDCP, and the series of the third voltage generating circuit 31 is in series. The connection output node 31 is connected to the serial connection node 20 of FIG.

4 is a configuration diagram of the gating means 40 of FIG. 3, in which 42, 46, and 48 are NAND gates, and 44 and 50 are negative gates. The gating means 40 is selected from the state in which the data value of the output terminal is "high" or "low" in a section in which the output data control pulse ψDCP of the control pulse generating means 40 is "high". The process of changing the voltage level of the output terminal to the voltage level of the high-impedance state by selectively turning on the transistors MU and MD of the voltage generator circuit will be described below.

i) When the previous data output voltage level of the output terminal 18 is "high",

When the output data control pulse ψDCP becomes "high" and the output level of the output terminal 18 is "high", the NAND gates 46 and 48 of FIG. 4 each have two input terminals. The control pulse? DCP is input and the output level " high " of the output terminal is respectively input to the other one, so that the outputs of the NAND gates 46 and 48 are " low ". The NAND gate 42 receives one of the two inputs of the control pulse ψDCP and the other receives the output of the NAND gate 46, “low”, and the output becomes “high”. The subgate 44 receives the output of the NAND gate 42 as an input and generates an output of "low", and the subgate 50 receives the output of the NAND gate 48 as an input and receives an output of "high". And the gating means 40 “turns off” the N-MOS transistor MU of the third voltage generator circuit 31 and “turns on” MD to raise the voltage level of the output terminal for a predetermined time. -Make the voltage level of the impedance state. In this case, power consumption of the third voltage generating circuit does not occur.

ii) when the previous data output voltage level of the output terminal is " low "

When the output data control pulse ψDCP becomes "high" and the output level of the output terminal 18 is "low", one of the two input terminals of the NAND gate 46 and 48 is the control pulse ( DCP) is input to each other, and the output level of the output terminal 18 is inputted to the other, and the output of the NAND gates 46 and 48 becomes “high”. One of the two inputs to the NAND gate 42 is the input of the control pulse ψDCP, and the other receives the output “high” of the NAND gate 46 as an input and the output becomes “low”.

The subgate 44 receives the output of the NAND gate 42 as an input and generates an output of "high", and the subgate 50 receives the output of the NAND gate 48 as an input and receives an output of "low". And the gating means 40 “turns on” the N-MOS transistor MU of the third voltage generator circuit 31 and “turns off” MD to turn the output terminal voltage high for a predetermined time. Make voltage level of impedance state. In this case, power consumption of the third voltage generating circuit occurs.

In this way, the gating means provided between the control pulse generating means 30 and the third voltage generating circuit 31 senses the previous output data voltage level of the output terminal 18 to output data control pulses of the control pulse generating means. When (ψDCP) is generated, by selectively " turning on " the N-MOS transistors MU and MD of the third voltage generator circuit 31, the generated power consumption is significantly reduced and the N of the third voltage generator circuit is also reduced. Selective turn-on of the MOS transistor results in speed improvement by reducing the voltage-level arrival time of the high-impedance state. 5 is a timing diagram for explaining the operation of FIG. ψOE is the enable clock, A and B are the outputs of the data output driver control circuit 12, ψDCP is the output data control pulse, Dout is the output of the data output terminal, and the current I ₄ is the N-MOS transistor MU. The "turn on" (MU) is "turned off" so that the current flows from the predetermined voltage Vcc of the power supply terminal 14 to the output terminal 18 and the current I ₅ is the N-MOS transistor MU "off". "MD" is " turned on " and is a current flowing from the output terminal 18 to the predetermined voltage Vss of the ground voltage supply terminal 16. " (MD) " Lead data of a memory cell by addressing is amplified by a sense amplifier (not shown) as described above with reference to FIG. ) Is input to the data output driver control circuit 12 of FIG. At this time, an enable clock ψ OE is input to the data output driver control circuit 12. The data output driver control circuit for inputting the enable clock ψOE may include an output signal SAS of a sense amplifier. ) Is output to the output terminals A and B by the clock? Therefore, the lead data by the open dress COL1 designation is input to the gates of the N-MOS transistors M1 and M2 by the enable clock ψOE, and at the voltage level of the high-impedance state of FIG. 5C. It is driven as 5a.

On the other hand, the enable clock ψ OE is input to the control pulse generating means 30, and outputs the output data control pulse ψDCP as described above in FIG. 1, and the gating means 40 is the output terminal 18. The voltage level of the previous output data is sensed by the control pulse (ψDCP) to selectively gate the N-MOS transistors (MU) and (MD), and due to the selective gating of the gating means 40, the output terminal The time point at which the high-impedance voltage level at (18) is reached at t ₁ and t ₄ is equal to the fifth degree. In addition, the selective gating causes the currents I ₄ and I ₅ to flow, where power consumption occurs only in the section in which the current I ₄ flows.

As described above, the present invention includes a gating means for sensing and selectively gating the previous data voltage level of the output terminal, thereby reducing the voltage level of the output terminal of the semiconductor memory device from the voltage level of the previous data output. By controlling the voltage level of high-impedance state at the time of, power consumption is low and high speed output is possible.

Claims (5)

A data output terminal connected to the output of the drive means having a driver control circuit for inputting a sense amplification signal and controlled by a data output buffer enable clock and a drive means for inputting the output of the driver control circuit to transmit output data; A control pulse generating means for inputting the data output buffer enable clock to generate an output data control pulse at a time point at which the data output by the clock is completed; and by the output data control pulse of the control pulse generating means. A data output driver of a semiconductor memory device having a third voltage generating means for outputting an impedance state voltage to the output terminal, wherein the third voltage generating means has a pull-up and pull-down transistor in series between a power supply terminal and a ground terminal. Connected and high by the gating signal of the gating means Receiving a third voltage generating circuit for outputting the voltage of the redundancy state to the data output terminal through the serial connection node and the output data control pulse of the control pulse generating means, by detecting the output data voltage level of the output terminal 3. A data output driver of a semiconductor memory device, comprising gating means for selectively gating pull-up and pull-down transistors of a voltage generating circuit. 2. The apparatus of claim 1, wherein the gating means receives the control pulse to turn on the pull-down transistor when the output data voltage level of the output terminal is " high ", and to turn off the pull-up transistor when the voltage level of the output terminal is " low ". Turn on " data output driver of a semiconductor memory device. A third connected to an output terminal and having a pull-up and pull-down transistor connected in series between a power supply terminal and a ground terminal to output a high-impedance voltage to the output terminal through the series connection node by a gating signal of a gating means; A voltage generating circuit, an output data means for supplying one potential voltage level of a binary logic level or another potential voltage level of the binary logic level to the output terminal, and a voltage level of the output data means being a binary logic level. A control means for generating a control signal before changing to a binary logic level different from the binary logic level in one state; and receiving the control signal of the control means to detect an output data voltage level of the output terminal to generate the third control logic. And gating means for selectively gating pull-up and pull-down transistors of the voltage generating circuit. The data output driver of the Physical Unit. 4. The gate of claim 3, wherein the gating means receives the control signal and " turns " the pull-down transistor when the output data voltage level of the output terminal is " high ", and " turns " the pull-up transistor when the voltage level of the output terminal is " low ". And a data output driver of a semiconductor memory device. A pull-up element for supplying a first power supply voltage to the data output terminal at the data "high" output, a pull-down element for supplying a second power supply voltage to the data output terminal at the data "low" output, and the data "high" Or power supply when the data is "high" or "low" driven by the pull-up element or pull-down element by holding the data at an output terminal at an arbitrary voltage between the first power supply voltage and the second power supply voltage immediately before the "low" output. A data output driver having noise reduction means for reducing voltage noise, wherein said noise reduction means is adapted to supply said data output terminal to said arbitrary voltage when all output states are "low" at the time of outputting said data "high". A pull-up element that couples the first power supply voltage to the data output terminal for raising; and when the output state is " high " And a pull-down element coupling a second power supply voltage to the data output terminal to lower the data output terminal to the arbitrary voltage.